April 2013 - U-Boot

[U-Boot] [PATCH v2] OMAP5: I2C: Enable i2c5 clocks
by Lubomir Popov 09 Apr '13

09 Apr '13

V2 fixes line wrap issue of the patch itself. I2C5 is used on all known OMAP5 hardware platforms, therefore enable. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- arch/arm/cpu/armv7/omap5/hw_data.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e5e41fd..5698876 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,7 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l4per_i2c5_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 -- 1.7.9.5

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[U-Boot] [PATCH] Exynos5: i2c: Fix read NACK handling and remove some redundancy
by Akshay Saraswat 09 Apr '13

09 Apr '13

From: Gabe Black <gabeblack(a)google.com> The exynos s3c24x0 i2c driver wouldn't do the right thing when a NACK was received on a read because it didn't attempt a read before waiting for the read to finish. Putting a call to ReadWriteByte in the NACK path fixed a problem where getting a NACK reading from a device would jam up the bus and prevent future accesses like probing from working. Because other than the ReadWriteByte call the NACK and normal paths were almost the same thing, and to avoid future instances of the NACK path not working because it's not exercised normally, this change also consolidates those two paths. Signed-off-by: Gabe Black <gabeblack(a)google.com> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- drivers/i2c/s3c24x0_i2c.c | 53 ++++++++++++++++------------------------------- 1 file changed, 18 insertions(+), 35 deletions(-) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index d2b4eb0..91298a7 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -366,21 +366,25 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, break; case I2C_READ: - if (result == I2C_OK) { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - writel(chip, &i2c->iicds); - /* send START */ - writel(readl(&i2c->iicstat) | I2C_START_STOP, - &i2c->iicstat); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); + { + int was_ok = (result == I2C_OK); + + writel(chip, &i2c->iicds); + /* resend START */ + writel(I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP, &i2c->iicstat); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + + if (was_ok || IsACK(i2c)) { i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ - if (i == data_len - 1) - writel(readl(&i2c->iiccon) - & ~I2CCON_ACKGEN, - &i2c->iiccon); + if (i == data_len - 1) { + writel(readl(&i2c->iiccon) & + ~I2CCON_ACKGEN, + &i2c->iiccon); + } ReadWriteByte(i2c); result = WaitForXfer(i2c); data[i] = readl(&i2c->iicds); @@ -388,35 +392,14 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); - writel(chip, &i2c->iicds); - /* send START */ - writel(readl(&i2c->iicstat) | I2C_START_STOP, - &i2c->iicstat); - result = WaitForXfer(i2c); - - if (IsACK(i2c)) { - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) - writel(readl(&i2c->iiccon) & - ~I2CCON_ACKGEN, - &i2c->iiccon); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - data[i] = readl(&i2c->iicds); - i++; - } - } else { - result = I2C_NACK; - } + result = I2C_NACK; } /* send STOP */ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(i2c); break; + } default: debug("i2c_transfer: bad call\n"); -- 1.8.0

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[U-Boot] [PATCH v2] OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
by Lubomir Popov 09 Apr '13

09 Apr '13

V2 fixes line wrap issue of the patch itself. This fix is needed (but not sufficient) for USB EHCI operation. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- arch/arm/cpu/armv7/omap5/hw_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ced274e..e5e41fd 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void) }; u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -411,7 +412,6 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, - (*prcm)->cm_l3init_hsusbtll_clkctrl, (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 -- 1.7.9.5

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 09 Apr '13

09 Apr '13

Hello, The following changes since commit 8bf3c322856f42d4db8acd7fa4f2a17898564064: logo: update to the new logo for ATMEL (2013-04-05 21:49:37 +0200) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to dd2445ec1b839a5ca61ff8438a5b7aebb21b7986: omap5_common.h: Use fallback CONFIG_SYS_BAUDRATE_TABLE (2013-04-08 11:40:59 -0400) ---------------------------------------------------------------- Andreas Bießmann (6): omap3/cpu.h: add BCH support asm/omap_gpmc.h: consolidate common defines omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernel omap_gpmc: change nandecc command omap_gpmc: add support for hw assisted BCH8 tricorder: enable hw assisted BCH8 in SPL and u-boot Bin Liu (2): musb: am335x: disable bulk split-combine feature musb: set MUSB speed based on CONFIG Hunter, Jon (4): omap2420-h4: Fix DRAM initialisation omap2420-h4: Fix booting from NOR flash omap2420-h4: Add device tree support omap2420-h4: Fix get_timer() and CONFIG_SYS_HZ Lars Poeschel (1): pcm051: Enable DDR PHY dynamic power down bit Lokesh Vutla (1): arm: omap4: Fix SDRAM AUTO DETECTION Lubomir Popov (1): OMAP: Fix copy-paste bug that did not enable UART4 clock Manfred Huber (1): omap3_beagle: Flush UART3 xmit on enable if TEMT is broken Nishanth Menon (1): omap5: Allow use of a plain text env file SRICHARAN R (4): ARM: OMAP5: Rename omap5_evm to omap5_uevm ARM: OMAP5: Set fdt_high to enable booting with Device tree ARM: OMAP4/5: Change the default boot command to work with device tree ARM: OMAP4/5: Make bootz as the default boot command Tom Rini (5): am335x: Enable MMC1 clock doc/feature-removal-schedule.txt: Add CONFIG_SYS_(CLOCKS|PADS)_ENABLE_ALL OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMC omap5_uevm.h: Move uEVM-specific choices to omap5_uevm.h omap5_common.h: Use fallback CONFIG_SYS_BAUDRATE_TABLE README | 8 - arch/arm/cpu/arm1136/omap24xx/timer.c | 8 +- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 5 + arch/arm/cpu/armv7/am33xx/elm.c | 2 +- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 +- arch/arm/cpu/armv7/omap-common/emif-common.c | 29 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 10 +- arch/arm/cpu/armv7/omap3/board.c | 31 +- arch/arm/cpu/armv7/omap4/emif.c | 1 - arch/arm/cpu/armv7/omap5/emif.c | 1 - arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 58 +--- arch/arm/include/asm/arch-am33xx/spl.h | 3 + arch/arm/include/asm/arch-am33xx/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap24xx/omap2420.h | 6 +- arch/arm/include/asm/arch-omap3/cpu.h | 6 + arch/arm/include/asm/arch-omap3/omap_gpmc.h | 68 +--- arch/arm/include/asm/arch-omap3/spl.h | 3 + arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap4/omap.h | 1 - arch/arm/include/asm/arch-omap4/spl.h | 2 + arch/arm/include/asm/arch-omap5/omap.h | 1 - arch/arm/include/asm/arch-omap5/spl.h | 2 + arch/arm/include/asm/emif.h | 1 - arch/arm/include/asm/omap_gpmc.h | 87 +++++ board/isee/igep00x0/igep00x0.c | 2 +- board/overo/overo.c | 2 +- board/phytec/pcm051/board.c | 3 +- board/ti/omap2420h4/config.mk | 4 +- board/ti/omap2420h4/mem.c | 13 - board/ti/omap2420h4/omap2420h4.c | 24 +- board/ti/{omap5_evm => omap5_uevm}/Makefile | 0 board/ti/{omap5_evm => omap5_uevm}/evm.c | 0 board/ti/{omap5_evm => omap5_uevm}/mux_data.h | 0 boards.cfg | 2 +- doc/README.omap3 | 28 ++ doc/feature-removal-schedule.txt | 16 + drivers/mtd/nand/omap_gpmc.c | 424 +++++++++++++++++------- drivers/serial/ns16550.c | 18 +- drivers/usb/musb-new/musb_core.c | 7 + drivers/usb/musb-new/musb_uboot.c | 2 +- include/configs/am335x_evm.h | 1 + include/configs/dra7xx_evm.h | 2 + include/configs/igep00x0.h | 3 - include/configs/omap2420h4.h | 5 +- include/configs/omap4_common.h | 22 +- include/configs/omap5_common.h | 51 ++- include/configs/{omap5_evm.h => omap5_uevm.h} | 18 + include/configs/tricorder.h | 13 +- lib/Makefile | 2 +- 49 files changed, 672 insertions(+), 331 deletions(-) create mode 100644 arch/arm/include/asm/omap_gpmc.h rename board/ti/{omap5_evm => omap5_uevm}/Makefile (100%) rename board/ti/{omap5_evm => omap5_uevm}/evm.c (100%) rename board/ti/{omap5_evm => omap5_uevm}/mux_data.h (100%) rename include/configs/{omap5_evm.h => omap5_uevm.h} (70%) Andreas' changes came well before the merge window, Everything else is a bugfix of some sort or another or part of keeping platforms still useful with later kernel releases. -- Tom

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[U-Boot] which u-boot build config to choose for kirkwood?
by JPT 08 Apr '13

08 Apr '13

Hi, I finally succeeded in booting my kirkwood board from UART. But this did not help. The Netgear uboot 1.1.4 still hangs after loading the network hardware. Since I was messing with the uboot-env before it broke, this is most likely the cause of the problems. To access the uboot-env I've got two alternatives I can think of: - Boot a current mainline U-boot to get the uboot console and access to the uboot-env in NAND. - Boot into (kirkwood?) debug console using the magic bytes. I once achieved to get it, but since I don't. And I don't know anything about how to use it. (any hints?) Kirkwood UART boot is integrated into the current mainline uboot, but debug console isn't, right? Well, I decided to build uboot myself. To access uboot env in NAND I only need working: CPU, NAND, RAM, UART. Correct? Could you please give some hints on how to choose the right config? Most detailed hw info I got from: http://natisbad.org/NAS CPU: Marvell 82F6282 SoC (aka ARMADA 300) from Kirkwood family. ARMv5TE-compatible cat /proc/cpuinfo Processor : Feroceon 88FR131 rev 1 (v5l) Features : swp half thumb fastmult edsp CPU implementer : 0x56 CPU architecture: 5TE CPU variant : 0x2 CPU part : 0x131 CPU revision : 1 Hardware : Feroceon-KW RAM 2x 128MB DDR3 1333 Hynix H5TQ1G83DFR-H9C @ 533Mhz? NAND Hynix H27U1G8F2BTR UART integrated into Marvell SoC I am not sure about this one, and if I need it: ATMEL AT25F512B-SSH 512 Kilobit SPI flash. btw, is uboot-env 1.1.4 compatible to recent uboot? thanks, Jan

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[U-Boot] [PATCH 1/1] TPM: STMicroelectronics u-boot driver I2C
by Mathias leblanc 08 Apr '13

08 Apr '13

From: Mathias Leblanc <mathias.leblanc(a)st.com> * STMicroelectronics version 1.2.0, Copyright (C) 2013 * STMicroelectronics comes with ABSOLUTELY NO WARRANTY. * This is free software, and you are welcome to redistribute it * under certain conditions. This is the driver for TPM chip from ST Microelectronics. If you have a TPM security chip from STMicroelectronics working with an I2C, read the README file and add the correct defines regarding the tpm in the configuration file of your board. This file is located in include/configs/your_board.h The driver will be accessible from within uboot terminal. Signed-off-by: Mathias Leblanc <mathias.leblanc(a)st.com> --- Makefile | 2 +- README | 12 + common/cmd_tpm.c | 176 ++++++++++++ drivers/tpm/Makefile | 1 + drivers/tpm/compatibility.h | 52 ++++ drivers/tpm/tis_i2c.c | 211 ++++++++++++++ drivers/tpm/tpm.c | 472 +++++++++++++++++++++++++++++++ drivers/tpm/tpm.h | 164 +++++++++++ drivers/tpm/tpm_i2c_st.c | 601 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 8 + include/tpm.h | 16 + 11 files changed, 1714 insertions(+), 1 deletions(-) create mode 100644 drivers/tpm/compatibility.h create mode 100644 drivers/tpm/tis_i2c.c create mode 100644 drivers/tpm/tpm.c create mode 100644 drivers/tpm/tpm.h create mode 100644 drivers/tpm/tpm_i2c_st.c diff --git a/Makefile b/Makefile index 12763ce..ef954a4 100644 --- a/Makefile +++ b/Makefile @@ -314,7 +314,7 @@ endif LIBS-y += drivers/rtc/librtc.o LIBS-y += drivers/serial/libserial.o LIBS-y += drivers/sound/libsound.o -LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o +LIBS-$(CONFIG_TPM) += drivers/tpm/libtpm.o LIBS-y += drivers/twserial/libtws.o LIBS-y += drivers/usb/eth/libusb_eth.o LIBS-y += drivers/usb/gadget/libusb_gadget.o diff --git a/README b/README index 7f2506a..0e497d1 100644 --- a/README +++ b/README @@ -1210,6 +1210,18 @@ The following options need to be configured: to. Contemporary x86 systems usually map it at 0xfed40000. + CONFIG_ST_TPM_I2C + Define to compile the ST TPM I2C DRIVER. + + CONFIG_TPM_I2C_BUS + Define the bus number of the board. + + CONFIG_TPM_I2C_ADDR + Define the address of the TPM. + + CONFIG_CMD_TPM + Define to use some TPM u-boot commands. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/common/cmd_tpm.c b/common/cmd_tpm.c index 0970a6f..5d4f485 100644 --- a/common/cmd_tpm.c +++ b/common/cmd_tpm.c @@ -158,6 +158,182 @@ U_BOOT_CMD(tpm, MAX_TRANSACTION_SIZE, 1, do_tpm, "device and read the response" ); +static int do_tpm_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 tpm_buffer[MAX_TRANSACTION_SIZE]; + u32 write_size, read_size; + char *p; + int rv = -1; + argc -= 1; + argv += 1; + u8 response[MAX_TRANSACTION_SIZE]; + u32 rlength = MAX_TRANSACTION_SIZE; + + u8 Startup[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x99, + 0x00, 0x01 + }; + + u8 SelfTestFull[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x50 + }; + + u8 ReadPcr17[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0e, + 0x00, 0x00, 0x00, 0x15, + 0x00, 0x00, 0x00, 0x11 + }; + + for (write_size = 0; write_size < argc; write_size++) { + u32 datum = simple_strtoul(argv[write_size], &p, 0); + if (*p || (datum > 0xff)) { + printf("\n%s: bad data value\n\n", argv[write_size]); + cmd_usage(cmdtp); + return rv; + } + tpm_buffer[write_size] = (u8)datum; + } + + if (tis_init()) { + puts("tis_init() failed!\n"); + return -1; + } + + if (tis_open()) { + puts("tis_open() failed!\n"); + return -1; + } + + rv = tis_sendrecv(Startup, sizeof(Startup), &response, &rlength); + if (rv) { + printf("tpm test Startup failed\n"); + CHECK(tis_close()); + } + + rv = tis_sendrecv(SelfTestFull, sizeof(SelfTestFull), &response, + &rlength); + if (rv) { + printf("tpm test SelfTestFull failed\n"); + CHECK(tis_close()); + } + + if (!tis_sendrecv(ReadPcr17, sizeof(ReadPcr17), &response, + &read_size)) { + int i; + puts("TPM Read PCR 17:\n"); + for (i = 10; i < read_size; i++) + printf(" %2.2x", response[i]); + puts("\n"); + rv = 0; + } else { + printf("tpm test ReadPcr17 failed\n"); + CHECK(tis_close()); + } + + read_size = sizeof(tpm_buffer); + if (!tis_sendrecv_hash(tpm_buffer, write_size, tpm_buffer, + &read_size)) { + int i; + puts("Got TPM Hash response:\n"); + for (i = 0; i < read_size; i++) + printf(" %2.2x", tpm_buffer[i]); + puts("\n"); + rv = 0; + } else { + puts("tpm hash command failed\n"); + } + + if (!tis_sendrecv(ReadPcr17, sizeof(ReadPcr17), &response, + &read_size)) { + int i; + puts("TPM Read PCR 17 after hash:\n"); + for (i = 10; i < read_size; i++) + printf(" %2.2x", response[i]); + puts("\n"); + rv = 0; + } else { + printf("tpm test ReadPcr17 failed\n"); + CHECK(tis_close()); + } + + if (tis_close()) { + puts("tis_close() failed!\n"); + rv = -1; + } + + return rv; +} + + +U_BOOT_CMD(tpm_hash, MAX_TRANSACTION_SIZE, 1, do_tpm_hash, + "<byte> [<byte> ...] - write data to hash and read response", + "send arbitrary data to the TPM " + "device and read the response." + "ex: tpm 53 01 75 06 00 08 24 05 00 08 00 01" +); + +static int do_tpm_get_flag(void) +{ + int rv = 0; + u8 response[MAX_TRANSACTION_SIZE]; + u32 rlength = MAX_TRANSACTION_SIZE; + + u8 Startup[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x99, + 0x00, 0x01 + }; + u8 SelfTestFull[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x0a, + 0x00, 0x00, 0x00, 0x50 + }; + u8 GetPermFlags[] = { + 0x00, 0xc1, + 0x00, 0x00, 0x00, 0x16, + 0x00, 0x00, 0x00, 0x65, + 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x01, 0x08 + }; + + + CHECK(tis_init()); + + + CHECK(tis_open()); + rv = tis_sendrecv(Startup, sizeof(Startup), response, &rlength); + if (rv) { + printf("tpm test Startup failed\n"); + CHECK(tis_close()); + } + rv = tis_sendrecv(SelfTestFull, sizeof(SelfTestFull), response, + &rlength); + if (rv) { + printf("tpm test SelfTestFull failed\n"); + CHECK(tis_close()); + } + rv = tis_sendrecv(GetPermFlags, sizeof(GetPermFlags), response, + &rlength); + if (rv) { + printf("tpm test GetPermFlags failed\n"); + CHECK(tis_close()); + } + CHECK(tis_close()); + return rv; +} + + +U_BOOT_CMD(tpm_get_flag, 1, 1, do_tpm_get_flag, + "start tpm get flag command", "" +); + static int do_tpm_stress(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index be11c8b..802b54e 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -24,6 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libtpm.o COBJS-$(CONFIG_GENERIC_LPC_TPM) = generic_lpc_tpm.o +COBJS-$(CONFIG_ST_TPM_I2C) = tis_i2c.o tpm.o tpm_i2c_st.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/tpm/compatibility.h b/drivers/tpm/compatibility.h new file mode 100644 index 0000000..c68a855 --- /dev/null +++ b/drivers/tpm/compatibility.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 Infineon Technologies + * + * Authors: + * Peter Huewe <huewe.external(a)infineon.com> + * + * Version: 2.1.1 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _COMPATIBILITY_H_ +#define _COMPATIBILITY_H_ + +/* all includes from U-Boot */ +#include <linux/types.h> +#include <linux/unaligned/be_byteshift.h> +#include <asm-generic/errno.h> +#include <compiler.h> +#include <common.h> + +/* extended error numbers from linux (see errno.h) */ +#define ECANCELED 125 /* Operation Canceled */ + +#define msleep(t) udelay((t)*1000) + +/* Timer frequency. Corresponds to msec timer resolution*/ +#define HZ 1000 + + +#define dev_dbg(dev, format, arg...) debug(format, ##arg) +#define dev_err(dev, format, arg...) printf(format, ##arg) +#define dev_info(dev, format, arg...) debug(format, ##arg) +#define dbg_printf debug + +#endif diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c new file mode 100644 index 0000000..a494608 --- /dev/null +++ b/drivers/tpm/tis_i2c.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <config.h> +#include <common.h> +#include <i2c.h> +#include "tpm.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Define in board config */ +#ifndef CONFIG_TPM_I2C_BUS + #define CONFIG_TPM_I2C_BUS 0 + #define CONFIG_TPM_I2C_ADDR 0 +#endif + +/* TPM configuration */ +struct tpm { + int i2c_bus; + int slave_addr; + char inited; + int old_bus; +} tpm; + + +static int tpm_select(void) +{ + int ret; + + tpm.old_bus = i2c_get_bus_num(); + if (tpm.old_bus != tpm.i2c_bus) { + ret = i2c_set_bus_num(tpm.i2c_bus); + if (ret) { + debug("%s: Fail to set i2c bus %d\n", __func__, + tpm.i2c_bus); + return -1; + } + } + return 0; +} + +static int tpm_deselect(void) +{ + int ret; + + if (tpm.old_bus != i2c_get_bus_num()) { + ret = i2c_set_bus_num(tpm.old_bus); + if (ret) { + debug("%s: Fail to restore i2c bus %d\n", + __func__, tpm.old_bus); + return -1; + } + } + tpm.old_bus = -1; + return 0; +} + +/** + * Decode TPM configuration. + * + * @param dev Returns a configuration of TPM device + * @return 0 if ok, -1 on error + */ +static int tpm_decode_config(struct tpm *dev) +{ +#ifdef CONFIG_OF_CONTROL + const void *blob = gd->fdt_blob; + int node, parent; + int i2c_bus; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM); + if (node < 0) { + debug("%s: Node not found\n", __func__); + return -1; + } + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Cannot find node parent\n", __func__); + return -1; + } + i2c_bus = i2c_get_bus_num_fdt(blob, parent); + if (i2c_bus < 0) + return -1; + dev->i2c_bus = i2c_bus; + dev->slave_addr = fdtdec_get_addr(blob, node, "reg"); +#else + dev->i2c_bus = CONFIG_TPM_I2C_BUS; + dev->slave_addr = CONFIG_TPM_I2C_ADDR; +#endif + return 0; +} + +/* Methods used by cmd_tpm */ +int tis_init(void) +{ + if (tpm.inited) + return 0; + if (tpm_decode_config(&tpm)) + return -1; + if (tpm_select()) + return -1; + /* + * Probe TPM twice; the first probing might fail because TPM is asleep, + * and the probing can wake up TPM. + */ + if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) { + debug("%s: fail to probe i2c addr 0x%x\n", __func__, + tpm.slave_addr); + return -1; + } + tpm_deselect(); + tpm.inited = 1; + return 0; +} + +int tis_open(void) +{ + int rc; + if (!tpm.inited) + return -1; + + if (tpm_select()) + return -1; + + rc = tpm_open(tpm.slave_addr); + tpm_deselect(); + + return rc; +} + +int tis_close(void) +{ + if (!tpm.inited) + return -1; + + if (tpm_select()) + return -1; + + tpm_close(); + + tpm_deselect(); + + return 0; +} + +int tis_sendrecv_hash(const uint8_t *sendbuf, size_t sbuf_size, + uint8_t *recvbuf, size_t *rbuf_len) +{ + int len; + uint8_t buf[TPM_BUFSIZE]; + + if (!tpm.inited) + return -1; + + if (sizeof(buf) < sbuf_size) + return -1; + + memcpy(buf, sendbuf, sbuf_size); + + if (tpm_select()) + return -1; + + len = tpm_transmit_hash(buf, sbuf_size); + + tpm_deselect(); + + if (len < 10) { + *rbuf_len = 0; + return -1; + } + + memcpy(recvbuf, buf, len); + *rbuf_len = len; + + return 0; +} + +int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, + uint8_t *recvbuf, size_t *rbuf_len) +{ + int len; + uint8_t buf[TPM_BUFSIZE]; + + if (!tpm.inited) + return -1; + + if (sizeof(buf) < sbuf_size) + return -1; + + memcpy(buf, sendbuf, sbuf_size); + + if (tpm_select()) + return -1; + + len = tpm_transmit(buf, sbuf_size); + + tpm_deselect(); + + if (len < 10) { + *rbuf_len = 0; + return -1; + } + + memcpy(recvbuf, buf, len); + *rbuf_len = len; + + return 0; +} diff --git a/drivers/tpm/tpm.c b/drivers/tpm/tpm.c new file mode 100644 index 0000000..3f4f66e --- /dev/null +++ b/drivers/tpm/tpm.c @@ -0,0 +1,472 @@ +/* + * Copyright (C) 2011 Infineon Technologies + * + * Authors: + * Peter Huewe <huewe.external(a)infineon.com> + * + * Description: + * Device driver for TCG/TCPA TPM (trusted platform module). + * Specifications at www.trustedcomputinggroup.org + * + * It is based on the Linux kernel driver tpm.c from Leendert van + * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. + * + * Version: 2.1.1 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <malloc.h> +#include "tpm.h" + +/* global structure for tpm chip data */ +struct tpm_chip g_chip; + +enum tpm_duration { + TPM_SHORT = 0, + TPM_MEDIUM = 1, + TPM_LONG = 2, + TPM_UNDEFINED, +}; + +#define TPM_MAX_ORDINAL 243 +#define TPM_MAX_PROTECTED_ORDINAL 12 +#define TPM_PROTECTED_ORDINAL_MASK 0xFF + +/* + * Array with one entry per ordinal defining the maximum amount + * of time the chip could take to return the result. The ordinal + * designation of short, medium or long is defined in a table in + * TCG Specification TPM Main Part 2 TPM Structures Section 17. The + * values of the SHORT, MEDIUM, and LONG durations are retrieved + * from the chip during initialization with a call to tpm_get_timeouts. + */ +static const u8 tpm_protected_ordinal_duration[TPM_MAX_PROTECTED_ORDINAL] = { + TPM_UNDEFINED, /* 0 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 5 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 10 */ + TPM_SHORT, +}; + +static const u8 tpm_ordinal_duration[TPM_MAX_ORDINAL] = { + TPM_UNDEFINED, /* 0 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 5 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 10 */ + TPM_SHORT, + TPM_MEDIUM, + TPM_LONG, + TPM_LONG, + TPM_MEDIUM, /* 15 */ + TPM_SHORT, + TPM_SHORT, + TPM_MEDIUM, + TPM_LONG, + TPM_SHORT, /* 20 */ + TPM_SHORT, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_SHORT, /* 25 */ + TPM_SHORT, + TPM_MEDIUM, + TPM_SHORT, + TPM_SHORT, + TPM_MEDIUM, /* 30 */ + TPM_LONG, + TPM_MEDIUM, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, /* 35 */ + TPM_MEDIUM, + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_MEDIUM, /* 40 */ + TPM_LONG, + TPM_MEDIUM, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, /* 45 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_LONG, + TPM_MEDIUM, /* 50 */ + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 55 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_MEDIUM, /* 60 */ + TPM_MEDIUM, + TPM_MEDIUM, + TPM_SHORT, + TPM_SHORT, + TPM_MEDIUM, /* 65 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 70 */ + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 75 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_LONG, /* 80 */ + TPM_UNDEFINED, + TPM_MEDIUM, + TPM_LONG, + TPM_SHORT, + TPM_UNDEFINED, /* 85 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 90 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, /* 95 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_MEDIUM, /* 100 */ + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 105 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 110 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, /* 115 */ + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_LONG, /* 120 */ + TPM_LONG, + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_SHORT, + TPM_SHORT, /* 125 */ + TPM_SHORT, + TPM_LONG, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, /* 130 */ + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_SHORT, + TPM_MEDIUM, + TPM_UNDEFINED, /* 135 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 140 */ + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 145 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 150 */ + TPM_MEDIUM, + TPM_MEDIUM, + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, /* 155 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 160 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 165 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_LONG, /* 170 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 175 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_MEDIUM, /* 180 */ + TPM_SHORT, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_MEDIUM, /* 185 */ + TPM_SHORT, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 190 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 195 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 200 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, + TPM_SHORT, /* 205 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_MEDIUM, /* 210 */ + TPM_UNDEFINED, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_MEDIUM, + TPM_UNDEFINED, /* 215 */ + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, + TPM_SHORT, /* 220 */ + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_SHORT, + TPM_UNDEFINED, /* 225 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 230 */ + TPM_LONG, + TPM_MEDIUM, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, /* 235 */ + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_UNDEFINED, + TPM_SHORT, /* 240 */ + TPM_UNDEFINED, + TPM_MEDIUM, +}; + +/* + * Returns max number of milliseconds to wait + */ +unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal) +{ + int duration_idx = TPM_UNDEFINED; + int duration = 0; + + if (ordinal < TPM_MAX_ORDINAL) + duration_idx = tpm_ordinal_duration[ordinal]; + else if ((ordinal & TPM_PROTECTED_ORDINAL_MASK) < + TPM_MAX_PROTECTED_ORDINAL) + duration_idx = + tpm_protected_ordinal_duration[ordinal & + TPM_PROTECTED_ORDINAL_MASK]; + + if (duration_idx != TPM_UNDEFINED) + duration = chip->vendor.duration[duration_idx]; + if (duration <= 0) + return 2 * 60 * HZ; /*two minutes timeout*/ + else + return duration; +} + +ssize_t tpm_transmit_hash(const unsigned char *buf, size_t bufsiz) +{ + ssize_t rc; + u32 count, ordinal; + unsigned long start, stop; + + struct tpm_chip *chip = &g_chip; + + rc = chip->vendor.send_hash(chip, (u8 *) buf, bufsiz); + if (rc < 0) { + dev_err(chip->dev, "tpm_transmit: tpm_send: error %zd\n", rc); + goto out; + } + +out_recv: + + dbg_printf("out_recv: reading response...\n"); + rc = chip->vendor.recv(chip, (u8 *) buf, TPM_BUFSIZE); + if (rc < 0) + dev_err(chip->dev, "tpm_transmit: tpm_recv: error %zd\n", rc); +out: + return rc; +} + +ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz) +{ + ssize_t rc; + u32 count, ordinal; + unsigned long start, stop; + + struct tpm_chip *chip = &g_chip; + + /* switch endianess: big->little */ + count = get_unaligned_be32(buf + TPM_CMD_SIZE_BYTE); + ordinal = get_unaligned_be32(buf + TPM_CMD_ORDINAL_BYTE); + + if (count == 0) { + dev_err(chip->dev, "no data\n"); + return -ENODATA; + } + if (count > bufsiz) { + dev_err(chip->dev, + "invalid count value %x %zx\n", count, bufsiz); + return -E2BIG; + } + + rc = chip->vendor.send(chip, (u8 *) buf, count); + if (rc < 0) { + dev_err(chip->dev, "tpm_transmit: tpm_send: error %zd\n", rc); + goto out; + } + + if (chip->vendor.irq) + goto out_recv; + + start = get_timer(0); + stop = tpm_calc_ordinal_duration(chip, ordinal); + do { + dbg_printf("waiting for status...\n"); + u8 status = chip->vendor.status(chip); + if ((status & chip->vendor.req_complete_mask) == + chip->vendor.req_complete_val) { + dbg_printf("...got it;\n"); + goto out_recv; + } + + if ((status == chip->vendor.req_canceled)) { + dev_err(chip->dev, "Operation Canceled\n"); + rc = -ECANCELED; + goto out; + } + msleep(TPM_TIMEOUT); + } while (get_timer(start) < stop); + + chip->vendor.cancel(chip); + dev_err(chip->dev, "Operation Timed out\n"); + rc = -ETIME; + goto out; + +out_recv: + + dbg_printf("out_recv: reading response...\n"); + rc = chip->vendor.recv(chip, (u8 *) buf, TPM_BUFSIZE); + if (rc < 0) + dev_err(chip->dev, "tpm_transmit: tpm_recv: error %zd\n", rc); +out: + return rc; +} + +enum tpm_capabilities { + TPM_CAP_PROP = cpu_to_be32(5), +}; + +enum tpm_sub_capabilities { + TPM_CAP_PROP_TIS_TIMEOUT = cpu_to_be32(0x115), + TPM_CAP_PROP_TIS_DURATION = cpu_to_be32(0x120), +}; + +struct tpm_chip *tpm_register_hardware(const struct tpm_vendor_specific *entry) +{ + struct tpm_chip *chip; + + /* Driver specific per-device data */ + chip = &g_chip; + memcpy(&chip->vendor, entry, sizeof(struct tpm_vendor_specific)); + chip->is_open = 1; + + return chip; +} + +int tpm_open(uint32_t dev_addr) +{ + int rc; + if (g_chip.is_open) + return -EBUSY; + rc = tpm_vendor_init(dev_addr); + if (rc < 0) + g_chip.is_open = 0; + return rc; +} + +void tpm_close(void) +{ + if (g_chip.is_open) { + tpm_vendor_cleanup(&g_chip); + g_chip.is_open = 0; + } +} diff --git a/drivers/tpm/tpm.h b/drivers/tpm/tpm.h new file mode 100644 index 0000000..151c584 --- /dev/null +++ b/drivers/tpm/tpm.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2011 Infineon Technologies + * + * Authors: + * Peter Huewe <huewe.external(a)infineon.com> + * + * Version: 2.1.1 + * + * Description: + * Device driver for TCG/TCPA TPM (trusted platform module). + * Specifications at www.trustedcomputinggroup.org + * + * It is based on the Linux kernel driver tpm.c from Leendert van + * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TPM_H_ +#define _TPM_H_ + +#include "compatibility.h" + +enum tpm_timeout { + TPM_TIMEOUT = 5, /* msecs */ +}; + +/* Size of external transmit buffer (used in tpm_transmit)*/ +#define TPM_BUFSIZE 4096 +#define TPM_ERROR_SIZE 10 +#define TPM_HEADER_SIZE 10 + +/* Index of fields in TPM command buffer */ +#define TPM_CMD_SIZE_BYTE 2 +#define TPM_CMD_ORDINAL_BYTE 6 + +/* Index of Count field in TPM response buffer */ +#define TPM_RSP_SIZE_BYTE 2 +#define TPM_RSP_RC_BYTE 6 + +struct tpm_chip; + +struct tpm_vendor_specific { + const u8 req_complete_mask; + const u8 req_complete_val; + const u8 req_canceled; + int irq; + int (*recv) (struct tpm_chip *, u8 *, size_t); + int (*send) (struct tpm_chip *, u8 *, size_t); + int (*send_hash) (struct tpm_chip *, u8 *, size_t); + void (*cancel) (struct tpm_chip *); + u8 (*status) (struct tpm_chip *); + int locality; + unsigned long timeout_a, timeout_b, timeout_c, timeout_d; /* msec */ + unsigned long duration[3]; /* msec */ +}; + +struct tpm_chip { + int is_open; + struct tpm_vendor_specific vendor; + /* testing */ + u8 dev; +}; + +struct tpm_input_header { + __be16 tag; + __be32 length; + __be32 ordinal; +} __attribute__ ((packed)); + +struct tpm_output_header { + __be16 tag; + __be32 length; + __be32 return_code; +} __attribute__ ((packed)); + +struct timeout_t { + __be32 a; + __be32 b; + __be32 c; + __be32 d; +} __attribute__ ((packed)); + +struct duration_t { + __be32 tpm_short; + __be32 tpm_medium; + __be32 tpm_long; +} __attribute__ ((packed)); + +typedef union { + struct timeout_t timeout; + struct duration_t duration; +} cap_t; + +struct tpm_getcap_params_in { + __be32 cap; + __be32 subcap_size; + __be32 subcap; +} __attribute__ ((packed)); + +struct tpm_getcap_params_out { + __be32 cap_size; + cap_t cap; +} __attribute__ ((packed)); + +typedef union { + struct tpm_input_header in; + struct tpm_output_header out; +} tpm_cmd_header; + +typedef union { + struct tpm_getcap_params_out getcap_out; + struct tpm_getcap_params_in getcap_in; +} tpm_cmd_params; + +struct tpm_cmd_t { + tpm_cmd_header header; + tpm_cmd_params params; +} __attribute__ ((packed)); + + +/* ---------- Interface for TPM vendor ------------ */ + +extern struct tpm_chip *tpm_register_hardware( + const struct tpm_vendor_specific *); + +extern int tpm_vendor_init(uint32_t dev_addr); + +extern void tpm_vendor_cleanup(struct tpm_chip *chip); + +/* ---------- Interface for TDDL ------------------- */ + +/* + * if dev_addr != 0 - redefines TPM device address + * Returns < 0 on error, 0 on success. + */ +extern int tpm_open(uint32_t dev_addr); + +extern void tpm_close(void); + +/* + * Transmit bufsiz bytes out of buf to TPM and get results back in buf, too. + * Returns < 0 on error, 0 on success. + */ +extern ssize_t tpm_transmit(const unsigned char *buf, size_t bufsiz); + +#endif diff --git a/drivers/tpm/tpm_i2c_st.c b/drivers/tpm/tpm_i2c_st.c new file mode 100644 index 0000000..cb716c5 --- /dev/null +++ b/drivers/tpm/tpm_i2c_st.c @@ -0,0 +1,601 @@ +/* + * STMicroelectronics TPM I2C UBOOT Linux driver for TPM ST33ZP24 + * Copyright (C) 2013 STMicroelectronics + * + * Description: + * Device driver for TCG/TCPA TPM (trusted platform module). + * Specifications at www.trustedcomputinggroup.org + * + * This device driver implements the TPM interface as defined in + * the TCG TPM Interface Spec version 1.2, revision 1.0 and the + * STMicroelectronics I2C Protocol Stack Specification version 1.2.0. + * + * It is based on the Linux kernel driver tpm.c from Leendert van + * Dorn, Dave Safford, Reiner Sailer, and Kyleen Hall. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation, version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * STMicroelectronics version 1.2.0, Copyright (C) 2013 + * STMicroelectronics comes with ABSOLUTELY NO WARRANTY. + * This is free software, and you are welcome to redistribute it + * under certain conditions. + * + * @Author: Mathias Leblanc tpmsupport(a)st.com + * + * @File: tpm_i2c_st.c + * + */ + +#include <common.h> +#include <i2c.h> +#include <linux/types.h> + +#include "compatibility.h" +#include "tpm.h" + +/* max. buffer size supported by our tpm */ +#ifdef TPM_BUFSIZE +#undef TPM_BUFSIZE +#endif + +#define MINOR_NUM_I2C 224 + +#define TPM_ACCESS (0x0) +#define TPM_STS (0x18) +#define TPM_HASH_END (0x20) +#define TPM_DATA_FIFO (0x24) +#define TPM_HASH_DATA (0x24) +#define TPM_HASH_START (0x28) +#define TPM_INTF_CAPABILITY (0x14) +#define TPM_INT_STATUS (0x10) +#define TPM_INT_ENABLE (0x08) + +#define TPM_DUMMY_BYTE 0xAA +#define TPM_WRITE_DIRECTION 0x80 +#define TPM_HEADER_SIZE 10 +#define TPM_BUFSIZE 2048 + +#define LOCALITY0 0 +#define LOCALITY4 4 + +struct st_tpm_hash { + int size; + u8 *data; +}; + +enum stm33zp24_access { + TPM_ACCESS_VALID = 0x80, + TPM_ACCESS_ACTIVE_LOCALITY = 0x20, + TPM_ACCESS_REQUEST_PENDING = 0x04, + TPM_ACCESS_REQUEST_USE = 0x02, +}; + +enum stm33zp24_status { + TPM_STS_VALID = 0x80, + TPM_STS_COMMAND_READY = 0x40, + TPM_STS_GO = 0x20, + TPM_STS_DATA_AVAIL = 0x10, + TPM_STS_DATA_EXPECT = 0x08, +}; + +enum stm33zp24_int_flags { + TPM_GLOBAL_INT_ENABLE = 0x80, + TPM_INTF_CMD_READY_INT = 0x080, + TPM_INTF_FIFO_AVALAIBLE_INT = 0x040, + TPM_INTF_WAKE_UP_READY_INT = 0x020, + TPM_INTF_LOC4SOFTRELEASE_INT = 0x008, + TPM_INTF_LOCALITY_CHANGE_INT = 0x004, + TPM_INTF_STS_VALID_INT = 0x002, + TPM_INTF_DATA_AVAIL_INT = 0x001, +}; + +enum tis_defaults { + TIS_SHORT_TIMEOUT = 750, /* ms */ + TIS_LONG_TIMEOUT = 2000, /* 2 sec */ +}; + +struct tpm_i2c_ST_dev { + uint addr; + u8 buf[TPM_BUFSIZE]; +}; + +static struct tpm_i2c_ST_dev tpm_dev = { + /* Note: replace with defined addr from board configuration */ + .addr = CONFIG_TPM_I2C_ADDR +}; + +/* + * write8_reg + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: Returns negative errno, or else the number of bytes written. + */ +static int write8_reg(u8 addr, u8 tpm_register, + u8 *tpm_data, u16 tpm_size) +{ + u8 data; + data = tpm_register; + memcpy(&(tpm_dev.buf[0]), &data, sizeof(data)); + memcpy(&(tpm_dev.buf[0])+1, tpm_data, tpm_size); + + return i2c_write(addr, 0, 0, &tpm_dev.buf[0], + tpm_size + 1); + +} /* write8_reg() */ + +/* +* read8_reg +* Recv byte from the TIS register according to the ST33ZP24 I2C protocol. +* @param: tpm_register, the tpm tis register where the data should be read +* @param: tpm_data, the TPM response +* @param: tpm_size, tpm TPM response size to read. +* @return: number of byte read successfully: should be one if success. +*/ +static int read8_reg(u8 addr, u8 tpm_register, +u8 *tpm_data, int tpm_size) +{ + u8 status = 0; + u8 data; + data = TPM_DUMMY_BYTE; + status = write8_reg(addr, tpm_register, &data, 1); + if (status == 0) + status = i2c_read(addr, 0, 0, tpm_data, tpm_size); +return status; +} /* read8_reg() */ + +/* + * I2C_WRITE_DATA + * Send byte to the TIS register according to the ST33ZP24 I2C protocol. + * @param: client, the chip description + * @param: tpm_register, the tpm tis register where the data should be written + * @param: tpm_data, the tpm_data to write inside the tpm_register + * @param: tpm_size, The length of the data + * @return: number of byte written successfully: should be one if success. + */ +#define I2C_WRITE_DATA(client, tpm_register, tpm_data, tpm_size)\ + (write8_reg(client, tpm_register | \ + TPM_WRITE_DIRECTION, tpm_data, tpm_size)) + +/* + * I2C_READ_DATA + * Recv byte from the TIS register according to the ST33ZP24 I2C protocol. + * @param: tpm, the chip description + * @param: tpm_register, the tpm tis register where the data should be read + * @param: tpm_data, the TPM response + * @param: tpm_size, tpm TPM response size to read. + * @return: number of byte read successfully: should be one if success. + */ +#define I2C_READ_DATA(client, tpm_register, tpm_data, tpm_size)\ + (read8_reg(client, tpm_register, tpm_data, tpm_size)) + +/* + * release_locality release the active locality + * @param: chip, the tpm chip description. + */ +static void release_locality(struct tpm_chip *chip) +{ + u8 data = TPM_ACCESS_ACTIVE_LOCALITY; + + I2C_WRITE_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); +} + +/* + * clear_interruption + * clear the TPM interrupt register. + * @param: tpm, the chip description + */ +static void clear_interruption(u8 addr) +{ + u8 interrupt; + I2C_READ_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); + I2C_WRITE_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); + I2C_READ_DATA(tpm_dev.addr, TPM_INT_STATUS, &interrupt, 1); +} /* clear_interruption() */ + +int wait_for_serirq_timeout(struct tpm_chip *chip, int condition, + unsigned long timeout) +{ + int status = 2; + + clear_interruption(tpm_dev.addr); + if (condition) + status = 1; + + return status; +} + +/* + * check_locality if the locality is active + * @param: chip, the tpm chip description + * @return: the active locality or -EACCESS. + */ +static int check_locality(struct tpm_chip *chip) +{ + u8 data; + u8 status; + status = I2C_READ_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); + + if ((status == 0) && (data & + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == + (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) + return chip->vendor.locality; + + return -EACCES; + +} /* check_locality() */ + +/* + * request_locality request the TPM locality + * @param: chip, the chip description + * @return: the active locality or EACCESS. + */ +static int request_locality(struct tpm_chip *chip) +{ + unsigned long start, stop; + long rc; + u8 data; + if (check_locality(chip) == chip->vendor.locality) + return chip->vendor.locality; + + data = TPM_ACCESS_REQUEST_USE; + rc = I2C_WRITE_DATA(tpm_dev.addr, TPM_ACCESS, &data, 1); + if (rc < 0) + goto end; + + if (chip->vendor.irq) { + rc = wait_for_serirq_timeout(chip, (check_locality + (chip) >= 0), + chip->vendor.timeout_a); + if (rc > 0) + return chip->vendor.locality; + } else{ + /* wait for locality activated */ + start = get_timer(0); + stop = chip->vendor.timeout_a; + do { + if (check_locality(chip) >= 0) + return chip->vendor.locality; + + msleep(TPM_TIMEOUT); + } while (get_timer(start) < stop); + } + rc = -EACCES; +end: + return rc; +} /* request_locality() */ + +/* + * tpm_stm_i2c_cancel, cancel is not implemented. + * @param: chip, tpm_chip description. + */ +static void tpm_stm_i2c_cancel(struct tpm_chip *chip) +{ + u8 data; + + data = TPM_STS_COMMAND_READY; + I2C_WRITE_DATA(tpm_dev.addr, TPM_STS, &data, 1); + if (chip->vendor.irq) + wait_for_serirq_timeout(chip, 1, chip->vendor.timeout_a); +} /* tpm_stm_i2c_cancel() */ + +/* + * tpm_stm_spi_status return the TPM_STS register + * @param: chip, the tpm chip description + * @return: the TPM_STS register value. + */ +static u8 tpm_stm_i2c_status(struct tpm_chip *chip) +{ + u8 data; + I2C_READ_DATA(tpm_dev.addr, TPM_STS, &data, 1); + return data; +} /* tpm_stm_i2c_status() */ + +/* + * get_burstcount return the burstcount address 0x19 0x1A + * @param: chip, the chip description + * return: the burstcount. + */ +static int get_burstcount(struct tpm_chip *chip) +{ + unsigned long start, stop; + int burstcnt, status; + u8 tpm_reg, temp; + + /* wait for burstcount */ + /* which timeout value, spec has 2 answers (c & d) */ + start = get_timer(0); + stop = chip->vendor.timeout_d; + do { + tpm_reg = TPM_STS + 1; + status = I2C_READ_DATA(tpm_dev.addr, tpm_reg, &temp, 1); + if (status < 0) + goto end; + + tpm_reg = tpm_reg + 1; + burstcnt = temp; + status = I2C_READ_DATA(tpm_dev.addr, tpm_reg, &temp, 1); + if (status < 0) + goto end; + + burstcnt |= temp << 8; + if (burstcnt) + return burstcnt; + + msleep(TPM_TIMEOUT); + } while (get_timer(start) < stop); + +end: + return -EBUSY; +} /* get_burstcount() */ + + +/* + * recv_data receive data + * @param: chip, the tpm chip description + * @param: buf, the buffer where the data are received + * @param: count, the number of data to receive + * @return: the number of bytes read from TPM FIFO. + */ +static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) +{ + int size = 0, burstcnt, len; + + while (size < count) { + burstcnt = get_burstcount(chip); + len = count - size; + if ((len) > burstcnt) + len = burstcnt; + if (I2C_READ_DATA(tpm_dev.addr, TPM_DATA_FIFO, + buf + size, len) == 0) + size += len; + else + break; + } + return size; +} /* recv_data() */ + +/* + * tpm_stm_i2c_recv received TPM response through the I2C bus. + * @param: chip, tpm_chip description. + * @param: buf, the buffer to store datas. + * @param: count, the number of bytes to send. + * @return: In case of success the number of bytes received. + * In other case, a < 0 value describing the issue. + */ +static int tpm_stm_i2c_recv(struct tpm_chip *chip, unsigned char *buf, + size_t count) +{ + int size = 0; + int expected; + + if (chip == NULL) + return -EBUSY; + + if (count < TPM_HEADER_SIZE) { + size = -EIO; + goto out; + } + + size = recv_data(chip, buf, TPM_HEADER_SIZE); + if (size < TPM_HEADER_SIZE) { + dev_err(chip->dev, "Unable to read header\n"); + goto out; + } + + + expected = get_unaligned_be32(buf + TPM_RSP_SIZE_BYTE); + if (expected > count) { + size = -EIO; + goto out; + } + + size += recv_data(chip, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (size < expected) { + dev_err(chip->dev, "Unable to read remainder of result\n"); + size = -ETIME; + goto out; + } + +out: + chip->vendor.cancel(chip); + release_locality(chip); + return size; +} /* tpm_stm_i2c_recv() */ + +/* + * tpm_stm_i2c_send send TPM commands through the I2C bus. + * + * @param: chip, tpm_chip description. + * @param: buf, the buffer to send. + * @param: len, the number of bytes to send. + * @return: In case of success the number of bytes sent. + * In other case, a < 0 value describing the issue. + */ +static int tpm_stm_i2c_send(struct tpm_chip *chip, u8 *buf, + size_t len) +{ + u32 ret = 0, + status, + burstcnt = 0, i, size; + u8 data; + + if (chip == NULL) + return -EBUSY; + if (len < TPM_HEADER_SIZE) + return -EBUSY; + + ret = request_locality(chip); + if (ret < 0) + return ret; + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_COMMAND_READY) == 0) + tpm_stm_i2c_cancel(chip); + + for (i = 0 ; i < len - 1 ;) { + burstcnt = get_burstcount(chip); + size = len - i - 1; + if ((size) > burstcnt) + size = burstcnt; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf, size); + if (ret < 0) + goto out_err; + + i += size; + } + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_DATA_EXPECT) == 0) { + ret = -EIO; + goto out_err; + } + + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf + len - 1, 1); + if (ret < 0) + goto out_err; + + status = tpm_stm_i2c_status(chip); + if ((status & TPM_STS_DATA_EXPECT) != 0) { + ret = -EIO; + goto out_err; + } + + data = TPM_STS_GO; + I2C_WRITE_DATA(tpm_dev.addr, TPM_STS, &data, 1); + + return len; +out_err: + tpm_stm_i2c_cancel(chip); + release_locality(chip); + return ret; +} /* tpm_stm_i2c_send() */ + +/* + * tpm_stm_i2c_send_hash send TPM locality 4 hash datas through the I2C bus + * to update the PCR[17]. + * @param: chip, the tpm_chip description. + * @param: buf, the data buffer to send. + * @param: len, the number of bytes to send. + * @return: In case of success the number of bytes sent. + * In other case, a < 0 value describing the issue. + */ +static int tpm_stm_i2c_send_hash(struct tpm_chip *chip, unsigned char *buf, + size_t len) +{ + u32 ret = 0; + u8 data; + + if (chip == NULL) + return -EBUSY; + + release_locality(chip); + + tpm_dev.addr = 0x1B; + chip->vendor.locality = LOCALITY4; + + data = TPM_DUMMY_BYTE; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_HASH_START, &data, 1); + if (ret < 0) + goto end; + ret = I2C_WRITE_DATA(tpm_dev.addr, TPM_DATA_FIFO, buf, len); + if (ret < 0) + goto end; + +end: + I2C_WRITE_DATA(tpm_dev.addr, TPM_HASH_END, &data, 1); + release_locality(chip); + chip->vendor.locality = LOCALITY0; + tpm_dev.addr = 0x13; + ret = request_locality(chip); + return ret; +} /* tpm_stm_i2c_send_hash */ + +static struct tpm_vendor_specific st_i2c_tpm = { + .send = tpm_stm_i2c_send, + .send_hash = tpm_stm_i2c_send_hash, + .recv = tpm_stm_i2c_recv, + .cancel = tpm_stm_i2c_cancel, + .status = tpm_stm_i2c_status, + .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, + .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, + .req_canceled = TPM_STS_COMMAND_READY, +}; + +/* + * tpm_vendor_init initialize the TPM device + * @param: dev_addr, the i2c address of the tpm. + * @return: 0 in case of success. + * -1 in other case. + */ +int tpm_vendor_init(uint32_t dev_addr) +{ + u32 vendor; + uint old_addr; + int rc = 0; + struct tpm_chip *chip; + + old_addr = tpm_dev.addr; + if (dev_addr != 0) + tpm_dev.addr = dev_addr; + + chip = tpm_register_hardware(&st_i2c_tpm); + + if (chip < 0) { + rc = -ENODEV; + goto out_err; + } + + /* Default timeouts */ + chip->vendor.timeout_a = TIS_SHORT_TIMEOUT; + chip->vendor.timeout_b = TIS_LONG_TIMEOUT; + chip->vendor.timeout_c = TIS_SHORT_TIMEOUT; + chip->vendor.timeout_d = TIS_SHORT_TIMEOUT; + + chip->vendor.locality = LOCALITY0; + + if (request_locality(chip) != 0) { + rc = -ENODEV; + goto out_err; + } + + vendor = be32_to_cpu(vendor); + + + dev_info(dev, "1.2 TPM STMicroelectronics"); + /* + * A timeout query to TPM can be placed here. + * Standard timeout values are used so far + */ + + return 0; + +out_err: + tpm_dev.addr = old_addr; + return rc; +} /* tpm_vendor_init() */ + + + +void tpm_vendor_cleanup(struct tpm_chip *chip) +{ + release_locality(chip); +} /* tpm_vendor_cleanup() */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 48ce4c0..ef381f8 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -111,6 +111,14 @@ #define STATUS_LED_BOOT STATUS_LED_BIT #define STATUS_LED_GREEN STATUS_LED_BIT1 +/* TPM */ +#define CONFIG_CMD_TPM +#define CONFIG_TPM +#define CONFIG_ST_TPM_DEBUG +#define CONFIG_ST_TPM_I2C +#define CONFIG_TPM_I2C_BUS 1 +#define CONFIG_TPM_I2C_ADDR 0x13 + /* Enable Multi Bus support for I2C */ #define CONFIG_I2C_MULTI_BUS 1 diff --git a/include/tpm.h b/include/tpm.h index 6b21e9c..9074885 100644 --- a/include/tpm.h +++ b/include/tpm.h @@ -68,4 +68,20 @@ int tis_close(void); int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len); +/* + * tis_sendrecv_hash() + * + * Send the requested data to the TPM for hash in LOC 4 + * and then try to get its response + * + * @sendbuf - buffer of the data to hash + * @send_size size of the data to send + * @recvbuf - memory to save the response to + * @recv_len - pointer to the size of the response buffer + * + * Returns 0 on success (and places the number of response bytes at recv_len) + * or -1 on failure. + */ +int tis_sendrecv_hash(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, + size_t *recv_len); #endif /* _INCLUDE_TPM_H_ */ -- 1.7.1

2 1

[U-Boot] [PATCH V4 0/5] ARM: OMAP4/5: Add support to boot with device tree as default
by Sricharan R 08 Apr '13

08 Apr '13

With the kernel moving all towards device tree, this series adds support to make the device tree boot as the default for OMAP4/5 platforms. Nishanth Menon (1): omap5: Allow use of a plain text env file Sricharan R (4): ARM: OMAP5: Rename omap5_evm to omap5_uevm ARM: OMAP5: Set fdt_high to enable booting with Device tree ARM: OMAP4/5: Change the default boot command to work with device tree ARM: OMAP4/5: Make bootz as the default boot command board/ti/{omap5_evm => omap5_uevm}/Makefile | 0 board/ti/{omap5_evm => omap5_uevm}/evm.c | 0 board/ti/{omap5_evm => omap5_uevm}/mux_data.h | 0 boards.cfg | 2 +- include/configs/omap4_common.h | 22 +++++++++++++--- include/configs/omap5_common.h | 35 +++++++++++++++++++++---- include/configs/{omap5_evm.h => omap5_uevm.h} | 0 7 files changed, 50 insertions(+), 9 deletions(-) rename board/ti/{omap5_evm => omap5_uevm}/Makefile (100%) rename board/ti/{omap5_evm => omap5_uevm}/evm.c (100%) rename board/ti/{omap5_evm => omap5_uevm}/mux_data.h (100%) rename include/configs/{omap5_evm.h => omap5_uevm.h} (100%) -- 1.7.9.5

3 18

[U-Boot] [RFC/PATCH 0/4] BCH8 support for OMAP3
by Andreas Bießmann 08 Apr '13

08 Apr '13

This RFC series implements BCH8 for OMAP3 as provided by linux kernel in commit 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c. This series is heavily influenced by Ilyas series 'NAND support for AM33XX' thus could share some code. I have managed to load kernel from an ubifs written by the kernel driver, but is far away from tested thoroughly. Cause my NAND device 'NAND device: Manufacturer ID: 0x2c, Chip ID: 0xbc (Micron NAND 512MiB 1,8V 16-bit)' does support 1bit ECC for first sector if erase is less than 1000, the rest requires 4bit ECC. Therefore the SPL needs to support BCH, the impact is about 9k for the SPL. Andreas Bießmann (4): omap3/cpu.h: add BCH support omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernel omap_gpmc: add support for hw assisted BCH8 tricorder: enable hw assisted BCH8 in SPL and u-boot arch/arm/cpu/armv7/omap3/board.c | 8 +- arch/arm/include/asm/arch-omap3/cpu.h | 6 + arch/arm/include/asm/arch-omap3/omap_gpmc.h | 12 ++ drivers/mtd/nand/omap_gpmc.c | 216 ++++++++++++++++++++++++++- include/configs/tricorder.h | 10 +- lib/Makefile | 3 +- 6 files changed, 248 insertions(+), 7 deletions(-) -- 1.7.10.4

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[U-Boot] [PATCH] arm: omap4: Fix SDRAM AUTO DETECTION
by Lokesh Vutla 08 Apr '13

08 Apr '13

Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards(a)prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/cpu/armv7/omap-common/emif-common.c | 29 ++++++++++++++------------ arch/arm/cpu/armv7/omap4/emif.c | 1 - arch/arm/cpu/armv7/omap5/emif.c | 1 - arch/arm/include/asm/arch-omap4/omap.h | 1 - arch/arm/include/asm/arch-omap5/omap.h | 1 - arch/arm/include/asm/emif.h | 1 - 6 files changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 9eb1279..cdb4439 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -655,20 +655,27 @@ static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) return phy; } -static u32 get_emif_mem_size(struct emif_device_details *devices) +static u32 get_emif_mem_size(u32 base) { u32 size_mbytes = 0, temp; + struct emif_device_details dev_details; + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + u32 emif_nr = emif_num(base); - if (!devices) - return 0; + emif_reset_phy(base); + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, + &cs0_dev_details); + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, + &cs1_dev_details); + emif_reset_phy(base); - if (devices->cs0_device_details) { - temp = devices->cs0_device_details->density; + if (dev_details.cs0_device_details) { + temp = dev_details.cs0_device_details->density; size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; } - if (devices->cs1_device_details) { - temp = devices->cs1_device_details->density; + if (dev_details.cs1_device_details) { + temp = dev_details.cs1_device_details->density; size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; } /* convert to bytes */ @@ -1040,13 +1047,9 @@ static void do_sdram_init(u32 base) /* Return if no devices on this EMIF */ if (!dev_details.cs0_device_details && !dev_details.cs1_device_details) { - emif_sizes[emif_nr - 1] = 0; return; } - if (!in_sdram) - emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); - /* * Get device timings: * - Default timings specified by JESD209-2 if @@ -1108,8 +1111,8 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; sys_addr = CONFIG_SYS_SDRAM_BASE; - emif1_size = emif_sizes[0]; - emif2_size = emif_sizes[1]; + emif1_size = get_emif_mem_size(EMIF1_BASE); + emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); if (!emif1_size && !emif2_size) diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index ca4823d..53f6063 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -33,7 +33,6 @@ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; -u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c index 90d362c..9f53c90 100644 --- a/arch/arm/cpu/armv7/omap5/emif.c +++ b/arch/arm/cpu/armv7/omap5/emif.c @@ -34,7 +34,6 @@ #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM; u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN; -u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 5f321fe..ad984da 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -147,7 +147,6 @@ struct s32ktimer { #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START /* SRAM scratch space entries */ #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b632635..887fcaa 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -196,7 +196,6 @@ struct s32ktimer { * SRAM scratch space entries */ #define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index c5d1e6c..5f11d7b 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1165,7 +1165,6 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; -extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); -- 1.7.9.5

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[U-Boot] [PATCH v2] OMAP: Fix copy-paste bug that did not enable UART4 clock
by Lubomir Popov 08 Apr '13

08 Apr '13

V2 fixes line wrap issue of the patch itself. UART3 was enabled twice instead of UART4. One more cosmetic change in a comment on EMIF clock. Signed-off-by: Lubomir Popov <lpopov(a)mm-sol.com> --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 9ed1899..2b955c7 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -612,7 +612,7 @@ void freq_update_core(void) /* * Putting EMIF in HW_AUTO is seen to be causing issues with - * EMIF clocks and the master DLL. Put EMIF in SW_WKUP + * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP * in OMAP5430 ES1.0 silicon */ if (omap_rev != OMAP5430_ES1_0) { @@ -659,7 +659,7 @@ void setup_clocks_for_console(void) MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); -- 1.7.9.5

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