April 2013 - U-Boot

[U-Boot] [PATCH v2] Tegra: Split tegra_get_chip_type() into soc & sku funcs
by Tom Warren 10 Apr '13

10 Apr '13

As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/cpu/arm720t/tegra-common/cpu.c | 48 +++++++++++++++++++-------------- arch/arm/cpu/arm720t/tegra-common/cpu.h | 4 ++- arch/arm/cpu/tegra-common/ap.c | 43 +++++++++++++++++++++-------- arch/arm/cpu/tegra20-common/pmu.c | 4 +-- arch/arm/include/asm/arch-tegra/ap.h | 20 ++++++++++++-- board/nvidia/common/emc.c | 2 +- 6 files changed, 84 insertions(+), 37 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 119342e..9294611 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -143,26 +143,34 @@ void init_pllx(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; - int chip_type; + int soc_type, sku_info, chip_sku; enum clock_osc_freq osc; struct clk_pll_table *sel; debug("init_pllx entry\n"); - /* get chip type */ - chip_type = tegra_get_chip_type(); - debug(" init_pllx: chip_type = %d\n", chip_type); + /* get SOC (chip) type */ + soc_type = tegra_get_chip(); + debug(" init_pllx: SoC = 0x%02X\n", soc_type); + + /* get SKU info */ + sku_info = tegra_get_sku_info(); + debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info); + + /* get chip SKU, combo of the above info */ + chip_sku = tegra_get_chip_sku(); + debug(" init_pllx: Chip SKU = %d\n", chip_sku); /* get osc freq */ osc = clock_get_osc_freq(); - debug(" init_pllx: osc = %d\n", osc); + debug(" init_pllx: osc = %d\n", osc); /* set pllx */ - sel = &tegra_pll_x_table[chip_type][osc]; + sel = &tegra_pll_x_table[chip_sku][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); - /* adjust PLLP_out1-4 on T30/T114 */ - if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) { + /* adjust PLLP_out1-4 on T3x/T114 */ + if (soc_type >= CHIPID_TEGRA30) { debug(" init_pllx: adjusting PLLP out freqs\n"); adjust_pllp_out_freqs(); } @@ -287,7 +295,7 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int chip; + int soc_type; debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -295,21 +303,21 @@ void clock_enable_coresight(int enable) if (enable) { /* - * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by - * 1.5, giving an effective frequency of 144MHz. - * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor - * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) - * - * Clock divider request for 204MHz would setup CSITE clock as - * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz + * Put CoreSight on PLLP_OUT0 and divide it down as per + * PLLP base frequency based on SoC type (T20/T30/T114). + * Clock divider request would setup CSITE clock as 144MHz + * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - chip = tegra_get_chip_type(); - if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114) + + soc_type = tegra_get_chip(); + if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25) + else if (soc_type == CHIPID_TEGRA20) src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); else - printf("%s: Unknown chip type %X!\n", __func__, chip); + printf("%s: Unknown SoC type %X!\n", + __func__, soc_type); + clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); /* Unlock the CPU CoreSight interfaces */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index e8e05d7..f9bfb32 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -80,5 +80,7 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); -int tegra_get_chip_type(void); +int tegra_get_chip(void); +int tegra_get_sku_info(void); +int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index a739fe2..9b77b2b 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -34,25 +34,44 @@ #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> -int tegra_get_chip_type(void) +int tegra_get_chip(void) { - struct apb_misc_gp_ctlr *gp; - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - uint tegra_sku_id, rev; + int rev; + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; /* * This is undocumented, Chip ID is bits 15:8 of the register * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for * Tegra30, and 0x35 for T114. */ - gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; + debug("%s: CHIPID is 0x%02X\n", __func__, rev); + + return rev; +} + +int tegra_get_sku_info(void) +{ + int sku_id; + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + + sku_id = readl(&fuse->sku_info) & 0xff; + debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + + return sku_id; +} + +int tegra_get_chip_sku(void) +{ + uint sku_id, chip_id; - tegra_sku_id = readl(&fuse->sku_info) & 0xff; + chip_id = tegra_get_chip(); + sku_id = tegra_get_sku_info(); - switch (rev) { + switch (chip_id) { case CHIPID_TEGRA20: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T20: return TEGRA_SOC_T20; case SKU_ID_T25SE: @@ -64,20 +83,22 @@ int tegra_get_chip_type(void) } break; case CHIPID_TEGRA30: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: return TEGRA_SOC_T30; } break; case CHIPID_TEGRA114: - switch (tegra_sku_id) { + switch (sku_id) { case SKU_ID_T114_ENG: return TEGRA_SOC_T114; } break; } - /* unknown sku id */ + /* unknown chip/sku id */ + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c index 2282953..4c5a533 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/cpu/tegra20-common/pmu.c @@ -44,7 +44,7 @@ int pmu_set_nominal(void) int core, cpu, bus; /* by default, the table has been filled with T25 settings */ - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { case TEGRA_SOC_T20: core = VDD_CORE_NOMINAL_T20; cpu = VDD_CPU_NOMINAL_T20; @@ -54,7 +54,7 @@ int pmu_set_nominal(void) cpu = VDD_CPU_NOMINAL_T25; break; default: - debug("%s: Unknown chip type\n", __func__); + debug("%s: Unknown SKU id\n", __func__); return -1; } diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index 5999f55..f6d08c6 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -59,9 +59,25 @@ extern void _start(void); /** - * Works out the SOC type used for clocks settings + * Works out the SOC/SKU type used for clocks settings * * @return SOC type - see TEGRA_SOC... */ -int tegra_get_chip_type(void); +int tegra_get_chip_sku(void); + +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ +int tegra_get_chip(void); + +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ +int tegra_get_sku_info(void); + +/* Do any chip-specific cache config */ void config_cache(void); diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c index 26b6ec7..87d7aa2 100644 --- a/board/nvidia/common/emc.c +++ b/board/nvidia/common/emc.c @@ -40,7 +40,7 @@ int board_emc_init(void) { unsigned rate; - switch (tegra_get_chip_type()) { + switch (tegra_get_chip_sku()) { default: case TEGRA_SOC_T20: rate = EMC_SDRAM_RATE_T20; -- 1.8.1.5

2 1

[U-Boot] [PATCH] doc/feature-removal-schedule.txt: Add CONFIG_SYS_(CLOCKS|PADS)_ENABLE_ALL
by Tom Rini 10 Apr '13

10 Apr '13

We shall remove these OMAP4/5-specific options in v2013.07, barring insufficient progress on the kernel side. Cc: Sricharan R <r.sricharan(a)ti.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- doc/feature-removal-schedule.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index d9a0cc2..58db440 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -24,6 +24,22 @@ Who: Wolfgang Denk <wd(a)denx.de> --------------------------- +What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL +When: Release v2013.07 + +Why: When set these options enable "all" of the pads and clocks found + on OMAP4/5 platforms, so that the Linux Kernel does not have to. + It has been agreed that this goes against the U-Boot design + philosophy and since f3f98bb0 we have not enabled more than is + used in U-Boot. The kernel has been updating drivers to enable + rather than assume pads/clocks have been enabled already. Our + expectation is that by v2013.07 a suitable kernel shall exist that + does not need these options set for a reasonable I/O set to function. + +Who: Tom Rini <trini(a)ti.com> and Sricharan R <r.sricharan(a)ti.com> + +--------------------------- + What: Users of the legacy miiphy_* code When: undetermined -- 1.7.9.5

2 7

[U-Boot] [PATCH] cmd/gpt: Support gpt command for all devices.
by egbert.eich＠googlemail.com 10 Apr '13

10 Apr '13

From: Egbert Eich <eich(a)suse.com> The gpt command was only implemented for mmc devices. There is no reason why this command should not be generalized and be applied all other storage device classes. This change both simplifies the implementation and eliminates a build failure for systems that don't support mmcs. Signed-off-by: Egbert Eich <eich(a)suse.com> --- common/cmd_gpt.c | 43 ++++++++++++++++++------------------------- 1 files changed, 18 insertions(+), 25 deletions(-) diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index efd7934..1a72e8e 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -23,7 +23,6 @@ #include <common.h> #include <malloc.h> #include <command.h> -#include <mmc.h> #include <part_efi.h> #include <exports.h> #include <linux/ctype.h> @@ -134,7 +133,7 @@ static int set_gpt_info(block_dev_desc_t *dev_desc, int errno = 0; uint64_t size_ll, start_ll; - debug("%s: MMC lba num: 0x%x %d\n", __func__, + debug("%s: lba num: 0x%x %d\n", __func__, (unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba); if (str_part == NULL) @@ -247,25 +246,18 @@ err: return errno; } -static int gpt_mmc_default(int dev, const char *str_part) +static int gpt_default(block_dev_desc_t *blk_dev_desc, const char *str_part) { int ret; char *str_disk_guid; u8 part_count = 0; disk_partition_t *partitions = NULL; - struct mmc *mmc = find_mmc_device(dev); - - if (mmc == NULL) { - printf("%s: mmc dev %d NOT available\n", __func__, dev); - return CMD_RET_FAILURE; - } - if (!str_part) return -1; /* fill partitions */ - ret = set_gpt_info(&mmc->block_dev, str_part, + ret = set_gpt_info(blk_dev_desc, str_part, &str_disk_guid, &partitions, &part_count); if (ret) { if (ret == -1) @@ -278,7 +270,7 @@ static int gpt_mmc_default(int dev, const char *str_part) } /* save partitions layout to disk */ - gpt_restore(&mmc->block_dev, str_disk_guid, partitions, part_count); + gpt_restore(&blk_dev_desc, str_disk_guid, partitions, part_count); free(str_disk_guid); free(partitions); @@ -306,20 +298,21 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* command: 'write' */ if ((strcmp(argv[1], "write") == 0) && (argc == 5)) { - /* device: 'mmc' */ - if (strcmp(argv[2], "mmc") == 0) { - /* check if 'dev' is a number */ - for (pstr = argv[3]; *pstr != '\0'; pstr++) - if (!isdigit(*pstr)) { - printf("'%s' is not a number\n", - argv[3]); - return CMD_RET_USAGE; - } - dev = (int)simple_strtoul(argv[3], NULL, 10); - /* write to mmc */ - if (gpt_mmc_default(dev, argv[4])) - return CMD_RET_FAILURE; + char *ep; + block_dev_desc_t *blk_dev_desc; + dev = (int)simple_strtoul(argv[3], NULL, 10); + if (*ep) { + printf("'%s' is not a number\n", argv[3]); + return CMD_RET_USAGE; } + blk_dev_desc = get_dev(argv[2], dev); + if (!blk_dev_desc) { + printf("%s: %s dev %d NOT available\n", __func__, argv[2], dev); + return CMD_RET_FAILURE; + } + + if (gpt_default(blk_dev_desc, argv[4])) + return CMD_RET_FAILURE; } else { return CMD_RET_USAGE; } -- 1.7.7

5 4

[U-Boot] sbabic@denx.de
by Peter Korsgaard 10 Apr '13

10 Apr '13

Hi, This patch series adds falcon boot mode for MMC (raw and FAT), similar to the existing nand support. This series applies on top of the recent spl_mmc variable cleanup: http://lists.denx.de/pipermail/u-boot/2013-March/149674.html As an example, it includes a RFC patch adding falcon boot support for the am335x evm board, which has been used to test the series. That patch should not be committed as is. -- Bye, Peter Korsgaard

3 11

[U-Boot] zmodem ?
by Brad Walker 10 Apr '13

10 Apr '13

I am curious to know about the status of support for zmodem. I've looked through the mail archives and it seems as though ymodem is supported. But, zmodem is currently not. Also, there is a kermit mode that is supported. Is my understanding correct? Thanks. -brad w.

2 1

[U-Boot] which version of uboot support ARM A7
by Li, Hai 10 Apr '13

10 Apr '13

Hi all, Does anybody know which version of uboot support ARM A7? And where I can get the ARM A7 patch for u-boot-2013.04-rc2.tar.bz2<ftp://ftp.denx.de/pub/u-boot/u-boot-2013.04-rc2.tar.bz2>? Thanks! Best Wishes Hai Li

1 0

[U-Boot] [PATCH 2/5][v2] powerpc/mpc85xx: new SPL support for IFC NAND
by Prabhakar Kushwaha 09 Apr '13

09 Apr '13

Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer cotrol from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: Sending as it is arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 2 +- board/freescale/common/Makefile | 10 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_ifc_spl.c | 258 +++++++++++++++++++++++++++++++ 4 files changed, 270 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/fsl_ifc_spl.c diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index f2b7bff..cf6fa7c 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -60,7 +60,7 @@ SECTIONS #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ .bootpg ADDR(.text) + 0x1000 : { - start.o (.bootpg) + arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ #elif defined(CONFIG_FSL_ELBC) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 75725b4..a4d521c 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,6 +29,15 @@ endif LIB = $(obj)libfreescale.o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifndef MINIMAL COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o @@ -62,6 +71,7 @@ SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c77c0c4..9d7deb8 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -82,6 +82,7 @@ COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o else # minimal SPL drivers COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o +COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o endif # drivers endif # nand diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c new file mode 100644 index 0000000..c4a9ba1 --- /dev/null +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -0,0 +1,258 @@ +/* + * NAND boot for Freescale Integrated Flash Controller, NAND FCM + * + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_ifc.h> +#include <linux/mtd/nand.h> + +static inline int is_blank(uchar *addr, int page_size) +{ + int i; + + for (i = 0; i < page_size; i++) { + if (__raw_readb(&addr[i]) != 0xff) + return 0; + } + + /* + * For the SPL, don't worry about uncorrectable errors + * where the main area is all FFs but shouldn't be. + */ + return 1; +} + +/* returns nonzero if entire page is blank */ +static inline int check_read_ecc(uchar *buf, u32 *eccstat, + unsigned int bufnum, int page_size) +{ + u32 reg = eccstat[bufnum / 4]; + int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; + + if (errors == 15) { /* uncorrectable */ + /* Blank pages fail hw ECC checks */ + if (is_blank(buf, page_size)) + return 1; + + puts("ecc error\n"); + for (;;) + ; + } + + return 0; +} + +static inline void nand_wait(uchar *buf, int bufnum, int page_size) +{ + struct fsl_ifc *ifc = IFC_BASE_ADDR; + u32 status; + u32 eccstat[4]; + int bufperpage = page_size / 512; + int bufnum_end, i; + + bufnum *= bufperpage; + bufnum_end = bufnum + bufperpage - 1; + + do { + status = in_be32(&ifc->ifc_nand.nand_evter_stat); + } while (!(status & IFC_NAND_EVTER_STAT_OPC)); + + if (status & IFC_NAND_EVTER_STAT_FTOER) { + puts("flash time out error\n"); + for (;;) + ; + } + + for (i = bufnum / 4; i <= bufnum_end / 4; i++) + eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + + for (i = bufnum; i <= bufnum_end; i++) { + if (check_read_ecc(buf, eccstat, i, page_size)) + break; + } + + out_be32(&ifc->ifc_nand.nand_evter_stat, status); +} + +static inline int bad_block(uchar *marker, int port_size) +{ + if (port_size == 8) + return __raw_readb(marker) != 0xff; + else + return __raw_readw((u16 *)marker) != 0xffff; +} + +static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +{ + struct fsl_ifc *ifc = IFC_BASE_ADDR; + uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; + int page_size; + int port_size; + int pages_per_blk; + int blk_size; + int bad_marker = 0; + int bufnum_mask, bufnum; + + int csor, cspr; + int pos = 0; + int j = 0; + + int sram_addr; + int pg_no; + + /* Get NAND Flash configuration */ + csor = CONFIG_SYS_NAND_CSOR; + cspr = CONFIG_SYS_NAND_CSPR; + + port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; + + if (csor & CSOR_NAND_PGS_4K) { + page_size = 4096; + bufnum_mask = 1; + } else if (csor & CSOR_NAND_PGS_2K) { + page_size = 2048; + bufnum_mask = 3; + } else { + page_size = 512; + bufnum_mask = 15; + + if (port_size == 8) + bad_marker = 5; + } + + pages_per_blk = + 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT); + + blk_size = pages_per_blk * page_size; + + /* Open Full SRAM mapping for spare are access */ + out_be32(&ifc->ifc_nand.ncfgr, 0x0); + + /* Clear Boot events */ + out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + + /* Program FIR/FCR for Large/Small page */ + if (page_size > 512) { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + + out_be32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + } else { + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, 0x0); + + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + } + + /* Program FBCR = 0 for full page read */ + out_be32(&ifc->ifc_nand.nand_fbcr, 0); + + /* Read and copy u-boot on SDRAM from NAND device, In parallel + * check for Bad block if found skip it and read continue to + * next Block + */ + while (pos < uboot_size) { + int i = 0; + do { + pg_no = offs / page_size; + bufnum = pg_no & bufnum_mask; + sram_addr = bufnum * page_size * 2; + + out_be32(&ifc->ifc_nand.row0, pg_no); + out_be32(&ifc->ifc_nand.col0, 0); + /* start read */ + out_be32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for read to complete */ + nand_wait(&buf[sram_addr], bufnum, page_size); + + /* + * If either of the first two pages are marked bad, + * continue to the next block. + */ + if (i++ < 2 && + bad_block(&buf[sram_addr + page_size + bad_marker], + port_size)) { + puts("skipping\n"); + offs = (offs + blk_size) & ~(blk_size - 1); + pos &= ~(blk_size - 1); + break; + } + + for (j = 0; j < page_size; j++) + dst[pos + j] = __raw_readb(&buf[sram_addr + j]); + + pos += page_size; + offs += page_size; + } while ((offs & (blk_size - 1)) && (pos < uboot_size)); + } +} + +/* + * Main entrypoint for NAND Boot. It's necessary that SDRAM is already + * configured and available since this code loads the main U-boot image + * from NAND into SDRAM and starts from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + /* + * Load U-Boot image from NAND into RAM + */ + nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + +#ifdef CONFIG_NAND_ENV_DST + nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); + +#ifdef CONFIG_ENV_OFFSET_REDUND + nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); +#endif +#endif + /* + * Jump to U-Boot image + */ +#ifdef CONFIG_SPL_FLUSH_IMAGE + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); +#endif + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot(); +} -- 1.7.9.5

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[U-Boot] [PATCH 0/5] omap5912-osk: Fix u-boot support for board
by Jon Hunter 09 Apr '13

09 Apr '13

Currently, u-boot support for the omap5912-osk board is broken and u-boot is not booting when program into flash. Fix u-boot support for this board. Jon Hunter (5): omap5912-osk: Fix DRAM initialisation omap5912-osk: Fix booting from NOR flash omap5912-osk: Fix device initialisation omap5912-osk: Increase flash partition for u-boot omap5912-osk: Fix get_timer() and CONFIG_SYS_HZ arch/arm/cpu/arm926ejs/omap/timer.c | 15 ++++++++------- board/ti/omap5912osk/config.mk | 12 ++++++------ board/ti/omap5912osk/lowlevel_init.S | 20 ++++++++++++++++++++ board/ti/omap5912osk/omap5912osk.c | 23 ++++++++++++++++------- include/configs/omap5912osk.h | 15 +++++++++------ 5 files changed, 59 insertions(+), 26 deletions(-) -- 1.7.10.4

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[U-Boot] Patman / buildman pull request
by Simon Glass 09 Apr '13

09 Apr '13

Hi Tom, I have brought in the patman changes for this release and also some changes that I consider to be bug fixes. For now I have left out these patches: http://patchwork.ozlabs.org/patch/231570/ http://patchwork.ozlabs.org/patch/231572/ http://patchwork.ozlabs.org/patch/231575/ however they do improve the operation of patman, so if you are OK with it I would quiet like to bring in the last two at least. As I mentioned earlier buildman is still not perfect - I am hoping that others will help fix the known deficiencies and find others, as happened with patman. The following changes since commit c8142633e169665b246352918df5b76fd243bb71: Prepare v2013.04-rc2 (2013-04-03 15:02:40 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git patman for you to fetch changes up to fc3fe1c287fc5ee4c528b4059405571fcd2d55bd: buildman - U-Boot multi-threaded builder and summary tool (2013-04-04 14:04:35 -0700) ---------------------------------------------------------------- Doug Anderson (2): patman: Make "Reviewed-by" an important tag patman: Allow specifying the message ID your series is in reply to Simon Glass (14): patman: Use ANSI colours only when outputting to a terminal patman: Use bright ANSI colours by default patman: Add cros_subprocess library to manage subprocesses patman: Make command methods return a CommandResult patman: Allow commands to raise on error, or not patman: Allow reading metadata from a list of commits patman: Add additional git utilties patman: Add Cover-letter-cc tag to Cc cover letter to people patman: Fix up checkpatch parsing to deal with 'CHECK' lines patman: Don't allow spaces in tags patman: Fix the comment in CheckTags to mention multiple tags patman: Minor help message/README fixes patman: Ignore all Gerrit Commit-* tags buildman - U-Boot multi-threaded builder and summary tool tools/buildman/.gitignore | 1 + tools/buildman/README | 679 ++++++++++++++++++++++++++++ tools/buildman/board.py | 167 +++++++ tools/buildman/bsettings.py | 60 +++ tools/buildman/builder.py | 1445 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ tools/buildman/buildman | 1 + tools/buildman/buildman.py | 126 ++++++ tools/buildman/control.py | 181 ++++++++ tools/buildman/test.py | 185 ++++++++ tools/buildman/toolchain.py | 185 ++++++++ tools/patman/README | 18 +- tools/patman/checkpatch.py | 110 +++-- tools/patman/command.py | 89 +++- tools/patman/commit.py | 7 +- tools/patman/cros_subprocess.py | 397 ++++++++++++++++ tools/patman/gitutil.py | 136 +++++- tools/patman/patchstream.py | 50 ++- tools/patman/patman.py | 8 +- tools/patman/series.py | 11 +- tools/patman/terminal.py | 30 +- tools/patman/test.py | 64 ++- 21 files changed, 3829 insertions(+), 121 deletions(-) create mode 100644 tools/buildman/.gitignore create mode 100644 tools/buildman/README create mode 100644 tools/buildman/board.py create mode 100644 tools/buildman/bsettings.py create mode 100644 tools/buildman/builder.py create mode 120000 tools/buildman/buildman create mode 100755 tools/buildman/buildman.py create mode 100644 tools/buildman/control.py create mode 100644 tools/buildman/test.py create mode 100644 tools/buildman/toolchain.py create mode 100644 tools/patman/cros_subprocess.py Regards, Simon

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[U-Boot] [PATCH v2 1/3] iomux-v3: Place pad control definitions into common file
by Fabio Estevam 09 Apr '13

09 Apr '13

Instead of having the same PAD control definition in each MX6 variant pin file, place it into a common location. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v2: - Add missing IOMUX_CONFIG_SION definition arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 27 --------------------------- arch/arm/include/asm/arch-mx6/mx6q_pins.h | 27 --------------------------- arch/arm/include/asm/imx-common/iomux-v3.h | 27 ++++++++++++++++++++++++++- 3 files changed, 26 insertions(+), 55 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 9846f1b..0ed12f3 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -22,33 +22,6 @@ #include <asm/imx-common/iomux-v3.h> -/* Use to set PAD control */ -#define PAD_CTL_HYS (1 << 16) -#define PAD_CTL_PUS_100K_DOWN (0 << 14) -#define PAD_CTL_PUS_47K_UP (1 << 14) -#define PAD_CTL_PUS_100K_UP (2 << 14) -#define PAD_CTL_PUS_22K_UP (3 << 14) - -#define PAD_CTL_PUE (1 << 13) -#define PAD_CTL_PKE (1 << 12) -#define PAD_CTL_ODE (1 << 11) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define IOMUX_CONFIG_SION 0x10 -#define NO_MUX_I 0 -#define NO_PAD_I 0 enum { MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h index 1c1c008..02a40d4 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h @@ -24,33 +24,6 @@ #include <asm/imx-common/iomux-v3.h> -/* Use to set PAD control */ -#define PAD_CTL_HYS (1 << 16) -#define PAD_CTL_PUS_100K_DOWN (0 << 14) -#define PAD_CTL_PUS_47K_UP (1 << 14) -#define PAD_CTL_PUS_100K_UP (2 << 14) -#define PAD_CTL_PUS_22K_UP (3 << 14) - -#define PAD_CTL_PUE (1 << 13) -#define PAD_CTL_PKE (1 << 12) -#define PAD_CTL_ODE (1 << 11) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define NO_MUX_I 0 -#define NO_PAD_I 0 - enum { MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0), diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index c34bb76..36917c8 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -95,7 +95,32 @@ typedef u64 iomux_v3_cfg_t; #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) -#define MUX_CONFIG_SION (0x1 << 4) +#define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_PUS_100K_DOWN (0 << 14) +#define PAD_CTL_PUS_47K_UP (1 << 14) +#define PAD_CTL_PUS_100K_UP (2 << 14) +#define PAD_CTL_PUS_22K_UP (3 << 14) + +#define PAD_CTL_PUE (1 << 13) +#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_SPEED_LOW (1 << 6) +#define PAD_CTL_SPEED_MED (2 << 6) +#define PAD_CTL_SPEED_HIGH (3 << 6) +#define PAD_CTL_DSE_DISABLE (0 << 3) +#define PAD_CTL_DSE_240ohm (1 << 3) +#define PAD_CTL_DSE_120ohm (2 << 3) +#define PAD_CTL_DSE_80ohm (3 << 3) +#define PAD_CTL_DSE_60ohm (4 << 3) +#define PAD_CTL_DSE_48ohm (5 << 3) +#define PAD_CTL_DSE_40ohm (6 << 3) +#define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) + +#define IOMUX_CONFIG_SION 0x10 +#define NO_MUX_I 0 +#define NO_PAD_I 0 int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, -- 1.7.9.5

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