March 2013 - U-Boot

[U-Boot] [PATCH 0/4 v5] Add ACE HW support for SHA256 and SHA1
by Akshay Saraswat 07 Mar '13

07 Mar '13

This patch set adds hardware acceleration for SHA 256 with the help of ACE. Changes since v1: - Patch-1: Fixed few nits. - Patch-2: Removed not required config. - Patch-3: Added sha256 to hash command instead of new sha256 command. Changes since v2: - Patch-1: - Added falling back to software sha256 in case length exceeds buffer limit. - Reduced one tab at lines 533, 559 and 571 in the patch. - Removed space after a cast at line 506 in the patch. - Removed blank line at line 561 in the patch. - Removed space before semicolon at line 576 in the patch. - Patch-2: - Added "SHA1" in the comment for config. - Patch-3: - Added new nodes for SHA1 and SHA256 in struct hash_algo for the case when ACE is enabled. - Added new declaration for function pointer hash_func_ws with different return type. - Patch-4: - New patch to enable config for hash command. Changes since v3: - Patch-1: - Removed buffer limit since there are 2 regs for address hash_msg_size_high and low. That means buffer length could go upto 2^64 bits which is practically - Removed falling back to software sha256 because there is no buffer limit. - Removed "/ 4" to sha1 and sha256 lengths and added increment to 4 in for loop at line 573. - Timed out still kept to be 100 ms since this is enough for hardware to switch status to idle from busy. In case it couldn't that means h/w is faulty. - Patch-2: - Added "Acked-by: Simon Glass <sjg(a)chromium.org>". - Patch-3: - New patch. - Patch-4: - Changed command names to lower case in algo struct. - Added generic ace_sha config. - Patch-5: Added acked-by Simon Glass - Added new generic config for ace_sha to enable ace support in hash.c. Changes since v4: - Patch-1: - Added include for clk.h. - Added define for MAX_FREQ. - Added timeout calculation as per frequency. - Changed "i+=4" to "i++" and "len" to "len/4" in for loop at line 591 in this patch. - Added two new functions ace_sha256 and ace_sha1. - Patch-2: None. - Patch-3: - Changed function names in struct algo. - Replaced ACE_SHA_TYPE to CHUNSZ in struct algo. - Patch-4: Added "Acked-by: Simon Glass <sjg(a)chromium.org>". Akshay Saraswat (4): Exynos: Add hardware accelerated SHA 256 Exynos: config: Enable ACE HW for SHA 256 for Exynos gen: Add ACE acceleration to hash Exynos: config: Enable hash command Makefile | 1 + arch/arm/include/asm/arch-exynos/cpu.h | 4 + common/hash.c | 14 ++ drivers/crypto/Makefile | 47 +++++ drivers/crypto/ace_sfr.h | 310 +++++++++++++++++++++++++++++++++ drivers/crypto/ace_sha.c | 138 +++++++++++++++ include/ace_sha.h | 67 +++++++ include/configs/exynos5250-dt.h | 5 + 8 files changed, 586 insertions(+) create mode 100644 drivers/crypto/Makefile create mode 100644 drivers/crypto/ace_sfr.h create mode 100644 drivers/crypto/ace_sha.c create mode 100644 include/ace_sha.h -- 1.8.0

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[U-Boot] I2C register access
by vnr1992 07 Mar '13

07 Mar '13

Hi, I have problem in accessing registers of I2C . I am calling my application from u-boot. In my application i can access registers of I2C1 but can't access registers of I2C2. Is there any thing done in u-boot for initializing I2Ci ; i=1,2,3 for accessing registers? -- View this message in context: http://u-boot.10912.n7.nabble.com/I2C-register-access-tp149189.html Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] driver for davicom dm9601 usb-ethernet NIC
by Beagle board 07 Mar '13

07 Mar '13

Hello Everyone, I'm working on Beagleboard C3, and i'm trying to do an nfs-boot. Please find below my bootup log. I'm getting the below error. After digging into the details of the error, could make out that my Ethernet NIC is not there in the supported drivers list of U-Boot {drivers/usb/eth/} I'm using "Davicom DM9601 USB-Ethernet NIC". I would like to check with u guys whether u've got any drivers for the same? ???40V???�H��?ս��сSPL 2011.12-00010-ga3eb89c (Jan 29 2012 - 14:53:43) Texas Instruments Revision detection unimplemented OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img U-Boot 2013.01 (Feb 22 2013 - 13:00:08) OMAP3530-GP ES3.0, CPU-OPP2, L3-165MHz, Max CPU Clock 600 mHz OMAP3 Beagle board + LPDDR/NAND I2C: ready DRAM: 256 MiB NAND: 256 MiB MMC: OMAP SD/MMC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Beagle Rev C1/C2/C3 timed out in wait_for_pin: I2C_STAT=0 No EEPROM on expansion board timed out in wait_for_pin: I2C_STAT=0 No EEPROM on expansion board Die ID #12ac000300000000040323090f024015 musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn) musb-hdrc: MHDRC RTL version 1.400 musb-hdrc: setup fifo_mode 4 musb-hdrc: 28/31 max ep, 16384/16384 memory USB Peripheral mode controller at 480ab000 using PIO, IRQ 0 Net: usb_ether Hit any key to stop autoboot: 0 mmc0 is current device gpio: pin 173 (gpio 173) value is 1 gpio: pin 7 (gpio 7) value is 0 SD/MMC found on device 0 reading uEnv.txt 769 bytes read in 3 ms (250 KiB/s) Loaded environment from uEnv.txt Importing environment from mmc ... Running uenvcmd ... Initializing net ... (Re)start USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 4 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found Loading kernel ... using musb-hdrc, OUT ep1out IN ep1in MAC 00:60:6e:00:f1:cd *ERROR: The remote end did not respond in time. at ether.c:2395/usb_eth_init()* Booting from nfs ... Wrong Image Format for bootm command ERROR: can't get kernel image!

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Re: [U-Boot] [PATCH 4/5 v4] gen: Add ACE acceleration to hash
by Akshay Saraswat 07 Mar '13

07 Mar '13

Hi Kim, >On Tue, 5 Mar 2013 17:51:00 -0800 >Simon Glass <sjg(a)chromium.org> wrote: > >> Hi Kim, >> >> On Tue, Mar 5, 2013 at 2:43 PM, Kim Phillips <kim.phillips(a)freescale.com> wrote: >> > On Tue, 5 Mar 2013 08:19:59 -0500 >> > Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> > >> >> Tested with command "hash sha256 0x40008000 0x2B 0x40009000". >> >> Used mm and md to write a standard string to memory location >> >> 0x40008000 and ran the above command to verify the output. >> > >> > patches 1,2,4,5 all contain this "tested with" text, yet obviously >> > were not. It also indicates that a data buffer that's > 8MB was not >> > tested? >> >> Would be useful to test a larger transfer. > >esp. since it's now advertised. I have removed "tested with" in the new set of patches. And I tested those patches with that command before mailing for review. I have tested them for various sizes this time which includes 8 MB as well. I have shared benchmark results in another mail. > >> > I also asked about speed relative to software running on the core >> > and didn't get a response. Software should be faster up to >> > a certain buffer size: what is that threshold? >> >> You can fairly easily do that by temporarily modifying your patch to >> use "acesha1" for the name, enable CONFIG_CMD_TIME, then you can >> compare the two with: >> >> time hash sha1 <addr> <size> >> time hash acesha1 <addr> <size> > >sure, but I don't have an ACE - that's why I asked. > >> >> Changes sice v3: >> >> - Changed command names to lower case in algo struct. >> >> - Added generic ace_sha config. >> > >> > I wouldn't call "ace" a generic name - crypto units other than >> > ACE should be able to use this code. >> >> I don't really understand this comment. A new CONFIG has been added, >> and this is specific to that unit. Are you suggesting that it be > >right, and that's the problem - it needn't be specific to that unit. > >> CONFIG_EXYNOS_ACE_SHA? Will the ACE unit not appear on any other SOC? > >my point is other SoCs can use the same entry in the array - there's >nothing h/w-vendor or model-specific about it. > >Something like CONFIG_HW_SHA{1,256} ought to do it. > These instances of struct algo were created specifically for ace because we need function name different for ace to distinguish it from others. Hence, config name includes "ace" as well. >> But I don't think crypto units other than ACE will use the code in >> this patch - it is intended to implement ACE support, and put it ahead >> of software support in terms of priority. > >the same priority that any h/w accelerated device would get - higher >than that of software crypto. > >Another question for Akshay wrt the timeout (since I never got a >reply re: documentation): how can the h/w fault? Regarding documentation, I have replied to that mail itself. Sorry for the delay. Since it is obvious that in case of h/w fault all readl and writel's would result incorrectly and since we know that status register should change it's value quickly, we have a good option to depend upon 100 ms as the time more than enough for wait. And I tried to handle our concern over frequency change and early timeout with the proportional timeout calculation in the new patch. Please have a look. > >Kim Regards, Akshay Saraswat

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[U-Boot] [PATCH v3 0/5] Various USB improvements
by Simon Glass 07 Mar '13

07 Mar '13

This series adds a few USB improvements for Marek: - Support for interupt transfers - Basic 64-bit controller support (used by x86) - Multiple controller support for EHCI PCI Changes in v3: - Set last pointer to correct position in create_int_queue() - Set S-mask bit always, not just on low-speed devices - Correct logic flow in destroy_int_queue() Changes in v2: - Update to use errno - Remove TODOs - Tidy code style a little - Squash timeouts patch into interrupt patch - Add blank line before function return Michael Spang (1): usb: usbeth: smsc95xx: remove EEPROM loaded check Patrick Georgi (1): usb: ehci: Support interrupt transfers via periodic list Simon Glass (1): x86: Enable USB features for coreboot Vincent Palatin (2): usb: ehci: Fix aliasing issue in EHCI interrupt code usb: Add multiple controllers support for EHCI PCI drivers/usb/eth/smsc95xx.c | 4 - drivers/usb/host/ehci-hcd.c | 315 +++++++++++++++++++++++++++++++++++++++++++- drivers/usb/host/ehci-pci.c | 52 +++++++- drivers/usb/host/ehci.h | 6 +- include/configs/coreboot.h | 17 +++ 5 files changed, 379 insertions(+), 15 deletions(-) -- 1.8.1.3

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[U-Boot] [PATCH v2 0/7] Various USB improvements
by Simon Glass 06 Mar '13

06 Mar '13

This series adds a few USB improvements for Marek: - Support for interupt transfers - Faster start-up and proper shutdown of ASIX USB adapter - Basic 64-bit controller support (used by x86) Changes in v2: - Use errno where possible - Use PCI_CLASS_SERIAL_USB_EHCI instead of the number - Update to use errno - Remove TODOs - Tidy code style a little - Squash timeouts patch into interrupt patch - Add blank line before function return Michael Spang (1): usb: usbeth: smsc95xx: remove EEPROM loaded check Patrick Georgi (1): usb: ehci: Support interrupt transfers via periodic list Simon Glass (2): usb: net: asix: Do a fast init if link already established x86: Enable USB features for coreboot Vincent Palatin (3): usb: ehci: generic PCI support usb: ehci: Fix aliasing issue in EHCI interrupt code usb: Add multiple controllers support for EHCI PCI drivers/usb/eth/asix.c | 40 +++++- drivers/usb/eth/smsc95xx.c | 4 - drivers/usb/host/ehci-hcd.c | 315 ++++++++++++++++++++++++++++++++++++++++++- drivers/usb/host/ehci-pci.c | 61 ++++++++- drivers/usb/host/ehci.h | 6 +- include/configs/coreboot.h | 17 +++ include/usb_ether.h | 1 + 7 files changed, 420 insertions(+), 24 deletions(-) -- 1.7.7.3

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[U-Boot] [PATCH v4] addition of btrfs to u-boot
by Adnan Ali 06 Mar '13

06 Mar '13

Adnan Ali (1): Introduced btrfs file-system with btrload command Makefile | 1 + common/Makefile | 1 + common/cmd_btr.c | 65 +++ fs/btrfs/Makefile | 51 ++ fs/btrfs/btrfs.c | 1209 ++++++++++++++++++++++++++++++++++++++++++++ fs/btrfs/crc32_c.c | 54 ++ fs/fs.c | 86 +++- include/btrfs.h | 391 ++++++++++++++ include/config_fallbacks.h | 4 + include/fs.h | 1 + 10 files changed, 1860 insertions(+), 3 deletions(-) create mode 100644 common/cmd_btr.c create mode 100644 fs/btrfs/Makefile create mode 100644 fs/btrfs/btrfs.c create mode 100644 fs/btrfs/crc32_c.c create mode 100644 include/btrfs.h -- 1.7.9.5

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Re: [U-Boot] [PATCH 1/4 v3] Exynos: Add hardware accelerated SHA 256
by Akshay Saraswat 06 Mar '13

06 Mar '13

Hi Kim, >On Fri, 1 Mar 2013 11:16:22 -0500 >Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >> SHA-256 and SHA-1 accelerated using ACE hardware. > >curious about the rationale: how much faster is this than software? > Time taken by s/w and h/w sha256 are as given below: Size: 0x1000 s/w - 11 ticks h/w - 10 ticks Size: 0x2000 s/w - 11 ticks h/w - 10 ticks Size: 0x4000 s/w - 13 ticks h/w - 10 ticks Size: 0x8000 s/w - 16 ticks h/w - 10 ticks Size: 0x800000 s/w - 1775 ticks h/w - 45 ticks Size: 0x400000 s/w - 893 ticks h/w - 27 ticks Size: 0x200000 s/w - 451 ticks h/w - 18 ticks Size: 0x8000000 s/w - 28270 ticks h/w - 110 ticks Size: 0x40000000 s/w - 225896 ticks h/w - 110 ticks >> --- >> Changes since v2: >> - Added falling back to software sha256 in case length exceeds buffer limit. >> - Reduced one tab at lines 533, 559 and 571 in this patch. >> - Removed space after a cast at line 506 in this patch. >> - Removed blank line at line 561 in this patch. >> - Removed space before semicolon at line 576 in this patch. > >you should retain the list of changes since v1 here. Read: > >http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions > >> +/* Hash status */ >> +#define ACE_HASH_BUFRDY_MASK (1 << 0) >> +#define ACE_HASH_BUFRDY_OFF (0 << 0) >> +#define ACE_HASH_BUFRDY_ON (1 << 0) >> +#define ACE_HASH_SEEDSETTING_MASK (1 << 1) >> +#define ACE_HASH_SEEDSETTING_OFF (0 << 1) >> +#define ACE_HASH_SEEDSETTING_ON (1 << 1) >> +#define ACE_HASH_PRNGBUSY_MASK (1 << 2) >> +#define ACE_HASH_PRNGBUSY_OFF (0 << 2) >> +#define ACE_HASH_PRNGBUSY_ON (1 << 2) >> +#define ACE_HASH_PARTIALDONE_MASK (1 << 4) >> +#define ACE_HASH_PARTIALDONE_OFF (0 << 4) >> +#define ACE_HASH_PARTIALDONE_ON (1 << 4) > >based on the nomenclature of the above definitions, this hardware >obviously has support for breaking up hash requests into multiple >buffer submissions, so do that, and not this: > >> + } else if (buf_len > BUF_LIMIT) { >> + /* >> + * ACE H/W cannot compute hash value for buffer > 8 MB. >> + * Falling back to software. >> + */ >> + if (hash_type == ACE_SHA_TYPE_SHA1) >> + sha1_csum_wd(pbuf, buf_len, pout, CHUNKSZ_SHA1); >> + else >> + sha256_csum_wd(pbuf, buf_len, pout, CHUNKSZ_SHA256); >> + return 0; >> + } > >Kim > Regards, Akshay Saraswat

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Re: [U-Boot] [PATCH 1/4] Exynos: Add hardware accelerated SHA 256
by Akshay Saraswat 06 Mar '13

06 Mar '13

Hi Kim, >On Fri, 1 Mar 2013 16:11:36 +0000 >Akshay Saraswat <akshay.s(a)samsung.com> wrote: > >> Samsung Enterprise Portal mySingle >> >> >> >> Hi Kim, >> >> >> >> >On Thu, 28 Feb 2013 11:08:21 +0000 >> >> >Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> >As you can see, no. It looks like you didn't change anything. I >have to manually single-space things below. > >> >> So, I have incremented this value >> >> to 500 which shall be good enough for the lowest of all frequencies. But I guess what we >> >> need here is some formula, to calculate timeout on the basis of frequency, which is nowhere >> >> defined. >> >> >That's odd - I see a bunch of frequencies advertised in >> >arch/arm/cpu/armv7/exynos/clock.c. >> >Or how about using a cycle counter instead? >> >btw, where can I find documentation for the ACE? >> >> I tried with different frequencies and data sizes and found that it takes 2 to 3 msecs in all the cases. >> Since, it is hardware accelerated encoding it is supposed to behave in this same manner. >> But the current version of u-boot behaves mysteriously and slow downs when pressed enter for long. >> In the above case mentioned I even saw time took to be more than 100 msecs for all the cases. >> I think it would not be a better idea to timeout encoding acceleration. >> But still if it is needed, cycle counter suggestion would be a great solution. > >it depends on whether the h/w can fault during its operation. > >> You can read Exynos5250 manual's "Security subsystem" section, which I referred for this. > >you mean this?: > >http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_… Yes, this is the manual. But this ine is just a part of it which has been made public by Samsung. The one I have has 64 chapters in it and security subsystems is the 57th chapter. > >There is no "Security subsystem" section. > >Kim > Regards, Akshay Saraswat

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[U-Boot] [PATCH] VCMA9: Enable CONFIG_CMD_NAND_YAFFS
by Tom Rini 06 Mar '13

06 Mar '13

As this board has NAND and supports YAFFS2, add CONFIG_MD_NAND_YAFFS Cc: David Müller <d.mueller(a)elsoft.ch> Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/VCMA9.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index fb7d922..2b3d59f 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -77,6 +77,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_YAFFS #define CONFIG_BOARD_LATE_INIT -- 1.7.9.5

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