March 2013 - U-Boot

[U-Boot] [PATCH v9 09/31] Introduce generic pre-relocation board_f.c
by Simon Glass 11 Mar '13

11 Mar '13

This file handles common pre-relocation init for boards which use the generic framework. It starts up the console, DRAM, performs relocation and then jumps to post-relocation init. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v9: - Rebase x86 global_data patch on top of mainline Changes in v8: None Changes in v7: None Changes in v6: - Tidy up stack reservation code to separate out ARM - Fix up ordering of dram init (specifically to get ARM SPL boards to boot) - Add debug() to show RAM top - Adjust the way the top of memory is calculated Changes in v5: - Add fdtdec header file to board_f.c - Remove setup_global_data_ptr() - Tidy up stack init - Put global data on stack in board_init_f() - Add fdt relocation - Remove fdt relocation field from x86 arch_global_data - Deal with change of board_init_f() semantics on ARM - Save boot_flags in global_data in board_init_f() - Add print_cpuinfo() prototype to include/common.h Changes in v4: - Use asm/sections.h instead of asm-generic/sections.h Changes in v3: - Cast away the volatile on gd for memcpy() Changes in v2: None arch/x86/lib/board.c | 2 +- arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/relocate.c | 8 +- common/Makefile | 3 + common/board_f.c | 579 ++++++++++++++++++++++++++++++++++++++ include/asm-generic/global_data.h | 2 + include/common.h | 1 + 7 files changed, 591 insertions(+), 6 deletions(-) create mode 100644 common/board_f.c diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 2441a66..555301a 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -219,7 +219,7 @@ static void do_init_loop(init_fnc_t **init_fnc_ptr) void board_init_f(ulong boot_flags) { - gd->fdt_blob = gd->arch.new_fdt = NULL; + gd->fdt_blob = gd->new_fdt = NULL; gd->flags = boot_flags; do_init_loop(init_sequence_f); diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 414fdcc..7df9536 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -111,7 +111,7 @@ int calculate_relocation_address(void) */ if (gd->fdt_blob) { dest_addr -= fdt_size; - gd->arch.new_fdt = (void *)dest_addr; + gd->new_fdt = (void *)dest_addr; dest_addr &= ~15; } #endif diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 3e370f2..e893c2b 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -49,15 +49,15 @@ int copy_uboot_to_ram(void) int copy_fdt_to_ram(void) { - if (gd->arch.new_fdt) { + if (gd->new_fdt) { ulong fdt_size; fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); - memcpy(gd->arch.new_fdt, gd->fdt_blob, fdt_size); + memcpy(gd->new_fdt, gd->fdt_blob, fdt_size); debug("Relocated fdt from %p to %p, size %lx\n", - gd->fdt_blob, gd->arch.new_fdt, fdt_size); - gd->fdt_blob = gd->arch.new_fdt; + gd->fdt_blob, gd->new_fdt, fdt_size); + gd->fdt_blob = gd->new_fdt; } return 0; diff --git a/common/Makefile b/common/Makefile index 719fc23..a5f5b1a 100644 --- a/common/Makefile +++ b/common/Makefile @@ -36,6 +36,9 @@ COBJS-y += s_record.o COBJS-y += xyzModem.o COBJS-y += cmd_disk.o +# boards +COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o + # core command COBJS-y += cmd_boot.o COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o diff --git a/common/board_f.c b/common/board_f.c new file mode 100644 index 0000000..d674f9d --- /dev/null +++ b/common/board_f.c @@ -0,0 +1,579 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/compiler.h> +#include <version.h> +#include <environment.h> +#include <fdtdec.h> +#include <initcall.h> +#include <logbuff.h> +#include <post.h> +#include <asm/io.h> +#include <asm/sections.h> +#include <linux/compiler.h> + +/* + * Pointer to initial global data area + * + * Here we initialize it if needed. + */ +#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR +#undef XTRN_DECLARE_GLOBAL_DATA_PTR +#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ +DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); +#else +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* + * sjg: IMO this code should be + * refactored to a single function, something like: + * + * void led_set_state(enum led_colour_t colour, int on); + */ +/************************************************************************ + * Coloured LED functionality + ************************************************************************ + * May be supplied by boards if desired + */ +inline void __coloured_LED_init(void) {} +void coloured_LED_init(void) + __attribute__((weak, alias("__coloured_LED_init"))); +inline void __red_led_on(void) {} +void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); +inline void __red_led_off(void) {} +void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); +inline void __green_led_on(void) {} +void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); +inline void __green_led_off(void) {} +void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); +inline void __yellow_led_on(void) {} +void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); +inline void __yellow_led_off(void) {} +void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); +inline void __blue_led_on(void) {} +void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); +inline void __blue_led_off(void) {} +void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); + +/* + * Why is gd allocated a register? Prior to reloc it might be better to + * just pass it around to each function in this file? + * + * After reloc one could argue that it is hardly used and doesn't need + * to be in a register. Or if it is it should perhaps hold pointers to all + * global data for all modules, so that post-reloc we can avoid the massive + * literal pool we get on ARM. Or perhaps just encourage each module to use + * a structure... + */ + +/* + * Could the CONFIG_SPL_BUILD infection become a flag in gd? + */ + +static int init_baud_rate(void) +{ + gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); + return 0; +} + +static int display_text_info(void) +{ + ulong bss_start, bss_end; + + bss_start = _bss_start_ofs + _TEXT_BASE; + bss_end = _bss_end_ofs + _TEXT_BASE; + debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", + CONFIG_SYS_TEXT_BASE, bss_start, bss_end); + +#ifdef CONFIG_MODEM_SUPPORT + debug("Modem Support enabled\n"); +#endif +#ifdef CONFIG_USE_IRQ + debug("IRQ Stack: %08lx\n", IRQ_STACK_START); + debug("FIQ Stack: %08lx\n", FIQ_STACK_START); +#endif + + return 0; +} + +static int announce_dram_init(void) +{ + puts("DRAM: "); + return 0; +} + +static int show_dram_config(void) +{ + ulong size; + +#ifdef CONFIG_NR_DRAM_BANKS + int i; + + debug("\nRAM Configuration:\n"); + for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + size += gd->bd->bi_dram[i].size; + debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); +#ifdef DEBUG + print_size(gd->bd->bi_dram[i].size, "\n"); +#endif + } + debug("\nDRAM: "); +#else + size = gd->ram_size; +#endif + + print_size(size, "\n"); + + return 0; +} + +void __dram_init_banksize(void) +{ +#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_effective_memsize(); +#endif +} + +void dram_init_banksize(void) + __attribute__((weak, alias("__dram_init_banksize"))); + +static int zero_global_data(void) +{ + memset((void *)gd, '\0', sizeof(gd_t)); + + return 0; +} + +static int setup_mon_len(void) +{ + gd->mon_len = _bss_end_ofs; + return 0; +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +static int setup_fdt(void) +{ +#ifdef CONFIG_OF_EMBED + /* Get a pointer to the FDT */ + gd->fdt_blob = _binary_dt_dtb_start; +#elif defined CONFIG_OF_SEPARATE + /* FDT is at end of image */ + gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); +#endif + /* Allow the early environment to override the fdt address */ + gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, + (uintptr_t)gd->fdt_blob); + return 0; +} + +/* Get the top of usable RAM */ +__weak ulong board_get_usable_ram_top(ulong total_size) +{ + return gd->ram_top; +} + +static int setup_dest_addr(void) +{ + debug("Monitor len: %08lX\n", gd->mon_len); + /* + * Ram is setup, size stored in gd !! + */ + debug("Ram size: %08lX\n", (ulong)gd->ram_size); +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif +#ifdef CONFIG_SYS_SDRAM_BASE + gd->ram_top = CONFIG_SYS_SDRAM_BASE; +#endif + gd->ram_top = board_get_usable_ram_top(gd->mon_len); + gd->dest_addr = gd->ram_top; + debug("Ram top: %08lX\n", (ulong)gd->ram_top); + gd->dest_addr_sp = gd->dest_addr; + return 0; +} + +#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) +static int reserve_logbuffer(void) +{ + /* reserve kernel log buffer */ + gd->dest_addr -= LOGBUFF_RESERVE; + debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, + gd->dest_addr); + return 0; +} +#endif + +#ifdef CONFIG_PRAM +/* reserve protected RAM */ +static int reserve_pram(void) +{ + ulong reg; + + reg = getenv_ulong("pram", 10, CONFIG_PRAM); + gd->dest_addr -= (reg << 10); /* size is in kB */ + debug("Reserving %ldk for protected RAM at %08lx\n", reg, + gd->dest_addr); + return 0; +} +#endif /* CONFIG_PRAM */ + +/* Round memory pointer down to next 4 kB limit */ +static int reserve_round_4k(void) +{ + gd->dest_addr &= ~(4096 - 1); + return 0; +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ + defined(CONFIG_ARM) +static int reserve_mmu(void) +{ + /* reserve TLB table */ + gd->arch.tlb_size = 4096 * 4; + gd->dest_addr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->dest_addr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->dest_addr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + return 0; +} +#endif + +#ifdef CONFIG_LCD +static int reserve_lcd(void) +{ +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else + /* reserve memory for LCD display (always full pages) */ + gd->dest_addr = lcd_setmem(gd->dest_addr); + gd->fb_base = gd->dest_addr; +#endif /* CONFIG_FB_ADDR */ + return 0; +} +#endif /* CONFIG_LCD */ + +static int reserve_uboot(void) +{ + /* + * reserve memory for U-Boot code, data & bss + * round down to next 4 kB limit + */ + gd->dest_addr -= gd->mon_len; + gd->dest_addr &= ~(4096 - 1); + + debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, + gd->dest_addr); + return 0; +} + +/* reserve memory for malloc() area */ +static int reserve_malloc(void) +{ + gd->dest_addr_sp = gd->dest_addr - TOTAL_MALLOC_LEN; + debug("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, gd->dest_addr_sp); + return 0; +} + +/* (permanently) allocate a Board Info struct */ +static int reserve_board(void) +{ + gd->dest_addr_sp -= sizeof(bd_t); + gd->bd = (bd_t *)gd->dest_addr_sp; + memset(gd->bd, '\0', sizeof(bd_t)); + debug("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof(bd_t), gd->dest_addr_sp); + return 0; +} + +static int setup_machine(void) +{ +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + return 0; +} + +static int reserve_global_data(void) +{ + gd->dest_addr_sp -= sizeof(gd_t); + gd->new_gd = (gd_t *)gd->dest_addr_sp; + debug("Reserving %zu Bytes for Global Data at: %08lx\n", + sizeof(gd_t), gd->dest_addr_sp); + return 0; +} + +static int reserve_fdt(void) +{ + /* + * If the device tree is sitting immediate above our image then we + * must relocate it. If it is embedded in the data section, then it + * will be relocated with other data. + */ + if (gd->fdt_blob) { + gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); + + gd->dest_addr_sp -= gd->fdt_size; + gd->new_fdt = (void *)gd->dest_addr_sp; + debug("Reserving %lu Bytes for FDT at: %p\n", + gd->fdt_size, gd->new_fdt); + } + + return 0; +} + +static int reserve_stacks(void) +{ + /* setup stack pointer for exceptions */ + gd->dest_addr_sp -= 16; + gd->dest_addr_sp &= ~0xf; + gd->irq_sp = gd->dest_addr_sp; + + /* + * Handle architecture-specific things here + * TODO(sjg(a)chromium.org): Perhaps create arch_reserve_stack() + * to handle this and put in arch/xxx/lib/stack.c + */ +# ifdef CONFIG_ARM +# ifdef CONFIG_USE_IRQ + gd->dest_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->dest_addr_sp); + + /* 8-byte alignment for ARM ABI compliance */ + gd->dest_addr_sp &= ~0x07; +# endif + /* leave 3 words for abort-stack, plus 1 for alignment */ + gd->dest_addr_sp -= 16; + + return 0; +} + +static int display_new_sp(void) +{ + debug("New Stack Pointer is: %08lx\n", gd->dest_addr_sp); + + return 0; +} + +#ifdef CONFIG_POST +static int init_post(void) +{ + post_bootmode_init(); + post_run(NULL, POST_ROM | post_bootmode_get(0)); + + return 0; +} +#endif + +static int setup_baud_rate(void) +{ + /* Ick, can we get rid of this line? */ + gd->bd->bi_baudrate = gd->baudrate; + + return 0; +} + +static int setup_dram_config(void) +{ + /* Ram is board specific, so move it to board code ... */ + dram_init_banksize(); + + return 0; +} + +static int reloc_fdt(void) +{ + if (gd->new_fdt) { + memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); + gd->fdt_blob = gd->new_fdt; + } + + return 0; +} + +static int setup_reloc(void) +{ + gd->relocaddr = gd->dest_addr; + gd->start_addr_sp = gd->dest_addr_sp; + gd->reloc_off = gd->dest_addr - CONFIG_SYS_TEXT_BASE; + memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); + + debug("Relocation Offset is: %08lx\n", gd->reloc_off); + debug("Relocating to %08lx, new gd at %p, sp at %08lx\n", + gd->dest_addr, gd->new_gd, gd->dest_addr_sp); + + return 0; +} + +/* ARM calls relocate_code from its crt0.S */ +#if !defined(CONFIG_ARM) + +static int jump_to_copy(void) +{ + relocate_code(gd->dest_addr_sp, gd->new_gd, gd->dest_addr); + + return 0; +} +#endif + +/* Record the board_init_f() bootstage (after arch_cpu_init()) */ +static int mark_bootstage(void) +{ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); + + return 0; +} + +static init_fnc_t init_sequence_f[] = { + setup_fdt, + setup_mon_len, + arch_cpu_init, /* basic arch cpu dependent setup */ + mark_bootstage, +#ifdef CONFIG_OF_CONTROL + fdtdec_check_fdt, +#endif +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, +#endif + timer_init, /* initialize timer */ +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init, +#endif +#ifdef CONFIG_FSL_ESDHC + get_clocks, +#endif + env_init, /* initialize environment */ + init_baud_rate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, /* stage 1 init of console */ + display_options, /* say that we are here */ + display_text_info, /* show debugging info if required */ +#if defined(CONFIG_DISPLAY_CPUINFO) + print_cpuinfo, /* display cpu info (and speed) */ +#endif +#if defined(CONFIG_DISPLAY_BOARDINFO) + checkboard, /* display board info */ +#endif + announce_dram_init, + /* TODO: unify all these dram functions? */ +#ifdef CONFIG_ARM + dram_init, /* configure available RAM banks */ +#endif +#ifdef CONFIG_POST + init_post, +#endif + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + * + * Reserve memory at end of RAM for (top down in that order): + * - area that won't get touched by U-Boot and Linux (optional) + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + */ + setup_dest_addr, +#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) + reserve_logbuffer, +#endif +#ifdef CONFIG_PRAM + reserve_pram, +#endif + reserve_round_4k, +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ + defined(CONFIG_ARM) + reserve_mmu, +#endif +#ifdef CONFIG_LCD + reserve_lcd, +#endif + reserve_uboot, + reserve_malloc, + reserve_board, + setup_machine, + reserve_global_data, + reserve_fdt, + reserve_stacks, + setup_dram_config, + show_dram_config, + setup_baud_rate, + display_new_sp, + reloc_fdt, + setup_reloc, +#ifndef CONFIG_ARM + jump_to_copy, +#endif + NULL, +}; + +void board_init_f(ulong boot_flags) +{ + gd_t data; + + gd = &data; + + gd->flags = boot_flags; + + if (initcall_run_list(init_sequence_f)) + hang(); + +#ifndef CONFIG_ARM + /* NOTREACHED - jump_to_copy() does not return */ + hang(); +#endif +} + +void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index b8ac024..ebfe2a3 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -81,6 +81,8 @@ typedef struct global_data { unsigned long reloc_off; struct global_data *new_gd; /* relocated global data */ const void *fdt_blob; /* Our device tree, NULL if none */ + void *new_fdt; /* Relocated FDT */ + unsigned long fdt_size; /* Space reserved for relocated FDT */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ struct arch_global_data arch; /* architecture-specific data */ diff --git a/include/common.h b/include/common.h index 6d52924..2ff8db1 100644 --- a/include/common.h +++ b/include/common.h @@ -311,6 +311,7 @@ extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +int print_cpuinfo(void); /** * Show the DRAM size in a board-specific way -- 1.8.1.3

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[U-Boot] [PATCH V2] Add Boundary Devices Nitrogen6X boards
by Eric Nelson 11 Mar '13

11 Mar '13

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- Changes for V2: - Update tXS, tXPR as noted by Benoît Thébaudeau - Use struct hdmi_regs and readb()/writeb() as noted by Wolfgang Denk - Use get_ram_size() instead of imx_ddr_size() - Remote unneeded CONFIG_ARP_TIMEOUT MAINTAINERS | 8 + board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg | 58 ++ board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/6x_bootscript.txt | 63 ++ .../boundary/nitrogen6x/6x_bootscript_android.txt | 64 ++ .../nitrogen6x/6x_bootscript_android_recovery.txt | 64 ++ board/boundary/nitrogen6x/6x_upgrade.txt | 45 + board/boundary/nitrogen6x/800mhz_2x128mx16.cfg | 58 ++ board/boundary/nitrogen6x/800mhz_2x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/800mhz_4x128mx16.cfg | 57 ++ board/boundary/nitrogen6x/800mhz_4x256mx16.cfg | 58 ++ board/boundary/nitrogen6x/Makefile | 41 + board/boundary/nitrogen6x/README | 92 ++ board/boundary/nitrogen6x/clocks.cfg | 46 + board/boundary/nitrogen6x/ddr-setup.cfg | 112 +++ board/boundary/nitrogen6x/nitrogen6dl.cfg | 45 + board/boundary/nitrogen6x/nitrogen6dl2g.cfg | 45 + board/boundary/nitrogen6x/nitrogen6q.cfg | 45 + board/boundary/nitrogen6x/nitrogen6q2g.cfg | 45 + board/boundary/nitrogen6x/nitrogen6s.cfg | 45 + board/boundary/nitrogen6x/nitrogen6s1g.cfg | 45 + board/boundary/nitrogen6x/nitrogen6x.c | 895 ++++++++++++++++++++ boards.cfg | 6 + include/configs/nitrogen6x.h | 286 +++++++ 24 files changed, 2339 insertions(+) create mode 100644 board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/6x_bootscript.txt create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android.txt create mode 100644 board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt create mode 100644 board/boundary/nitrogen6x/6x_upgrade.txt create mode 100644 board/boundary/nitrogen6x/800mhz_2x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_2x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_4x128mx16.cfg create mode 100644 board/boundary/nitrogen6x/800mhz_4x256mx16.cfg create mode 100644 board/boundary/nitrogen6x/Makefile create mode 100644 board/boundary/nitrogen6x/README create mode 100644 board/boundary/nitrogen6x/clocks.cfg create mode 100644 board/boundary/nitrogen6x/ddr-setup.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6dl.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6dl2g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6q.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6q2g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6s.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6s1g.cfg create mode 100644 board/boundary/nitrogen6x/nitrogen6x.c create mode 100644 include/configs/nitrogen6x.h diff --git a/MAINTAINERS b/MAINTAINERS index 175bbe2..f490d62 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1037,6 +1037,14 @@ Pali Rohár <pali.rohar(a)gmail.com> nokia_rx51 ARM ARMV7 (OMAP34xx SoC) +Eric Nelson <eric.nelson(a)boundarydevices.com> + nitrogen6dl i.MX6DL 1GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6q i.MX6Q/6D 1GB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6s i.MX6S 512MB + nitrogen6s1g i.MX6S 1GB + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg new file mode 100644 index 0000000..16a37d0 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg new file mode 100644 index 0000000..0607703 --- /dev/null +++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt new file mode 100644 index 0000000..061b3a4 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript.txt @@ -0,0 +1,63 @@ +setenv bootargs enable_wait_mode=off +setenv nextcon 0; + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + setenv fbmem "fbmem=28M"; + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +i2c dev 2 +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbmem "fbmem=10M"; + else + setenv fbmem ${fbmem},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs $fbmem +setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait" + +if test "sata" = "${dtype}" ; then + setenv bootargs "$bootargs root=/dev/sda1" ; +else + setenv "bootargs $bootargs root=/dev/mmcblk0p1" ; +fi +${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ; +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt new file mode 100644 index 0000000..0982cf8 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt @@ -0,0 +1,64 @@ +${dtype} dev ${disk} + +setenv bootargs enable_wait_mode=off +setenv nextcon 0; +setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ; + +i2c dev 2 + +if i2c probe 0x04 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no Freescale display"; +fi + +if i2c probe 0x38 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 1024x600 display"; +fi + +if i2c probe 0x48 ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=10M"; + else + setenv fbcon ${fbcon},10M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no 800x480 display"; +fi + +if hdmidet ; then + setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24 + if test "0" -eq $nextcon; then + setenv fbcon "fbcon=28M"; + else + setenv fbcon ${fbcon},28M + fi + setexpr nextcon $nextcon + 1 +else + echo "------ no HDMI monitor"; +fi + +while test "3" -ne $nextcon ; do + setenv bootargs $bootargs video=mxcfb${nextcon}:off ; + setexpr nextcon $nextcon + 1 ; +done + +setenv bootargs $bootargs fbcon=$fbcon +${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000 +echo "Error loading kernel image" diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt new file mode 100644 index 0000000..0d8e8e5 --- /dev/null +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -0,0 +1,45 @@ +setenv stdout serial,vga +echo "check U-Boot" ; +setenv offset 0x400 +if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then + echo "read $filesize bytes from SD card" ; + if sf probe || sf probe || \ + sf probe 1 27000000 || sf probe 1 27000000 ; then + echo "probed SPI ROM" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + echo "------- U-Boot versions match" ; + else + echo "Need U-Boot upgrade" ; + echo "Program in 5 seconds" ; + for n in 5 4 3 2 1 ; do + echo $n ; + sleep 1 ; + done + echo "erasing" ; + sf erase 0 0x50000 ; + # two steps to prevent bricking + echo "programming" ; + sf write 0x12000000 $offset $filesize ; + echo "verifying" ; + if sf read 0x12400000 $offset $filesize ; then + if cmp.b 0x12000000 0x12400000 $filesize ; then + while echo "---- U-Boot upgraded. reset" ; do + sleep 120 + done + else + echo "Read verification error" ; + fi + else + echo "Error re-reading EEPROM" ; + fi + fi + else + echo "Error reading boot loader from EEPROM" ; + fi + else + echo "Error initializing EEPROM" ; + fi ; +else + echo "No U-Boot image found on SD card" ; +fi diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg new file mode 100644 index 0000000..de33e65 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg new file mode 100644 index 0000000..19707cf --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg new file mode 100644 index 0000000..dd6a423 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 +DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038 +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg new file mode 100644 index 0000000..d5d06e2 --- /dev/null +++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D +DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023 +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile new file mode 100644 index 0000000..fe1e5e0 --- /dev/null +++ b/board/boundary/nitrogen6x/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg(a)denx.de> +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices <info(a)boundarydevices.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := nitrogen6x.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README new file mode 100644 index 0000000..5049093 --- /dev/null +++ b/board/boundary/nitrogen6x/README @@ -0,0 +1,92 @@ +U-Boot for the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards + +This file contains information for the port of +U-Boot to the Boundary Devices Nitrogen6X and +Freescale i.MX6Q SabreLite boards. + +1. Boot source, boot from SPI NOR +--------------------------------- +The configuration in this directory supports both the +Nitrogen6X and Freescale SabreLite board, but in a +different fashion from Freescale's implementation in +board/freescale/mx6qsabrelite. + +In particular, this image supports booting from SPI NOR +and saving the environment to SPI NOR. + +It does not support 'boot from SD' at offset 0x400 +except through the 'bmode' command. + http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + +2. Boots using 6x_bootscript on SATA or SD card +----------------------------------------------- +The default bootcmd for these boards is configured +to look for and source a boot script named '6x_bootscript' +in the root of the first partition of the following +devices: + + sata 0 + mmc 0 + mmc 1 + +They're searched in the order listed above, trying both the +ext2 and fat filesystems. + +2. Maintaining the SPI NOR +-------------------------- +A couple of convenience commands + + clearenv - clear environment to factory default + upgradeu - look and source a boot script named + '6x_upgrade' to upgrade the U-Boot version + in SPI NOR. The search is the same as for + 6x_bootscript described above. + +3. Display support +------------------ +U-Boot support for the following displays is configured by +default: + + HDMI - 1024 x 768 for maximum compatibility + Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1) + wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600) + wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480) + +Since the ipuv3_fb display driver currently supports only a single display, +this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect +or the I2C touch controller of the LVDS and RGB displays in the priority +listed above. + +Setting 'panel' environment variable to one of the names above will +override auto-detection and force activation of the specified panel. + +4. Building +------------ + +To build U-Boot for one of the Nitrogen6x or SabreLite board: + + make nitrogen6x_config + make u-boot.imx + +Note that 'nitrogen6x' is a placeholder. The complete list of supported +board configurations is shown in tha MAINTAINERS file: + nitrogen6q i.MX6Q/6D 1GB + nitrogen6dl i.MX6DL 1GB + nitrogen6s i.MX6S 512MB + nitrogen6q2g i.MX6Q/6D 2GB + nitrogen6dl2g i.MX6DL 2GB + nitrogen6s1g i.MX6S 1GB + +The -6q variants support either the i.MX6Quad or i.MX6Dual processors +and are configured for a 64-bit memory bus at 1066 MHz. + +The -6dl variants also use a 64-bit memory bus, operated at 800MHz. + +The -6s variants use a 32-bit memory bus at 800MHz. + +If you place the u-boot.imx into a single-partition SD card +along with a binary version of the boot script 6x_upgrade.txt, +you can program it using 'upgradeu': + + U-Boot> run upgradeu diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg new file mode 100644 index 0000000..e7d1f86 --- /dev/null +++ b/board/boundary/nitrogen6x/clocks.cfg @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg new file mode 100644 index 0000000..c315812 --- /dev/null +++ b/board/boundary/nitrogen6x/ddr-setup.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 + +DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 + +DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 + +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 + +/* (differential input) */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* (differential input) */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* disable ddr pullups */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 + +/* Read data DQ Byte0-3 delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 + +/* + * MDMISC mirroring interleaved (row/bank/col) + */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 + +/* + * MDSCR con_req + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg new file mode 100644 index 0000000..d6da96c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg new file mode 100644 index 0000000..0b1c35c --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg new file mode 100644 index 0000000..680a853 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg new file mode 100644 index 0000000..f57ab0e --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "1066mhz_4x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg new file mode 100644 index 0000000..b5af5cc --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x128mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg new file mode 100644 index 0000000..5aeefc8 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2013 Boundary Devices + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "ddr-setup.cfg" +#include "800mhz_2x256mx16.cfg" +#include "clocks.cfg" diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c new file mode 100644 index 0000000..147bd91 --- /dev/null +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -0,0 +1,895 @@ +/* + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013, Boundary Devices <info(a)boundarydevices.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +#include <malloc.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <micrel.h> +#include <miiphy.h> +#include <netdev.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mxc_hdmi.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_SRE_SLOW) + +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1, SGTL5000 */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2 Camera, MIPI */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3, J15 - RGB connector */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* wl1271 pads on nitrogen6x */ +iomux_v3_cfg_t const wl12xx_pads[] = { + (MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(WEAK_PULLDOWN), + (MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), + (MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK) + | MUX_PAD_CTRL(OUTPUT_40OHM), +}; +#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14) +#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15) +#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16) + +/* Button assignments for J14 */ +static iomux_v3_cfg_t const button_pads[] = { + /* Menu */ + MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */ + gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */ + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */ + gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */ + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(IMX_GPIO_NR(7, 12), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(7, 12), 1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(IMX_GPIO_NR(7, 0)); + ret = !gpio_get_value(IMX_GPIO_NR(7, 0)); + } else { + gpio_direction_input(IMX_GPIO_NR(2, 6)); + ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +u32 get_board_rev(void) +{ + return 0x63000; +} + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +int board_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + uint32_t base = IMX_FEC_BASE; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + bus = fec_get_miibus(base, -1); + if (!bus) + return 0; + /* scan phy 4,5,6,7 */ + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + free(bus); + return 0; + } + printf("using phy at %d\n", phydev->addr); + ret = fec_probe(bis, -1, base, bus, phydev); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + free(phydev); + free(bus); + } +#endif + return 0; +} + +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} +#endif + +#if defined(CONFIG_VIDEO_IPUV3) + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight on RGB connector: J15 */ + MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) + + /* Backlight on LVDS connector: J6 */ + MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) +}; + +static iomux_v3_cfg_t const rgb_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DI0_PIN4__GPIO_4_20, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, +}; + +struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + + +static int detect_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + printf("%s: setup HDMI monitor\n", __func__); + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static int detect_i2c(struct display_info_t const *dev) +{ + return ((0 == i2c_set_bus_num(dev->bus)) + && + (0 == i2c_probe(dev->addr))); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *) + IOMUXC_BASE_ADDR; + u32 reg = readl(&iomux->gpr[2]); + reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT; + writel(reg, &iomux->gpr[2]); + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); +} + +static void enable_rgb(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads( + rgb_pads, + ARRAY_SIZE(rgb_pads)); + gpio_direction_output(RGB_BACKLIGHT_GP, 1); +} + +static struct display_info_t const displays[] = {{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x4, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x38, + .pixfmt = IPU_PIX_FMT_LVDS666, + .detect = detect_i2c, + .enable = enable_lvds, + .mode = { + .name = "wsvga-lvds", + .refresh = 60, + .xres = 1024, + .yres = 600, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = 2, + .addr = 0x48, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = detect_i2c, + .enable = enable_rgb, + .mode = { + .name = "wvga-rgb", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays+i; + if (dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, + displays[i].pixfmt); + if (!ret) { + displays[i].enable(displays+i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, + displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + ret = -EINVAL; + } + return (0 != ret); +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + + int reg; + + /* Turn on LDB0,IPU,IPU DI0 clocks */ + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET + |MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); + + /* Turn on HDMI PHY clock */ + reg = __raw_readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK + |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + + /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */ + writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr); + writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + reg = readl(&mxc_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &mxc_ccm->cscmr2); + + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK + |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + |(CHSCCDR_PODF_DIVIDE_BY_3 + <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + /* backlights off until needed */ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + gpio_direction_input(LVDS_BACKLIGHT_GP); + gpio_direction_input(RGB_BACKLIGHT_GP); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + /* Disable wl1271 For Nitrogen6w */ + gpio_direction_input(WL12XX_WL_IRQ_GP); + gpio_direction_output(WL12XX_WL_ENABLE_GP, 0); + gpio_direction_output(WL12XX_BT_ENABLE_GP, 0); + + imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads)); + setup_buttons(); + +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + + return 0; +} + +int checkboard(void) +{ + if (gpio_get_value(WL12XX_WL_IRQ_GP)) + puts("Board: Nitrogen6X\n"); + else + puts("Board: SABRE Lite\n"); + + return 0; +} + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", IMX_GPIO_NR(2, 2), 'B'}, + {"home", IMX_GPIO_NR(2, 4), 'H'}, + {"menu", IMX_GPIO_NR(2, 1), 'M'}, + {"search", IMX_GPIO_NR(2, 3), 'S'}, + {"volup", IMX_GPIO_NR(7, 13), 'V'}, + {"voldown", IMX_GPIO_NR(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + return 0; +} diff --git a/boards.cfg b/boards.cfg index 7a0b79d..fb3b197 100644 --- a/boards.cfg +++ b/boards.cfg @@ -255,6 +255,12 @@ mx6qsabreauto arm armv7 mx6qsabreauto freesca mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg eco5pk arm armv7 eco5pk 8dtech omap3 +nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 +nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 +nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 +nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 +nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 +nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,SDRAM_MB=1024 cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h new file mode 100644 index 0000000..05f6813 --- /dev/null +++ b/include/configs/nitrogen6x.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the Boundary Devices Nitrogen6X + * and Freescale i.MX6Q Sabre Lite boards. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 3769 + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* OCOTP Configs */ +#define CONFIG_CMD_IMXOTP +#ifdef CONFIG_CMD_IMXOTP +#define CONFIG_IMX_OTP +#define IMX_OTP_BASE OCOTP_BASE_ADDR +#define IMX_OTP_ADDR_MAX 0x7F +#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#define IMX_OTPWRITE_ENABLED +#endif + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#ifdef CONFIG_MX6Q +#define CONFIG_CMD_SATA +#endif + +/* + * SATA Configs + */ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* Miscellaneous commands */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +/* Framebuffer and LCD */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_CMD_HDMIDETECT +#define CONFIG_CONSOLE_MUX + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#ifdef CONFIG_CMD_SATA +#define CONFIG_DRIVE_SATA "sata " +#else +#define CONFIG_DRIVE_SATA +#endif + +#ifdef CONFIG_CMD_MMC +#define CONFIG_DRIVE_MMC "mmc " +#else +#define CONFIG_DRIVE_MMC +#endif + +#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc1\0" \ + "clearenv=if sf probe || sf probe || sf probe 1 ; then " \ + "sf erase 0xc0000 0x2000 && " \ + "echo restored environment to factory default ; fi\0" \ + "bootcmd=for dtype in " CONFIG_DRIVE_TYPES \ + "; do " \ + "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ + "for fs in fat ext2 ; do " \ + "${fs}load " \ + "${dtype} ${disk}:1 " \ + "10008000 " \ + "/6x_bootscript" \ + "&& source 10008000 ; " \ + "done ; " \ + "done ; " \ + "done; " \ + "setenv stdout serial,vga ; " \ + "echo ; echo 6x_bootscript not found ; " \ + "echo ; echo serial console at 115200, 8N1 ; echo ; " \ + "echo details at http://boundarydevices.com/6q_bootscript ; " \ + "setenv stdout serial\0" \ + "upgradeu=for dtype in " CONFIG_DRIVE_TYPES \ + "; do " \ + "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \ + "for fs in fat ext2 ; do " \ + "${fs}load ${dtype} ${disk}:1 10008000 " \ + "/6x_upgrade " \ + "&& source 10008000 ; " \ + "done ; " \ + "done ; " \ + "done\0" \ + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (CONFIG_DDR_MB * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +/* #define CONFIG_ENV_IS_IN_MMC */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_SYS_DCACHE_OFF + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#define CONFIG_CMD_BMP + +#define CONFIG_CMD_TIME +#define CONFIG_SYS_ALT_MEMTEST + +#endif /* __CONFIG_H */ -- 1.7.9.5

6 19

[U-Boot] [PATCH] mtd: nand: fix the written length when nand_write_skip_bad failed
by Tao Hou 11 Mar '13

11 Mar '13

When the data has been partially written into the NAND Flash, returning the written length instead of 0. The written length may be useful when the upper level decides to continue the writing after skipping the block causing the write failure. Signed-off-by: Tao Hou <hotforest(a)gmail.com> Cc: Scott Wood <scottwood(a)freescale.com> Cc: Ben Gardiner <bengardiner(a)nanometrics.ca> Cc: Lei Wen <leiwen(a)marvell.com> --- drivers/mtd/nand/nand_util.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index de1d13e..f57d723 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -496,8 +496,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, #ifdef CONFIG_CMD_NAND_YAFFS if (flags & WITH_YAFFS_OOB) { - if (flags & ~WITH_YAFFS_OOB) + if (flags & ~WITH_YAFFS_OOB) { + *length = 0; return -EINVAL; + } int pages; pages = nand->erasesize / nand->writesize; @@ -505,6 +507,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (*length % (nand->writesize + nand->oobsize)) { printf("Attempt to write incomplete page" " in yaffs mode\n"); + *length = 0; return -EINVAL; } } else @@ -542,7 +545,6 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (rval == 0) return 0; - *length = 0; printf("NAND write to offset %llx failed %d\n", offset, rval); return rval; @@ -550,7 +552,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, while (left_to_write > 0) { size_t block_offset = offset & (nand->erasesize - 1); - size_t write_size, truncated_write_size; + size_t write_size, truncated_write_size, written_size; WATCHDOG_RESET(); @@ -586,8 +588,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, ops.oobbuf = ops.datbuf + pagesize; rval = nand->write_oob(nand, offset, &ops); - if (rval != 0) + if (rval != 0) { + written_size = pagesize_oob * page; break; + } offset += pagesize; p_buffer += pagesize_oob; @@ -605,14 +609,18 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, rval = nand_write(nand, offset, &truncated_write_size, p_buffer); - offset += write_size; - p_buffer += write_size; + if (rval == 0) { + offset += write_size; + p_buffer += write_size; + } else { + written_size = truncated_write_size; + } } if (rval != 0) { printf("NAND write to offset %llx failed %d\n", offset, rval); - *length -= left_to_write; + *length -= left_to_write - written_size; return rval; } -- 1.7.9.5

3 7

[U-Boot] [PATCH v8 07/31] __HAVE_ARCH_GENERIC_BOARD controls availabilty of generic board
by Simon Glass 11 Mar '13

11 Mar '13

We are introducing a new unified board setup. Add a check to make sure that board config files do not define CONFIG_SYS_GENERIC_BOARD unless their architecture defines __HAVE_ARCH_GENERIC_BOARD __HAVE_ARCH_GENERIC_BOARD will currently not be the default setting, but we can switch this later when most architecture support generic board. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v8: - Switch polarity: !CONFIG_SYS_LEGACY_BOARD becomes __HAVE_ARCH_GENERIC_BOARD Changes in v7: - Add description of CONFIG_SYS_LEGACY_BOARD to README Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None README | 10 ++++++++++ config.mk | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/README b/README index 42544ce..2c36e00 100644 --- a/README +++ b/README @@ -3211,6 +3211,16 @@ Configuration Settings: If defined, don't allow the -f switch to env set override variable access flags. +- CONFIG_SYS_GENERIC_BOARD + This selects the architecture-generic board system instead of the + architecture-specific board files. It is intended to move boards + to this new framework over time. Defining this will disable the + arch/foo/lib/board.c file and use common/board_f.c and + common/board_r.c instead. To use this option your architecture + must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in + its config.mk file). If you find problems enabling this option on + your board please report the problem and send patches! + The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: diff --git a/config.mk b/config.mk index b7cd481..9886415 100644 --- a/config.mk +++ b/config.mk @@ -221,6 +221,14 @@ ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif +# Does this architecture support generic board init? +ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifneq ($(CONFIG_SYS_GENERIC_BOARD),) +$(error Your architecture does not support generic board. Please undefined \ +CONFIG_SYS_GENERIC_BOARD in your board config file) +endif +endif + ifneq ($(RESET_VECTOR_ADDRESS),) CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) endif -- 1.8.1.3

3 8

[U-Boot] [PULL REQUEST] MPC82xx
by Wolfgang Denk 11 Mar '13

11 Mar '13

Dear Tom, The following changes since commit fc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4: x86: Enable CONFIG_OF_CONTROL on coreboot (2013-03-04 15:57:52 -0800) are available in the git repository at: git://git.denx.de/u-boot-mpc82xx master for you to fetch changes up to 8327122b0d25a4be29292ff30293f1241bbcfb5b: powerpc/82xx/km: removed unneeded ifdef (2013-03-09 16:05:00 +0100) ---------------------------------------------------------------- Holger Brunck (2): powerpc/82xx/km: make handle_mgcoge3un_reset static powerpc/82xx/km: removed unneeded ifdef board/keymile/km82xx/km82xx.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de There are three things I always forget. Names, faces - the third I can't remember. - Italo Svevo

2 1

[U-Boot] [PULL REQUEST] MPC5xxx
by Wolfgang Denk 11 Mar '13

11 Mar '13

Dear Tom, I apologize for being inattentive for so long... The following changes since commit fc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4: x86: Enable CONFIG_OF_CONTROL on coreboot (2013-03-04 15:57:52 -0800) are available in the git repository at: git://git.denx.de/u-boot-mpc5xxx master for you to fetch changes up to 5a35831b1f427a91ae06c971c2b3b4d9843372a1: mpc512x: pdm360ng: drop not needed memory node fixup (2013-03-09 08:23:08 +0100) ---------------------------------------------------------------- Anatolij Gustschin (8): mpc512x: add common LAW and Chip Select configuration mpc512x: use common code for CSx configuration mpc512x: use common code for clock setting for all mpc512x boards mpc512x: optionally configure DIU, LPC and NFC deviders mpc512x: allow configuring board specific IPS divider mpc512x: add ifm ac14xx board mpc512x: Adjust the DRAM init sequence to the datasheet spec mpc512x: pdm360ng: drop not needed memory node fixup Stefan Roese (3): mpc5200: spl_boot.c: Change init oder to first enable printf mpc5200: Add a4m2k board port mpc5200: a4m2k: Implement custom "dynamic" watchdog support MAINTAINERS | 2 + arch/powerpc/cpu/mpc512x/cpu_init.c | 120 +++++++ arch/powerpc/cpu/mpc512x/fixed_sdram.c | 17 +- arch/powerpc/cpu/mpc512x/iopin.c | 54 +++ arch/powerpc/cpu/mpc5xxx/spl_boot.c | 20 +- arch/powerpc/include/asm/immap_512x.h | 22 ++ board/a3m071/README | 2 +- board/a3m071/a3m071.c | 147 +++++++- board/a3m071/is46r16320d.h | 35 ++ board/davedenx/aria/aria.c | 64 ---- board/esd/mecp5123/mecp5123.c | 54 --- board/freescale/mpc5121ads/mpc5121ads.c | 52 --- board/ifm/ac14xx/Makefile | 34 ++ board/ifm/ac14xx/ac14xx.c | 617 ++++++++++++++++++++++++++++++++ board/pdm360ng/pdm360ng.c | 58 --- boards.cfg | 2 + include/configs/a3m071.h | 118 +++--- include/configs/ac14xx.h | 591 ++++++++++++++++++++++++++++++ include/configs/aria.h | 23 +- include/configs/mecp5123.h | 24 ++ include/configs/mpc5121ads.h | 23 ++ include/configs/pdm360ng.h | 24 +- 22 files changed, 1810 insertions(+), 293 deletions(-) create mode 100644 board/a3m071/is46r16320d.h create mode 100644 board/ifm/ac14xx/Makefile create mode 100644 board/ifm/ac14xx/ac14xx.c create mode 100644 include/configs/ac14xx.h

2 1

[U-Boot] [PATCH] at91sam9x5: mmc: save environment as a file in FAT partition.
by Josh Wu 11 Mar '13

11 Mar '13

This patch will save U-Boot environment as a file: uboot.env, in FAT partition instead of saving it in raw sector of SD card. Since saving environment in raw sector has risk of corrupting the SD card and only can use very small size. Save as a FAT file has no above limitation. Signed-off-by: Josh Wu <josh.wu(a)atmel.com> --- this patch is based on v2013.01. include/configs/at91sam9x5ek.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6fac5ac..b01bb30 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -217,11 +217,13 @@ "bootm 0x22000000" #else /* CONFIG_SYS_USE_MMC */ /* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_IS_IN_MMC -/* For FAT system, most cases it should be in the reserved sector */ -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_FILE "uboot.env" +#define FAT_ENV_DEVICE 0 +#define FAT_ENV_PART 1 +#define CONFIG_ENV_SIZE 0x4000 #endif #ifdef CONFIG_SYS_USE_MMC -- 1.7.9.5

3 4

[U-Boot] [PATCH v2] mx6dl: Add initial support for Wandboard dual lite
by Fabio Estevam 10 Mar '13

10 Mar '13

From: Fabio Estevam <fabio.estevam(a)freescale.com> Add initial support for Wandboard dual lite. Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For details on the features of Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- This applies on top of Eric's series for adding nitrogen6x boards support. Changes since v1: - Use get_ram_size - Remove ARP_TIMEOUT - Remove unneeded "1u" MAINTAINERS | 1 + arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 3 + board/wandboard/Makefile | 29 ++++ board/wandboard/wandboard.c | 180 ++++++++++++++++++++++++ boards.cfg | 1 + include/configs/wandboard.h | 208 ++++++++++++++++++++++++++++ 6 files changed, 422 insertions(+) create mode 100644 board/wandboard/Makefile create mode 100644 board/wandboard/wandboard.c create mode 100644 include/configs/wandboard.h diff --git a/MAINTAINERS b/MAINTAINERS index 42e7664..9e1e169 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -659,6 +659,7 @@ Fabio Estevam <fabio.estevam(a)freescale.com> mx53smd i.MX53 mx6qsabresd i.MX6Q mx6qsabreauto i.MX6Q + wandboard i.MX6DL Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index 9494e41..9846f1b 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -50,6 +50,8 @@ #define NO_MUX_I 0 #define NO_PAD_I 0 enum { + MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0), MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), @@ -90,6 +92,7 @@ enum { MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0), MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0), MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0), MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0), MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0), diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile new file mode 100644 index 0000000..014ea6c --- /dev/null +++ b/board/wandboard/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := wandboard.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c new file mode 100644 index 0000000..e2839d8 --- /dev/null +++ b/board/wandboard/wandboard.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <mmc.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ETH_PHY_RESET IMX_GPIO_NR(3, 29) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8031 PHY Reset */ + MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* Reset AR8031 PHY */ + gpio_direction_output(ETH_PHY_RESET, 0); + udelay(500); + gpio_set_value(ETH_PHY_RESET, 1); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +static int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +u32 get_board_rev(void) +{ + return 0x61011; +} + +int checkboard(void) +{ + puts("Board: Wandboard\n"); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 7c3e5f5..3518609 100644 --- a/boards.cfg +++ b/boards.cfg @@ -259,6 +259,7 @@ nitrogen6q arm armv7 nitrogen6x boundar nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S +wandboard_dl arm armv7 wandboard - mx6 wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h new file mode 100644 index 0000000..2b156a3 --- /dev/null +++ b/include/configs/wandboard.h @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the Wandboard. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4412 + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6dl-wandboard.dtb\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ -- 1.7.9.5

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[U-Boot] [PATCH 0/2] Protect splashimage from improperly aligned addresses
by Nikita Kiryanov 10 Mar '13

10 Mar '13

As discussed in the links below, one needs to be careful about choosing an address for a splash image BMP file when working on architectures that can't handle unaligned memory accesses. A bad address may lead to a bricked board, and the safe addresses are not obvious due to the internal structure of BMP files. This patchset documents the problem and implements an optional callback that prevents the environment variable from being set to a bad value. Finally, it turns this protection on for cm_t35. http://lists.denx.de/pipermail/u-boot/2013-January/144666.html http://lists.denx.de/pipermail/u-boot/2013-February/146021.html Nikita Kiryanov (2): lcd: implement a callback for splashimage cm_t35: prevent splashimage from being set to a bad value README | 11 +++++++++++ common/lcd.c | 26 ++++++++++++++++++++++++++ doc/README.displaying-bmps | 27 +++++++++++++++++++++++++++ include/configs/cm_t35.h | 2 ++ include/env_callback.h | 7 +++++++ 5 files changed, 73 insertions(+) create mode 100644 doc/README.displaying-bmps -- 1.7.10.4

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[U-Boot] [PATCH V3 0/7] Add splash screen for CM-T35
by Nikita Kiryanov 10 Mar '13

10 Mar '13

This patchset adds splash screen support for CM-T35. It includes the ability to initialize the display subsystem either using predefines (selected via env variable "displaytype"), or user supplied configuration options, also stored in an environment variables and pointed to by displaytype. The splash image data is currently read from NAND. As a preparation for the above functionality this patchset adds: - new DSS #defines - an option for board-specific splash screen preparation, which can be invoked in lcd_logo() right before displaying the splash screen (typical use case: load the image data from non-memory mapped storage in time for it to be displayed). - struct panel_config is extended to support setting the gfx_format dynamically - protection from data aborts due to unaligned bmp headers is added to lcd_logo's splashscreen section (I'm also looking into refining this protection later on). Changes in V3: - No unnecessary #defines in arch-omap3/dss.h [Wolfgang Denk] - Reworded patch 2 comment [Wolfgang Denk] - Used a #define for cmap addr [Wolfgang Denk] Changes in V2: - DSS #defines are defined shiften where possible [Jeroen Hofstee] - GFXFORMAT_RGB16 now passed to omap3_dss_panel_config() in a new field of panel_cfg. Updated existing panel_config structs to set this field to the value that was originally hardcoded into omap3_dss_panel_config(). [Jeroen Hofstee] - Used LCD_BPP for vl_bpix. [Jeroen Hofstee] - Added a comment to explain the choice of GFXFORMAT_RGB16. [Jeroen Hofstee] - Added an address check (and fix) to the address of splashimage in order to avoid alignment problems with bmp header. A similar check appears in board_splash_screen_prepare() for cm_t35. [Albert ARIBAUD] - Do not manually set gfx burst size to GFXBURSTSIZE16, as it is apparently not necessary. GFXBURSTSIZE* #defines were kept in patch 1 anyway in the hope they will be useful for someone. Nikita Kiryanov (7): omap3: add useful dss defines omap3: allow dynamic selection of gfx_format lcd: prevent unaligned memory access when displaying splash screen lcd: add option for board specific splash screen preparation cm-t35: add support for dvi displays cm-t35: add support for user defined lcd parameters cm-t35: add support for loading splash image from NAND README | 8 + arch/arm/include/asm/arch-omap3/dss.h | 31 +++ board/cm_t35/Makefile | 1 + board/cm_t35/cm_t35.c | 68 ++++++ board/cm_t35/display.c | 428 +++++++++++++++++++++++++++++++++ board/htkw/mcx/mcx.c | 1 + board/teejet/mt_ventoux/mt_ventoux.c | 2 + board/ti/beagle/beagle.h | 6 +- common/lcd.c | 23 ++ drivers/video/omap3_dss.c | 2 +- include/configs/cm_t35.h | 11 + include/lcd.h | 1 + 12 files changed, 579 insertions(+), 3 deletions(-) create mode 100644 board/cm_t35/display.c -- 1.7.10.4

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