March 2013 - U-Boot

[U-Boot] [PATCH v6] Exynos5: Pinmux: Add fdt for pinmux
by Akshay Saraswat 12 Mar '13

12 Mar '13

This patch adds fdt nodes for peripherals which require pin muxing and configuration. Device tree bindings for pinctrl are kept same as required for Linux. Existing pinmux code modified to retrieve gpio range and function related info from fdt. Depends-on: [U-Boot] [PATCH 0/4 V3] EXYNOS5: Add GPIO numbering feature URL: http://lists.denx.de/pipermail/u-boot/2013-February/146151.html Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- Changes since v1: - Device tree bindings changed to linux style. - Added documentation for samsung pinctrl. Changes since v2: - Rebased as per new version of GPIO numbering patch-set. Changes since v3: - Added comments to reduce ambiguity and increase readability. - Fixed few other nits. Changes since v4: - Added support for reading peripheral pinctrl subnode names from preipheral's node instead of hard coding. Changes since v5: - Changed compatible strings for uart, mshc, i2s and pinctrl to make them similar to kernel in lib/fdtdec.c. - Changed "samsung,pinctrl-names" to "pinctrl-names" in exynos5250.dtsi to make it same as kernel. - Added explanation for "pinctrl-names" in bindings documentation samsung-pinctrl.txt. arch/arm/cpu/armv7/exynos/pinmux.c | 357 +++++++------- arch/arm/dts/exynos5250-pinctrl.dtsi | 675 +++++++++++++++++++++++++++ arch/arm/dts/exynos5250.dtsi | 88 ++++ board/samsung/dts/exynos5250-smdk5250.dts | 11 + doc/device-tree-bindings/samsung-pinctrl.txt | 258 ++++++++++ include/fdtdec.h | 4 + lib/fdtdec.c | 4 + 7 files changed, 1232 insertions(+), 165 deletions(-) create mode 100644 arch/arm/dts/exynos5250-pinctrl.dtsi create mode 100644 doc/device-tree-bindings/samsung-pinctrl.txt diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index a01ce0c..d590fc9 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -23,10 +23,20 @@ #include <common.h> #include <fdtdec.h> +#include <linux/ctype.h> #include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> +DECLARE_GLOBAL_DATA_PTR; + +/* Struct for temporarily storing pin related info */ +struct pin_group { + uint8_t function; /* Pin function */ + uint8_t pull_mode; /* Pin pull mode */ + uint8_t drive_strength; /* Pin drive strength */ +}; + struct gpio_name_num_table exynos5_gpio_table[] = { { 'a', GPIO_A00 }, { 'b', GPIO_B00 }, @@ -42,252 +52,271 @@ struct gpio_name_num_table exynos5_gpio_table[] = { { 'z', GPIO_Z0 }, }; -static void exynos5_uart_config(int peripheral) +/* Extract and set pins in a particular pinctrl node */ +static void pinmux_set_pins(const char *fprop_data, + struct pin_group *pingrp) { - int i, start, count; + int i; + char gpio[5]; + + /* + * Get all the pin names from fdt and fill the gpio array + * with corresponding enum values(Pin numbers). + */ + for (i = 0; !(fprop_data[i] == (int)NULL && + fprop_data[i+1] == (int)NULL); i += 7) { + int pin_num = -1; + + /* + * Modify pin name retrieved from fdt, + * so that name_to_gpio may understand. + */ + gpio[0] = fprop_data[i]; + gpio[1] = fprop_data[i + 1]; + gpio[2] = fprop_data[i + 2]; + gpio[3] = fprop_data[i + 3]; + gpio[4] = fprop_data[i + 5]; + + pin_num = name_to_gpio(gpio); + + /* + * If pin number is valid, add it to the pin array + * and increment pin count. + */ + if (pin_num >= 0) { + gpio_cfg_pin(pin_num, + S5P_GPIO_FUNC(pingrp->function)); + gpio_set_pull(pin_num, pingrp->pull_mode); + gpio_set_drv(pin_num, pingrp->drive_strength); + } + } +} + +/* Extract all the config info from pinctrl periph subnodei */ +static int pinmux_do_config(struct pin_group *pingrp, const char * dev_name) +{ + int node, subnode; + const char *fprop_data; + + /* Loop for all pinctrl nodes in fdt */ + for (node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_PINCTRL); node >= 0; + node = fdtdec_next_compatible(gd->fdt_blob, node, + COMPAT_SAMSUNG_PINCTRL)) { + /* Get the subnode from FDT for this peripheral*/ + subnode = fdt_subnode_offset(gd->fdt_blob, + node, dev_name); + if (subnode < 0) + continue; + + /* Get names of pins to be configured from fdt */ + fprop_data = fdt_getprop(gd->fdt_blob, + subnode, "samsung,pins", NULL); + + /* Get the pin function from fdt */ + pingrp->function = fdtdec_get_int(gd->fdt_blob, + subnode, "samsung,pin-function", 0); + + /* Get the pull mode for pins from fdt */ + pingrp->pull_mode = fdtdec_get_int(gd->fdt_blob, + subnode, "samsung,pin-pud", 0); + + /* Get the drive strength for pins from fdt */ + pingrp->drive_strength = fdtdec_get_int(gd->fdt_blob, + subnode, "samsung,pin-drv", 0); + + /* Convert pin names to pin numbers */ + pinmux_set_pins(fprop_data, pingrp); + + return 0; + } + + return -1; +} + +/* Set configuration for all pins as per fdt for a peripheral */ +static int pinmux_group_set(struct pin_group *pingrp, int pnode) +{ + int err, i = 0; + const char *fprop_data; + const char *dev_name; + + fprop_data = fdt_getprop(gd->fdt_blob, pnode, + "pinctrl-names", NULL); + + do { + dev_name = (fprop_data + i); + err = pinmux_do_config(pingrp, dev_name); + if (err) + break; + while (fprop_data[i] != (int)NULL) + i++; + } while (isalnum(fprop_data[++i])); + + return err; +} + +static int exynos5_uart_config(int peripheral) +{ + int suffix, pnode; + struct pin_group pingrp; switch (peripheral) { case PERIPH_ID_UART0: - start = GPIO_A00; - count = 4; + suffix = 0; break; case PERIPH_ID_UART1: - start = GPIO_D00; - count = 4; + suffix = 1; break; case PERIPH_ID_UART2: - start = GPIO_A10; - count = 4; + suffix = 2; break; case PERIPH_ID_UART3: - start = GPIO_A14; - count = 2; + suffix = 3; break; } - for (i = start; i < start + count; i++) { - gpio_set_pull(i, S5P_GPIO_PULL_NONE); - gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); - } + + pnode = fdtdec_next_alias(gd->fdt_blob, "uart", + COMPAT_SAMSUNG_EXYNOS_UART, &suffix); + + return pinmux_group_set(&pingrp, pnode); } -static int exynos5_mmc_config(int peripheral, int flags) +static int exynos5_mmc_config(int peripheral) { - int i, start, start_ext, gpio_func = 0; + int suffix, pnode; + struct pin_group pingrp; switch (peripheral) { case PERIPH_ID_SDMMC0: - start = GPIO_C00; - start_ext = GPIO_C10; - gpio_func = S5P_GPIO_FUNC(0x2); + suffix = 0; break; case PERIPH_ID_SDMMC1: - start = GPIO_C20; - start_ext = 0; + suffix = 1; break; case PERIPH_ID_SDMMC2: - start = GPIO_C30; - start_ext = GPIO_C43; - gpio_func = S5P_GPIO_FUNC(0x3); + suffix = 2; break; case PERIPH_ID_SDMMC3: - start = GPIO_C40; - start_ext = 0; + suffix = 3; break; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", - peripheral); - return -1; - } - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start_ext; i <= (start_ext + 3); i++) { - gpio_cfg_pin(i, gpio_func); - gpio_set_pull(i, S5P_GPIO_PULL_UP); - gpio_set_drv(i, S5P_GPIO_DRV_4X); - } - } - for (i = 0; i < 2; i++) { - gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(start + i, S5P_GPIO_PULL_NONE); - gpio_set_drv(start + i, S5P_GPIO_DRV_4X); - } - for (i = 3; i <= 6; i++) { - gpio_cfg_pin(start + i, S5P_GPIO_FUNC(0x2)); - gpio_set_pull(start + i, S5P_GPIO_PULL_UP); - gpio_set_drv(start + i, S5P_GPIO_DRV_4X); - } - return 0; + pnode = fdtdec_next_alias(gd->fdt_blob, "mshc", + COMPAT_SAMSUNG_EXYNOS_MSHC, &suffix); + + return pinmux_group_set(&pingrp, pnode); } -static void exynos5_sromc_config(int flags) +static int exynos5_sromc_config(void) { - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - gpio_cfg_pin(GPIO_Y00 + (flags & PINMUX_FLAG_BANK), - S5P_GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y04, S5P_GPIO_FUNC(2)); - gpio_cfg_pin(GPIO_Y05, S5P_GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - gpio_cfg_pin(GPIO_Y10 + i, S5P_GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - gpio_cfg_pin(GPIO_Y30 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y30 + i, S5P_GPIO_PULL_UP); + int pnode; + static struct pin_group pingrp; - gpio_cfg_pin(GPIO_Y50 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y50 + i, S5P_GPIO_PULL_UP); + pnode = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_EXYNOS5_SROMC); - gpio_cfg_pin(GPIO_Y60 + i, S5P_GPIO_FUNC(2)); - gpio_set_pull(GPIO_Y60 + i, S5P_GPIO_PULL_UP); - } + return pinmux_group_set(&pingrp, pnode); } -static void exynos5_i2c_config(int peripheral, int flags) +static int exynos5_i2c_config(int peripheral) { + int suffix, pnode; + struct pin_group pingrp; switch (peripheral) { case PERIPH_ID_I2C0: - gpio_cfg_pin(GPIO_B30, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B31, S5P_GPIO_FUNC(0x2)); + suffix = 0; break; case PERIPH_ID_I2C1: - gpio_cfg_pin(GPIO_B32, S5P_GPIO_FUNC(0x2)); - gpio_cfg_pin(GPIO_B33, S5P_GPIO_FUNC(0x2)); + suffix = 1; break; case PERIPH_ID_I2C2: - gpio_cfg_pin(GPIO_A06, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A07, S5P_GPIO_FUNC(0x3)); + suffix = 2; break; case PERIPH_ID_I2C3: - gpio_cfg_pin(GPIO_A12, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A13, S5P_GPIO_FUNC(0x3)); + suffix = 3; break; case PERIPH_ID_I2C4: - gpio_cfg_pin(GPIO_A20, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A21, S5P_GPIO_FUNC(0x3)); + suffix = 4; break; case PERIPH_ID_I2C5: - gpio_cfg_pin(GPIO_A22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_A23, S5P_GPIO_FUNC(0x3)); + suffix = 5; break; case PERIPH_ID_I2C6: - gpio_cfg_pin(GPIO_B13, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_B14, S5P_GPIO_FUNC(0x4)); + suffix = 6; break; case PERIPH_ID_I2C7: - gpio_cfg_pin(GPIO_B22, S5P_GPIO_FUNC(0x3)); - gpio_cfg_pin(GPIO_B23, S5P_GPIO_FUNC(0x3)); + suffix = 7; break; } + + pnode = fdtdec_next_alias(gd->fdt_blob, "i2c", + COMPAT_SAMSUNG_S3C2440_I2C, &suffix); + + return pinmux_group_set(&pingrp, pnode); } -static void exynos5_i2s_config(int peripheral) +static int exynos5_i2s_config(int peripheral) { - int i; + int suffix, pnode; + struct pin_group pingrp; + + if (peripheral == PERIPH_ID_I2S1) { + suffix = 1; + pnode = fdtdec_next_alias(gd->fdt_blob, "i2s", + COMPAT_SAMSUNG_EXYNOS_I2S, &suffix); + } - for (i = 0; i < 5; i++) - gpio_cfg_pin(GPIO_B00+i, S5P_GPIO_FUNC(0x02)); + return pinmux_group_set(&pingrp, pnode); } -void exynos5_spi_config(int peripheral) +int exynos5_spi_config(int peripheral) { - int cfg = 0, pin = 0, i; + int suffix, pnode; + static struct pin_group pingrp; switch (peripheral) { case PERIPH_ID_SPI0: - cfg = S5P_GPIO_FUNC(0x2); - pin = GPIO_A20; + suffix = 0; break; case PERIPH_ID_SPI1: - cfg = S5P_GPIO_FUNC(0x2); - pin = GPIO_A24; + suffix = 1; break; case PERIPH_ID_SPI2: - cfg = S5P_GPIO_FUNC(0x5); - pin = GPIO_B11; + suffix = 2; break; case PERIPH_ID_SPI3: - cfg = S5P_GPIO_FUNC(0x2); - pin = GPIO_F10; + suffix = 3; break; case PERIPH_ID_SPI4: - for (i = 0; i < 2; i++) { - gpio_cfg_pin(GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); - gpio_cfg_pin(GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); - } + suffix = 4; break; } - if (peripheral != PERIPH_ID_SPI4) { - for (i = pin; i < pin + 4; i++) - gpio_cfg_pin(i, cfg); - } + + pnode = fdtdec_next_alias(gd->fdt_blob, "spi", + COMPAT_SAMSUNG_EXYNOS_SPI, &suffix); + + return pinmux_group_set(&pingrp, pnode); } -static int exynos5_pinmux_config(int peripheral, int flags) +static int exynos5_pinmux_config(int peripheral) { switch (peripheral) { case PERIPH_ID_UART0: case PERIPH_ID_UART1: case PERIPH_ID_UART2: case PERIPH_ID_UART3: - exynos5_uart_config(peripheral); + return exynos5_uart_config(peripheral); break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: - return exynos5_mmc_config(peripheral, flags); + return exynos5_mmc_config(peripheral); + break; case PERIPH_ID_SROMC: - exynos5_sromc_config(flags); + return exynos5_sromc_config(); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -297,24 +326,22 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C5: case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: - exynos5_i2c_config(peripheral, flags); + return exynos5_i2c_config(peripheral); break; case PERIPH_ID_I2S1: - exynos5_i2s_config(peripheral); + return exynos5_i2s_config(peripheral); break; case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: case PERIPH_ID_SPI2: case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: - exynos5_spi_config(peripheral); + return exynos5_spi_config(peripheral); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - - return 0; } static void exynos4_i2c_config(int peripheral, int flags) @@ -427,7 +454,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) - return exynos5_pinmux_config(peripheral, flags); + return exynos5_pinmux_config(peripheral); else if (cpu_is_exynos4()) return exynos4_pinmux_config(peripheral, flags); else { @@ -495,6 +522,6 @@ int name_to_gpio(const char *name) if (i == ARRAY_SIZE(exynos5_gpio_table)) return -1; - + return num; } diff --git a/arch/arm/dts/exynos5250-pinctrl.dtsi b/arch/arm/dts/exynos5250-pinctrl.dtsi new file mode 100644 index 0000000..657fdb0 --- /dev/null +++ b/arch/arm/dts/exynos5250-pinctrl.dtsi @@ -0,0 +1,675 @@ +/* + * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + * + * Note: This file does not include pin-ctrl subnodes for all the controllers in + * Exynos5250 SoC. It can be updated as per need in future. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x11400000 0x1000>; + interrupts = <0 46 0>; + + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb3: gpb3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc3: gpc3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy1: gpy1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy2: gpy2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy3: gpy3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy4: gpy4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy5: gpy5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpy6: gpy6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpd0-0", "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samaung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpc0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpc2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpc2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpc2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpc2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpc3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpc3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpc3-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpc3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus8: sd2-bus-width8 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_clk: sd3-clk { + samsung,pins = "gpc4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cmd: sd3-cmd { + samsung,pins = "gpc4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd3_cd: sd3-cd { + samsung,pins = "gpc4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus1: sd3-bus-width1 { + samsung,pins = "gpc4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd3_bus4: sd3-bus-width4 { + samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + srom_cs1: srom-cs1 { + samsung,pins = "gpy0-1", "gpy0-4", "gpy0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + srom_ebi: srom-ebi-enable { + samsung,pins = "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + srom_ebi_a: srom-ebi-addr-lines { + samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", + "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + srom_ebi_d: srom-ebi-data-lines { + samsung,pins = "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", + "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", + "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", + "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s: i2s { + samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", + "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpa2-4", "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpb3-0", "gpb3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpb3-2", "gpb3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpa2-0", "gpa2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samaung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpb1-3", "gpb1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpb2-2", "gpb2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl_1: pinctrl@13400000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x13400000 0x1000>; + interrupts = <0 45 0>; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi3_bus: spi3-bus { + samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi4_bus: spi4-bus { + samsung,pins = "gpf0-2", "gpf0-3", "gpe0-4", "gpe0-5"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + pinctrl_2: pinctrl@10d10000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x10d10000 0x1000>; + interrupts = <0 45 0>; + + gpv0: gpv0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv1: gpv1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv2: gpv2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv3: gpv3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpv4: gpv4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pinctrl_3: pinctrl@03680000 { + compatible = "samsung,pinctrl-exynos5250"; + reg = <0x03680000 0x1000>; + interrupts = <0 45 0>; + + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index ed8c8dd..bbf56c6 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -18,6 +18,7 @@ */ /include/ "skeleton.dtsi" +/include/ "exynos5250-pinctrl.dtsi" / { compatible = "samsung,exynos5250"; @@ -27,6 +28,9 @@ reg = <0x12250000 0x20>; #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "srom-cs1", "srom-ebi-enable", + "srom-ebi-addr-lines", + "srom-ebi-data-lines"; }; i2c@12c60000 { @@ -35,6 +39,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; interrupts = <0 56 0>; + pinctrl-names = "i2c0-bus"; }; i2c@12c70000 { @@ -43,6 +48,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12C70000 0x100>; interrupts = <0 57 0>; + pinctrl-names = "i2c1-bus"; }; i2c@12c80000 { @@ -51,6 +57,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12C80000 0x100>; interrupts = <0 58 0>; + pinctrl-names = "i2c2-bus"; }; i2c@12c90000 { @@ -59,6 +66,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12C90000 0x100>; interrupts = <0 59 0>; + pinctrl-names = "i2c3-bus"; }; i2c@12ca0000 { @@ -67,6 +75,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12CA0000 0x100>; interrupts = <0 60 0>; + pinctrl-names = "i2c4-bus"; }; i2c@12cb0000 { @@ -75,6 +84,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12CB0000 0x100>; interrupts = <0 61 0>; + pinctrl-names = "i2c5-bus"; }; i2c@12cc0000 { @@ -83,6 +93,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12CC0000 0x100>; interrupts = <0 62 0>; + pinctrl-names = "i2c6-bus"; }; i2c@12cd0000 { @@ -91,6 +102,7 @@ compatible = "samsung,s3c2440-i2c"; reg = <0x12CD0000 0x100>; interrupts = <0 63 0>; + pinctrl-names = "i2c7-bus"; }; sound@12d60000 { @@ -104,6 +116,7 @@ compatible = "samsung,exynos-spi"; reg = <0x12d20000 0x30>; interrupts = <0 68 0>; + pinctrl-names = "spi0-bus"; }; spi@12d30000 { @@ -112,6 +125,7 @@ compatible = "samsung,exynos-spi"; reg = <0x12d30000 0x30>; interrupts = <0 69 0>; + pinctrl-names = "spi1-bus"; }; spi@12d40000 { @@ -121,6 +135,7 @@ reg = <0x12d40000 0x30>; clock-frequency = <50000000>; interrupts = <0 70 0>; + pinctrl-names = "spi2-bus"; }; spi@131a0000 { @@ -129,6 +144,7 @@ compatible = "samsung,exynos-spi"; reg = <0x131a0000 0x30>; interrupts = <0 129 0>; + pinctrl-names = "spi3-bus"; }; spi@131b0000 { @@ -137,6 +153,7 @@ compatible = "samsung,exynos-spi"; reg = <0x131b0000 0x30>; interrupts = <0 130 0>; + pinctrl-names = "spi4-bus"; }; ehci@12110000 { @@ -151,4 +168,75 @@ }; }; + serial@12C00000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C00000 0x100>; + pinctrl-names = "uart0-data", "uart0-fctl"; + }; + + serial@12C10000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C10000 0x100>; + pinctrl-names = "uart1-data", "uart1-fctl"; + }; + + serial@12C20000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C20000 0x100>; + pinctrl-names = "uart2-data", "uart2-fctl"; + }; + + serial@12C30000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x12C30000 0x100>; + pinctrl-names = "uart3-data"; + }; + + dwmmc@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12200000 0x1000>; + pinctrl-names = "sd0-clk", "sd0-cmd", + "sd0-bus-width4", + "sd0-bus-width8"; + }; + + dwmmc@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12210000 0x1000>; + pinctrl-names = "sd1-clk", "sd1-cmd", + "sd1-bus-width4"; + }; + + dwmmc@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12220000 0x1000>; + pinctrl-names = "sd2-clk", "sd2-cmd", + "sd2-bus-width4", + "sd2-bus-width8"; + }; + + dwmmc@12230000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12230000 0x1000>; + pinctrl-names = "sd3-clk", "sd3-cmd", + "sd3-bus-width4"; + }; + + i2s@03830000 { + compatible = "samsung,exynos5250-i2s"; + reg = <0x03830000 0x100>; + pinctrl-names = "i2s0"; + }; + + i2s@12d60000 { + compatible = "samsung,exynos5250-i2s"; + reg = <0x12d60000 0x100>; + pinctrl-names = "i2s1"; + }; + + i2s@12D70000 { + compatible = "samsung,exynos5250-i2s"; + reg = <0x12D70000 0x100>; + pinctrl-names = "i2s2"; + }; }; diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index cbfab6f..30ba5aa 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -30,6 +30,17 @@ spi2 = "/spi@12d40000"; spi3 = "/spi@131a0000"; spi4 = "/spi@131b0000"; + mshc0 = "/dwmmc@12200000"; + mshc1 = "/dwmmc@12210000"; + mshc2 = "/dwmmc@12220000"; + mshc3 = "/dwmmc@12230000"; + uart0 = "/serial@12C00000"; + uart1 = "/serial@12C10000"; + uart2 = "/serial@12C20000"; + uart3 = "/serial@12C30000"; + i2s0 = "/i2s@03830000"; + i2s1 = "/sound@12d60000"; + i2s2 = "/i2s@12D70000"; }; sromc@12250000 { diff --git a/doc/device-tree-bindings/samsung-pinctrl.txt b/doc/device-tree-bindings/samsung-pinctrl.txt new file mode 100644 index 0000000..f2364a1 --- /dev/null +++ b/doc/device-tree-bindings/samsung-pinctrl.txt @@ -0,0 +1,258 @@ +Samsung GPIO and Pin Mux/Config controller + +Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pads/pins +and also provides ability to multiplex and configure the output of various +on-chip controllers onto these pads. + +Required Properties: +- compatible: should be one of the following. + - "samsung,pinctrl": for Exynos compatible pin-controller. + +- reg: Base address of the pin controller hardware module and length of + the address space it occupies. + +- Pin banks as child nodes: Pin banks of the controller are represented by child + nodes of the controller node. Bank name is taken from name of the node. Each + bank node must contain following properties: + + - gpio-controller: identifies the node as a gpio controller and pin bank. + - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See generic + GPIO binding documentation for description of particular cells. + +- Pin mux/config groups as child nodes: The pin mux (selecting pin function + mode) and pin config (pull up/down, driver strength) settings are represented + as child nodes of the pin-controller node. There should be atleast one + child node and there is no limit on the count of these child nodes. + + The child node should contain a list of pin(s) on which a particular pin + function selection or pin configuration (or both) have to applied. This + list of pins is specified using the property name "samsung,pins". There + should be atleast one pin specfied for this property and there is no upper + limit on the count of pins that can be specified. The pins are specified + using pin names which are derived from the hardware manual of the SoC. As + an example, the pins in GPA0 bank of the pin controller can be represented + as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. + The format of the pin names should be (as per the hardware manual) + "[pin bank name]-[pin number within the bank]". + + The pin function selection that should be applied on the pins listed in the + child node is specified using the "samsung,pin-function" property. The value + of this property that should be applied to each of the pins listed in the + "samsung,pins" property should be picked from the hardware manual of the SoC + for the specified pin group. This property is optional in the child node if + no specific function selection is desired for the pins listed in the child + node. The value of this property is used as-is to program the pin-controller + function selector register of the pin-bank. + + The child node can also optionally specify one or more of the pin + configuration that should be applied on all the pins listed in the + "samsung,pins" property of the child node. The following pin configuration + properties are supported. + + - samsung,pin-pud: Pull up/down configuration. + - samsung,pin-drv: Drive strength configuration. + - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. + - samsung,pin-drv-pdn: Drive strength configuration in power down mode. + + The values specified by these config properties should be derived from the + hardware manual and these values are programmed as-is into the pin + pull up/down and driver strength register of the pin-controller. + + Note: A child should include atleast a pin function selection property or + pin configuration property (one or more) or both. + + The client nodes that require a particular pin function selection and/or + pin configuration should use the bindings listed in the "pinctrl-bindings.txt" + file. + +External GPIO and Wakeup Interrupts: + +The controller supports two types of external interrupts over gpio. The first +is the external gpio interrupt and second is the external wakeup interrupts. +The difference between the two is that the external wakeup interrupts can be +used as system wakeup events. + +A. External GPIO Interrupts: For supporting external gpio interrupts, the + following properties should be specified in the pin-controller device node. + + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - interrupts: interrupt specifier for the controller. The format and value of + the interrupt specifier depends on the interrupt parent for the controller. + + In addition, following properties must be present in node of every bank + of pins supporting GPIO interrupts: + + - interrupt-controller: identifies the controller node as interrupt-parent. + - #interrupt-cells: the value of this property should be 2. + - First Cell: represents the external gpio interrupt number local to the + external gpio interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered + +B. External Wakeup Interrupts: For supporting external wakeup interrupts, a + child node representing the external wakeup interrupt controller should be + included in the pin-controller device node. This child node should include + the following properties. + + - compatible: identifies the type of the external wakeup interrupt controller + The possible values are: + - samsung,wakeup-eint: represents wakeup interrupt controller + found on Samsung Exynos SoC. + - interrupt-parent: phandle of the interrupt parent to which the external + wakeup interrupts are forwarded to. + - interrupts: interrupt used by multiplexed wakeup interrupts. + + In addition, following properties must be present in node of every bank + of pins supporting wake-up interrupts: + + - interrupt-controller: identifies the node as interrupt-parent. + - #interrupt-cells: the value of this property should be 2 + - First Cell: represents the external wakeup interrupt number local to + the external wakeup interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered + + Node of every bank of pins supporting direct wake-up interrupts (without + multiplexing) must contain following properties: + + - interrupt-parent: phandle of the interrupt parent to which the external + wakeup interrupts are forwarded to. + - interrupts: interrupts of the interrupt parent which are used for external + wakeup interrupts from pins of the bank, must contain interrupts for all + pins of the bank. + +Aliases: + +All the pin controller nodes should be represented in the aliases node using +the following format 'pinctrl{n}' where n is a unique number for the alias. + +Example: A pin-controller node with pin banks: + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + + /* ... */ + + /* Pin bank without external interrupts */ + gpy0: gpy0 { + gpio-controller; + #gpio-cells = <2>; + }; + + /* ... */ + + /* Pin bank with external GPIO or muxed wake-up interrupts */ + gpj0: gpj0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ... */ + + /* Pin bank with external direct wake-up interrupts */ + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, + <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; + #interrupt-cells = <2>; + }; + + /* ... */ + }; + +Example 1: A pin-controller node with pin groups. + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 47 0>; + + /* ... */ + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + +Example 2: A pin-controller node with external wakeup interrupt controller node. + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 46 0> + + /* ... */ + + wakeup-interrupt-controller { + compatible = "samsung,wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 32 0>; + }; + }; + +Example 3: A uart client node that supports 'default' and 'flow-control' states. + Pinctrl Properties: + - pinctrl-names: names of all the pin-controller peripheral + sub-nodes which provide pinmux and pinconfig info. + - pinctrl{n}: This shows parent pin-controller nodes consisting + peripheral pin-controller subnodes. + + uart@13800000 { + compatible = "samsung,uart"; + reg = <0x13800000 0x100>; + interrupts = <0 52 0>; + pinctrl-names = "default", "flow-control; + pinctrl-0 = <&uart0_data>; + pinctrl-1 = <&uart0_data &uart0_fctl>; + }; diff --git a/include/fdtdec.h b/include/fdtdec.h index 77f244f..3e5cb8a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -81,6 +81,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ + COMPAT_SAMSUNG_EXYNOS_UART, /* Exynos serial */ + COMPAT_SAMSUNG_EXYNOS_MSHC, /* Exynos MMC controller */ + COMPAT_SAMSUNG_EXYNOS_I2S, /* Exynos I2S controller */ + COMPAT_SAMSUNG_PINCTRL, /* Exynos PINCTRL */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 3ae348d..5486996 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -56,6 +56,10 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), + COMPAT(SAMSUNG_EXYNOS_UART, "samsung,exynos4210-uart"), + COMPAT(SAMSUNG_EXYNOS_MSHC, "samsung,exynos5250-dw-mshc"), + COMPAT(SAMSUNG_EXYNOS_I2S, "samsung,exynos5250-i2s"), + COMPAT(SAMSUNG_PINCTRL, "samsung,pinctrl-exynos5250"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- 1.8.0

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[U-Boot] [PATCH 0/4] Tegra114: MMC: Add MMC driver for T114/Dalmore
by Tom Warren 12 Mar '13

12 Mar '13

This patchset adds SDMMC device-tree support to the Tegra114 dts files, and enables the Tegra MMC driver on Tegra114 Dalmore. Tested on my Dalmore E1611 board, eMMC and SD-Card work fine, can load a kernel off of a SD card OK, card detect works, and the env is now stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20/30). Tom Warren (4): Tegra114: fdt: Add SDMMC (sdhci) nodes for T114 boards (Dalmore for now) Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table Tegra114: MMC: Add SD bus power-rail init routine Tegra114: MMC: Enable DT MMC driver support for Tegra114 Dalmore boards arch/arm/dts/tegra114.dtsi | 32 +++++++++ arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 7 ++ board/nvidia/dalmore/dalmore.c | 79 +++++++++++++++++++++++ board/nvidia/dalmore/pinmux-config-dalmore.h | 2 + board/nvidia/dts/tegra114-dalmore.dts | 13 ++++ include/configs/dalmore.h | 12 +++- 6 files changed, 144 insertions(+), 1 deletions(-)

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[U-Boot] [PATCH] Tegra114: Dalmore: Add pad config tables/code based on pinmux code
by Tom Warren 12 Mar '13

12 Mar '13

Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/cpu/tegra114-common/pinmux.c | 188 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra114/pinmux.h | 75 ++++++++++- board/nvidia/dalmore/pinmux-config-dalmore.h | 16 +++ 3 files changed, 274 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c index 27b5f69..f037320 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/cpu/tegra114-common/pinmux.c @@ -39,6 +39,19 @@ struct tegra_pingroup_desc { #define PMUX_IO_RESET_SHIFT 8 #define PMUX_RCV_SEL_SHIFT 9 +#define PGRP_HSM_SHIFT 2 +#define PGRP_SCHMT_SHIFT 3 +#define PGRP_LPMD_SHIFT 4 +#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT) +#define PGRP_DRVDN_SHIFT 12 +#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT) +#define PGRP_DRVUP_SHIFT 20 +#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT) +#define PGRP_SLWR_SHIFT 28 +#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT) +#define PGRP_SLWF_SHIFT 30 +#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT) + /* Convenient macro for defining pin group properties */ #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \ { \ @@ -544,3 +557,178 @@ void pinmux_config_table(struct pingroup_config *config, int len) for (i = 0; i < len; i++) pinmux_config_pingroup(&config[i]); } + +static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, + int slwf) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwf = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwf */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwf)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwf == PGRP_SLWF_NONE) + return 0; + + reg = readl(pad_slwf); + reg &= ~PGRP_SLWF_MASK; + reg |= (slwf << PGRP_SLWF_SHIFT); + writel(reg, pad_slwf); + + return 0; +} + +static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_slwr = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and slwr */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_slw_isvalid(slwr)); + + /* NONE means unspecified/do not change/use POR value */ + if (slwr == PGRP_SLWR_NONE) + return 0; + + reg = readl(pad_slwr); + reg &= ~PGRP_SLWR_MASK; + reg |= (slwr << PGRP_SLWR_SHIFT); + writel(reg, pad_slwr); + + return 0; +} + +static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvup = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvup */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvup)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvup == PGRP_DRVUP_NONE) + return 0; + + reg = readl(pad_drvup); + reg &= ~PGRP_DRVUP_MASK; + reg |= (drvup << PGRP_DRVUP_SHIFT); + writel(reg, pad_drvup); + + return 0; +} + +static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_drvdn = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check on pad and drvdn */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_drv_isvalid(drvdn)); + + /* NONE means unspecified/do not change/use POR value */ + if (drvdn == PGRP_DRVDN_NONE) + return 0; + + reg = readl(pad_drvdn); + reg &= ~PGRP_DRVDN_MASK; + reg |= (drvdn << PGRP_DRVDN_SHIFT); + writel(reg, pad_drvdn); + + return 0; +} + +static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_lpmd = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad and lpmd value */ + assert(pmux_padgrp_isvalid(pad)); + assert(pmux_pad_lpmd_isvalid(lpmd)); + + /* NONE means unspecified/do not change/use POR value */ + if (lpmd == PGRP_LPMD_NONE) + return 0; + + reg = readl(pad_lpmd); + reg &= ~PGRP_LPMD_MASK; + reg |= (lpmd << PGRP_LPMD_SHIFT); + writel(reg, pad_lpmd); + + return 0; +} + +static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_schmt = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + reg = readl(pad_schmt); + reg &= ~(1 << PGRP_SCHMT_SHIFT); + if (schmt == PGRP_SCHMT_ENABLE) + reg |= (0x1 << PGRP_SCHMT_SHIFT); + writel(reg, pad_schmt); + + return 0; +} +static int padgrp_set_hsm(enum pdrive_pingrp pad, + enum pgrp_hsm hsm) +{ + struct pmux_tri_ctlr *pmt = + (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + u32 *pad_hsm = &pmt->pmt_drive[pad]; + u32 reg; + + /* Error check pad */ + assert(pmux_padgrp_isvalid(pad)); + + reg = readl(pad_hsm); + reg &= ~(1 << PGRP_HSM_SHIFT); + if (hsm == PGRP_HSM_ENABLE) + reg |= (0x1 << PGRP_HSM_SHIFT); + writel(reg, pad_hsm); + + return 0; +} + +void padctrl_config_pingroup(struct padctrl_config *config) +{ + enum pdrive_pingrp pad = config->padgrp; + + padgrp_set_drvup_slwf(pad, config->slwf); + padgrp_set_drvdn_slwr(pad, config->slwr); + padgrp_set_drvup(pad, config->drvup); + padgrp_set_drvdn(pad, config->drvdn); + padgrp_set_lpmd(pad, config->lpmd); + padgrp_set_schmt(pad, config->schmt); + padgrp_set_hsm(pad, config->hsm); +} + +void padgrp_config_table(struct padctrl_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + padctrl_config_pingroup(&config[i]); +} diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 53905cb..6025f90 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -470,10 +470,67 @@ enum pmux_vddio { PMUX_VDDIO_NONE }; -/* T114 pin drive group and pin mux registers */ -#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) -#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ - PDRIVE_PINGROUP_COUNT) +#define PGRP_SLWF_NONE -1 +#define PGRP_SLWF_MAX 3 +#define PGRP_SLWR_NONE PGRP_SLWF_NONE +#define PGRP_SLWR_MAX PGRP_SLWF_MAX + +#define PGRP_DRVUP_NONE -1 +#define PGRP_DRVUP_MAX 127 +#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE +#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX + +/* return 1 if a padgrp is in range */ +#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT)) + +/* return 1 if a slew-rate rising/falling edge value is in range */ +#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)) + +/* return 1 if a driver output pull-up/down strength code value is in range */ +#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)) + +/* return 1 if a low-power mode value is in range */ +#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)) + +/* Defines a pin group cfg's low-power mode select */ +enum pgrp_lpmd { + PGRP_LPMD_X8 = 0, + PGRP_LPMD_X4, + PGRP_LPMD_X2, + PGRP_LPMD_X, + PGRP_LPMD_NONE = -1, +}; + +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pgrp_schmt { + PGRP_SCHMT_DISABLE = 0, + PGRP_SCHMT_ENABLE = 1, +}; + +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pgrp_hsm { + PGRP_HSM_DISABLE = 0, + PGRP_HSM_ENABLE = 1, +}; + +/* + * This defines the configuration for a pin group's pad control config + */ +struct padctrl_config { + enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */ + int slwf; /* falling edge slew */ + int slwr; /* rising edge slew */ + int drvup; /* pull-up drive strength */ + int drvdn; /* pull-down drive strength */ + enum pgrp_lpmd lpmd; /* low-power mode selection */ + enum pgrp_schmt schmt; /* schmidt enable */ + enum pgrp_hsm hsm; /* high-speed mode enable */ +}; + +/* t114 pin drive group and pin mux registers */ +#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) +#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ + PDRIVE_PINGROUP_COUNT) struct pmux_tri_ctlr { uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ @@ -541,4 +598,12 @@ void pinmux_config_table(struct pingroup_config *config, int len); /* Set a group of pins from a table */ void pinmux_init(void); -#endif /* _TEGRA114_PINMUX_H_ */ +/** + * Set the GP pad configs + * + * @param config List of config items + * @param len Number of config items in list + */ +void padgrp_config_table(struct padctrl_config *config, int len); + +#endif /* _TEGRA114_PINMUX_H_ */ diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index d258819..e6fe842 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -79,6 +79,18 @@ #define USB_PINMUX CEC_PINMUX +#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .padgrp = PDRIVE_PINGROUP_##_padgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PGRP_LPMD_##_lpmd, \ + .schmt = PGRP_SCHMT_##_schmt, \ + .hsm = PGRP_HSM_##_hsm, \ + } + static struct pingroup_config tegra114_pinmux_common[] = { /* EXTPERIPH1 pinmux */ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), @@ -349,4 +361,8 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = { DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), }; + +static struct padctrl_config dalmore_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ +}; #endif /* PINMUX_CONFIG_COMMON_H */ -- 1.7.0.4

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[U-Boot] [PATCH] Tegra114: fdt: Move aliases from dtsi to dts file as per other Tegras
by Tom Warren 12 Mar '13

12 Mar '13

All other Tegra boards have their aliase nodes in the .dts file Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/dts/tegra114.dtsi | 8 -------- board/nvidia/dts/tegra114-dalmore.dts | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index dfeac53..701c0f9 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -3,14 +3,6 @@ / { compatible = "nvidia,tegra114"; - aliases { - i2c0 = "/i2c@7000d000"; - i2c1 = "/i2c@7000c000"; - i2c2 = "/i2c@7000c400"; - i2c3 = "/i2c@7000c500"; - i2c4 = "/i2c@7000c700"; - }; - tegra_car: clock { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 3e1e1ea..30cf1fb 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -6,6 +6,14 @@ model = "NVIDIA Dalmore"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x80000000>; -- 1.7.0.4

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[U-Boot] [GIT PULL] please pull u-boot-atmel/master
by Andreas Bießmann 12 Mar '13

12 Mar '13

Dear Albert Aribaud, please pull the following changes into u-boot-arm/master. The following changes since commit 9f024f62e4604274a23213dcee30016092e32e7b: Merge branch 'fixes' of git://git.denx.de/u-boot-mips (2013-02-15 12:23:42 -0500) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 08f0533a147ca37546a6539b43fce3916e82811a: ARM: sam9x5: fix ethernet pins in MII mode (2013-03-12 13:02:20 +0100) ---------------------------------------------------------------- Bo Shen (3): ARM: atmel: add at91sam9g20ek_2mmc nand boot support ARM: at91: change nand flash table ARM: at91sam9x5: Using CPU string directly Jesse Gilles (1): ARM: sam9x5: fix ethernet pins in MII mode Nicolas Ferre (2): arm: at91/configs: add libfdt to configuration arm: at91/configs: add bootz to configuration arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 30 +++++++++++----------- arch/arm/include/asm/arch-at91/at91sam9x5.h | 6 ----- board/atmel/at91sam9260ek/at91sam9260ek.c | 7 ++++- boards.cfg | 1 + include/configs/at91rm9200ek.h | 3 +++ include/configs/at91sam9260ek.h | 23 ++++++++++------- include/configs/at91sam9261ek.h | 19 +++++++------- include/configs/at91sam9263ek.h | 20 +++++++++------ include/configs/at91sam9m10g45ek.h | 17 ++++++------ include/configs/at91sam9rlek.h | 3 +++ include/configs/at91sam9x5ek.h | 12 +++++---- 11 files changed, 79 insertions(+), 62 deletions(-)

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[U-Boot] [PATCH] cmd_mem.c: Fix warning when CONFIG_CMD_MEMTEST is not set
by Tom Rini 12 Mar '13

12 Mar '13

mem_test_quick and mem_test_alt functions are only called by do_mem_mtest, so move them under the #ifdef Signed-off-by: Tom Rini <trini(a)ti.com> --- common/cmd_mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 53572f7..64dd76a 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -631,6 +631,7 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_LOOPW */ +#ifdef CONFIG_CMD_MEMTEST static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, vu_long *dummy) { @@ -910,7 +911,6 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr, return 0; } -#ifdef CONFIG_CMD_MEMTEST /* * Perform a memory test. A more complete alternative test can be * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until -- 1.7.9.5

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[U-Boot] USB patches
by Simon Glass 12 Mar '13

12 Mar '13

Hi Marek, As requested here is an email about the USB patches. I have put them in a bundle here: http://patchwork.ozlabs.org/bundle/sjg/for-marex/ Regards, Simon

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 12 Mar '13

12 Mar '13

Hello, The following changes since commit fc959081d41aab2d6f4614c5fb3dd1b77ffcdcf4: x86: Enable CONFIG_OF_CONTROL on coreboot (2013-03-04 15:57:52 -0800) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to 76b40ab41eff1f402ee52ba768b09daad293b9bb: Merge u-boot/master into u-boot-ti/master (2013-03-11 12:16:13 -0400) ---------------------------------------------------------------- Enric Balletbo i Serra (4): SPL: ONENAND: Fix some ONENAND related defines. SPL: ONENAND: Fix onenand_spl_load_image implementation. SPL: ONENAND: Support SPL to boot u-boot from OneNAND. OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled. Lokesh Vutla (13): ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register ARM: OMAP4+: Cleanup emif specific files ARM: OMAP4+: Make control module register structure generic ARM: OMAP5: Clean up iosettings code ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup arm: dra7xx: clock: Add the prcm changes arm: dra7xx: clock: Add the dplls data arm: dra7xx: Add control module changes arm: dra7xx: Add DDR related data for DRA752 ES1.0 arm: dra7xx: Add board files for DRA7XX socs arm: dra7xx: Add dra7xx_evm build support arm: dra7xx: Add silicon id support for DRA752 soc Mark Jackson (1): Allow AM33xx boards to setup GPMC chipselects. Mugunthan V N (1): am335x: cpsw: optimize cpsw_send to increase network performance Nikita Kiryanov (14): omap: consolidate common mmc definitions omap_hsmmc: fix out of bounds array access omap_hsmmc: introduce omap_hsmmc_data struct omap_hsmmc: implement driver check for card detection cm-t35: implement board specific card detect check mmc: add support for write protection omap_hsmmc: add driver check for write protection omap3: add useful dss defines omap3: allow dynamic selection of gfx_format lcd: add option for board specific splash screen preparation cm-t35: add support for dvi displays cm-t35: add support for user defined lcd parameters lcd: implement a callback for splashimage cm_t35: prevent splashimage from being set to a bad value SRICHARAN R (6): ARM: OMAP4+: Change the PRCM structure prototype common for all Socs ARM: OMAP4+: Cleanup the clocks layer ARM: OMAP4+: Clean up the pmic code ARM: OMAP5: Add silicon id support for ES2.0 revision. ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum Tom Rini (8): am335x_evm: Never set CONFIG_EXTRA_ENV_SETTINGS in SPL am335x_evm: Add am335x_evm_usbspl build target am33xx: Update DDR3 EMIF configuration sequence am335x_evm: Enable CONFIG_CMD_BOOTZ omap5_evm: Enable CONFIG_CMD_BOOTZ omap3_beagle: Enable CONFIG_CMD_BOOTZ omap4_common: Enable CONFIG_CMD_BOOTZ Merge u-boot/master into u-boot-ti/master The following diffstat is a little "funny" since to generate something close to correct I had to make a manual merge branch of u-boot-arm/master + u-boot/master and compare vs that. MAINTAINERS | 1 + README | 19 + arch/arm/cpu/arm1136/mx35/generic.c | 2 +- arch/arm/cpu/armv7/am33xx/board.c | 4 +- arch/arm/cpu/armv7/am33xx/ddr.c | 12 +- arch/arm/cpu/armv7/omap-common/boot-common.c | 7 +- arch/arm/cpu/armv7/omap-common/clocks-common.c | 312 +++++--- arch/arm/cpu/armv7/omap-common/emif-common.c | 73 +- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 23 +- arch/arm/cpu/armv7/omap-common/vc.c | 11 +- arch/arm/cpu/armv7/omap3/board.c | 6 +- arch/arm/cpu/armv7/omap4/Makefile | 3 +- arch/arm/cpu/armv7/omap4/clocks.c | 517 ------------ arch/arm/cpu/armv7/omap4/hw_data.c | 491 ++++++++++++ arch/arm/cpu/armv7/omap4/hwinit.c | 36 +- arch/arm/cpu/armv7/omap4/prcm-regs.c | 315 ++++++++ arch/arm/cpu/armv7/omap4/sdram_elpida.c | 34 +- arch/arm/cpu/armv7/omap5/Makefile | 3 +- arch/arm/cpu/armv7/omap5/clocks.c | 494 ------------ arch/arm/cpu/armv7/omap5/hw_data.c | 596 ++++++++++++++ arch/arm/cpu/armv7/omap5/hwinit.c | 292 ++++--- arch/arm/cpu/armv7/omap5/prcm-regs.c | 958 +++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/sdram.c | 214 ++++- arch/arm/cpu/armv7/zynq/Makefile | 1 + arch/arm/cpu/armv7/zynq/cpu.c | 28 +- arch/arm/cpu/armv7/zynq/slcr.c | 63 ++ arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 140 +--- arch/arm/include/asm/arch-am33xx/spl.h | 1 + arch/arm/include/asm/arch-am33xx/sys_proto.h | 2 + arch/arm/include/asm/arch-davinci/gpio.h | 7 +- arch/arm/include/asm/arch-mx35/spl.h | 2 +- arch/arm/include/asm/arch-omap3/dss.h | 31 + arch/arm/include/asm/arch-omap3/mmc_host_def.h | 139 +--- arch/arm/include/asm/arch-omap3/spl.h | 2 +- arch/arm/include/asm/arch-omap4/clocks.h | 562 +------------ arch/arm/include/asm/arch-omap4/mmc_host_def.h | 140 +--- arch/arm/include/asm/arch-omap4/omap.h | 34 +- arch/arm/include/asm/arch-omap4/spl.h | 2 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap5/clocks.h | 539 +------------ arch/arm/include/asm/arch-omap5/mmc_host_def.h | 140 +--- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 344 ++++++++ arch/arm/include/asm/arch-omap5/mux_omap5.h | 8 - arch/arm/include/asm/arch-omap5/omap.h | 125 +-- arch/arm/include/asm/arch-omap5/spl.h | 2 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 10 +- arch/arm/include/asm/arch-zynq/hardware.h | 85 ++ arch/arm/include/asm/arch-zynq/sys_proto.h | 30 + arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/emif.h | 20 +- arch/arm/include/asm/omap_common.h | 523 +++++++++++++ arch/arm/include/asm/omap_mmc.h | 168 ++++ board/cm_t35/Makefile | 1 + board/cm_t35/cm_t35.c | 16 +- board/cm_t35/display.c | 428 ++++++++++ board/comelit/dig297/dig297.c | 3 +- board/corscience/tricorder/tricorder.c | 2 +- board/htkw/mcx/mcx.c | 3 +- board/isee/igep00x0/igep00x0.c | 3 +- board/isee/igep00x0/igep00x0.h | 7 +- board/logicpd/am3517evm/am3517evm.c | 3 +- board/logicpd/omap3som/omap3logic.c | 2 +- board/logicpd/zoom1/zoom1.c | 3 +- board/logicpd/zoom2/zoom2.c | 3 +- board/matrix_vision/mvblx/fpga.c | 14 +- board/matrix_vision/mvblx/mvblx.c | 4 +- board/matrix_vision/mvblx/sys_eeprom.c | 24 + board/nokia/rx51/rx51.c | 4 +- board/ns9750dev/config.mk | 16 - board/ns9750dev/flash.c | 474 ----------- board/ns9750dev/led.c | 46 -- board/ns9750dev/lowlevel_init.S | 298 ------- board/ns9750dev/ns9750dev.c | 125 --- board/overo/overo.c | 3 +- board/pandora/pandora.c | 3 +- board/phytec/pcm051/mux.c | 1 - board/technexion/twister/twister.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 4 +- board/ti/am335x/board.c | 40 +- board/ti/am3517crane/am3517crane.c | 3 +- board/ti/beagle/beagle.c | 17 +- board/ti/beagle/beagle.h | 6 +- board/{ns9750dev => ti/dra7xx}/Makefile | 22 +- board/ti/dra7xx/evm.c | 103 +++ board/ti/dra7xx/mux_data.h | 47 ++ board/ti/evm/evm.c | 3 +- board/ti/omap5_evm/evm.c | 4 +- board/ti/panda/panda.c | 3 +- board/ti/sdp3430/sdp.c | 3 +- board/ti/sdp4430/sdp.c | 4 +- board/timll/devkit8000/devkit8000.c | 3 +- boards.cfg | 5 + common/cmd_mmc.c | 7 + common/lcd.c | 41 + common/spl/Makefile | 1 + common/spl/spl.c | 10 + common/spl/spl_onenand.c | 47 ++ doc/README.displaying-bmps | 27 + doc/README.ns9750dev | 36 - doc/README.scrapyard | 161 ++-- doc/SPL/README.am335x-network | 92 +++ doc/driver-model/UDM-serial.txt | 2 +- drivers/gpio/da8xx_gpio.c | 137 +++- drivers/mmc/arm_pl180_mmci.c | 1 + drivers/mmc/bfin_sdh.c | 1 + drivers/mmc/davinci_mmc.c | 1 + drivers/mmc/fsl_esdhc.c | 1 + drivers/mmc/ftsdc010_esdhc.c | 1 + drivers/mmc/gen_atmel_mci.c | 1 + drivers/mmc/mmc.c | 17 + drivers/mmc/mmc_spi.c | 1 + drivers/mmc/mxcmmc.c | 1 + drivers/mmc/mxsmmc.c | 1 + drivers/mmc/omap_hsmmc.c | 103 ++- drivers/mmc/sdhci.c | 1 + drivers/mmc/sh_mmcif.c | 1 + drivers/mmc/tegra_mmc.c | 1 + drivers/mtd/onenand/onenand_spl.c | 14 +- drivers/net/cpsw.c | 20 +- drivers/serial/Makefile | 1 - drivers/serial/ns9750_serial.c | 218 ------ drivers/serial/serial.c | 2 - drivers/video/omap3_dss.c | 2 +- include/configs/am335x_evm.h | 83 +- include/configs/cm_t35.h | 9 + include/configs/dra7xx_evm.h | 36 + include/configs/ea20.h | 1 + include/configs/igep00x0.h | 7 +- include/configs/ns9750dev.h | 187 ----- include/configs/omap3_beagle.h | 3 +- include/configs/omap3_mvblx.h | 25 +- include/configs/omap4_common.h | 2 +- include/configs/omap5_common.h | 262 +++++++ include/configs/omap5_evm.h | 240 +----- include/configs/zynq.h | 5 + include/env_callback.h | 7 + include/lcd.h | 1 + include/mmc.h | 2 + include/ns9750_bbus.h | 125 --- include/ns9750_mem.h | 172 ---- include/ns9750_ser.h | 202 ----- include/ns9750_sys.h | 215 ----- include/spl.h | 3 + spl/Makefile | 2 + 144 files changed, 6257 insertions(+), 5611 deletions(-) delete mode 100644 arch/arm/cpu/armv7/omap4/clocks.c create mode 100644 arch/arm/cpu/armv7/omap4/hw_data.c create mode 100644 arch/arm/cpu/armv7/omap4/prcm-regs.c delete mode 100644 arch/arm/cpu/armv7/omap5/clocks.c create mode 100644 arch/arm/cpu/armv7/omap5/hw_data.c create mode 100644 arch/arm/cpu/armv7/omap5/prcm-regs.c create mode 100644 arch/arm/cpu/armv7/zynq/slcr.c create mode 100644 arch/arm/include/asm/arch-omap5/mux_dra7xx.h create mode 100644 arch/arm/include/asm/arch-zynq/hardware.h create mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h create mode 100644 arch/arm/include/asm/omap_mmc.h create mode 100644 board/cm_t35/display.c delete mode 100644 board/ns9750dev/config.mk delete mode 100644 board/ns9750dev/flash.c delete mode 100644 board/ns9750dev/led.c delete mode 100644 board/ns9750dev/lowlevel_init.S delete mode 100644 board/ns9750dev/ns9750dev.c rename board/{ns9750dev => ti/dra7xx}/Makefile (74%) create mode 100644 board/ti/dra7xx/evm.c create mode 100644 board/ti/dra7xx/mux_data.h create mode 100644 common/spl/spl_onenand.c create mode 100644 doc/README.displaying-bmps delete mode 100644 doc/README.ns9750dev create mode 100644 doc/SPL/README.am335x-network delete mode 100644 drivers/serial/ns9750_serial.c create mode 100644 include/configs/dra7xx_evm.h delete mode 100644 include/configs/ns9750dev.h create mode 100644 include/configs/omap5_common.h delete mode 100644 include/ns9750_bbus.h delete mode 100644 include/ns9750_mem.h delete mode 100644 include/ns9750_ser.h delete mode 100644 include/ns9750_sys.h This includes the following change as the merge commit for merging u-boot/master into u-boot-ti/master: arch/arm/include/asm/arch-davinci/gpio.h | 5 ++++- drivers/gpio/da8xx_gpio.c | 8 ++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h index fbbb1f3..06390c8 100644 --- a/arch/arm/include/asm/arch-davinci/gpio.h +++ b/arch/arm/include/asm/arch-davinci/gpio.h @@ -67,7 +67,10 @@ struct davinci_gpio_bank { #define gpio_status() gpio_info() #define GPIO_NAME_SIZE 20 -#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +#if defined(CONFIG_SOC_DM644X) +/* GPIO0 to GPIO53, omit the V3.3 volts one */ +#define MAX_NUM_GPIOS 70 +#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) #define MAX_NUM_GPIOS 128 #else #define MAX_NUM_GPIOS 144 diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 271b8d9..76648d2 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -31,6 +31,7 @@ static struct gpio_registry { char name[GPIO_NAME_SIZE]; } gpio_registry[MAX_NUM_GPIOS]; +#if defined(CONFIG_SOC_DA8XX) #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) #if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) @@ -164,7 +165,7 @@ static const struct pinmux_config gpio_pinmux[] = { { pinmux(0), 1, 0 }, { pinmux(0), 1, 1 }, }; -#else +#else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */ static const struct pinmux_config gpio_pinmux[] = { { pinmux(1), 8, 7 }, /* GP0[0] */ { pinmux(1), 8, 6 }, @@ -311,7 +312,10 @@ static const struct pinmux_config gpio_pinmux[] = { { pinmux(18), 8, 3 }, { pinmux(18), 8, 2 }, }; -#endif +#endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */ +#else /* !CONFIG_SOC_DA8XX */ +#define davinci_configure_pin_mux(a, b) +#endif /* CONFIG_SOC_DA8XX */ int gpio_request(unsigned gpio, const char *label) { -- Tom

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[U-Boot] [PATCH v5] usb: Add multiple controllers support for EHCI PCI
by Simon Glass 12 Mar '13

12 Mar '13

From: Vincent Palatin <vpalatin(a)chromium.org> Use the ability to have several active EHCI controller on a system in the PCI EHCI controller implementation. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v5: - Rebase to usb/master Changes in v4: - Add errno.h header file to ehci-pci Changes in v2: - Add blank line before function return drivers/usb/host/ehci-pci.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 001d141..90d7a6f 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -34,7 +34,7 @@ static struct pci_device_id ehci_pci_ids[] = { {0, 0} }; #else -static pci_dev_t ehci_find_class(void) +static pci_dev_t ehci_find_class(int index) { int bus; int devnum; @@ -54,7 +54,8 @@ static pci_dev_t ehci_find_class(void) bdf += PCI_BDF(0, 0, 1)) { pci_read_config_dword(bdf, PCI_CLASS_REVISION, &class); - if (class >> 8 == PCI_CLASS_SERIAL_USB_EHCI) + if ((class >> 8 == PCI_CLASS_SERIAL_USB_EHCI) + && !index--) return bdf; } } @@ -68,29 +69,35 @@ static pci_dev_t ehci_find_class(void) * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr, + struct ehci_hcor **ret_hcor) { pci_dev_t pdev; uint32_t cmd; + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; #ifdef CONFIG_PCI_EHCI_DEVICE pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); #else - pdev = ehci_find_class(); + pdev = ehci_find_class(index); #endif if (pdev < 0) { printf("EHCI host controller not found\n"); return -1; } - *hccr = (struct ehci_hccr *)pci_map_bar(pdev, + hccr = (struct ehci_hccr *)pci_map_bar(pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + (uint32_t)hccr, (uint32_t)hcor, + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + *ret_hccr = hccr; + *ret_hcor = hcor; /* enable busmaster */ pci_read_config_dword(pdev, PCI_COMMAND, &cmd); -- 1.8.1.3

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[U-Boot] [PATCH] ARM: sam9x5: fix ethernet pins in MII mode
by Bo Shen 12 Mar '13

12 Mar '13

From: Jesse Gilles <jgilles(a)multitech.com> Fix pin setting in MII mode Signed-off-by: Jesse Gilles <jgilles(a)multitech.com> --- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index d0d31da..3c58536 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -206,14 +206,14 @@ void at91_macb_hw_init(void) #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } -- 1.7.9.5

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