March 2013 - U-Boot

[U-Boot] [PATCH 1/1] USB: EHCI: Add weak functions to support new chip
by Jim Lin 27 Mar '13

27 Mar '13

Add ehci_get_port_speed() and ehci_set_usbmode() weak functions for platform driver to support new chip. Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- drivers/usb/host/ehci-hcd.c | 40 ++++++++++++++++++++++++++++------------ 1 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index c816878..6a55cd2 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -122,6 +122,31 @@ static struct descriptor { #define ehci_is_TDI() (0) #endif +int __ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) +{ + return PORTSC_PSPD(reg); +} + +int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg) + __attribute__((weak, alias("__ehci_get_port_speed"))); + +void __ehci_set_usbmode(int index) +{ + uint32_t tmp; + uint32_t *reg_ptr; + + reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd + USBMODE); + tmp = ehci_readl(reg_ptr); + tmp |= USBMODE_CM_HC; +#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) + tmp |= USBMODE_BE; +#endif + ehci_writel(reg_ptr, tmp); +} + +void ehci_set_usbmode(int index) + __attribute__((weak, alias("__ehci_set_usbmode"))); + void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) { mdelay(50); @@ -149,8 +174,6 @@ static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) static int ehci_reset(int index) { uint32_t cmd; - uint32_t tmp; - uint32_t *reg_ptr; int ret = 0; cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd); @@ -163,15 +186,8 @@ static int ehci_reset(int index) goto out; } - if (ehci_is_TDI()) { - reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE); - tmp = ehci_readl(reg_ptr); - tmp |= USBMODE_CM_HC; -#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) - tmp |= USBMODE_BE; -#endif - ehci_writel(reg_ptr, tmp); - } + if (ehci_is_TDI()) + ehci_set_usbmode(index); #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning); @@ -711,7 +727,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; if (ehci_is_TDI()) { - switch (PORTSC_PSPD(reg)) { + switch (ehci_get_port_speed(ctrl->hcor, reg)) { case PORTSC_PSPD_FS: break; case PORTSC_PSPD_LS: -- 1.7.7

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[U-Boot] [PATCH] mx6: Fix the reading of CPU revision
by Fabio Estevam 27 Mar '13

27 Mar '13

Currently when booting a mx6 solo processor get_cpu_rev() returns 0x62xxx, which is an invalid mx6 CPU revision. This causes run-time problems when trying to use VPU library in the kernel, as this library loads the VPU firmware according to the CPU type. Fix get_cpu_rev() so that it correctly returns 0x61xxx for a mx6 solo. While at it, also remove the duplicate definitions for MXC_CPU_ types. Tested on a Wandboard solo and on a mx6qsabresd. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/cpu/armv7/mx6/soc.c | 28 ++++++++++++---------------- arch/arm/imx-common/cpu.c | 16 ++++++++++------ arch/arm/include/asm/arch-mx5/sys_proto.h | 7 ------- arch/arm/include/asm/arch-mx6/sys_proto.h | 7 ------- 4 files changed, 22 insertions(+), 36 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 193ba12..87725eb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -43,22 +43,18 @@ struct scu_regs { u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - u32 reg = readl(&anatop->digprog_sololite); - u32 type = ((reg >> 16) & 0xff); - - if (type != MXC_CPU_MX6SL) { - reg = readl(&anatop->digprog); - type = ((reg >> 16) & 0xff); - if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - - if (!cfg) - type = MXC_CPU_MX6SOLO; - } - } - reg &= 0xff; /* mx6 silicon revision */ - return (type << 12) | (reg + 0x10); + u32 fsl_system_rev; + u32 cpu_rev = readl(&anatop->digprog); + + /* Chip Silicon ID */ + fsl_system_rev = ((cpu_rev >> 16) & 0xFF) << 12; + /* Chip silicon major revision */ + fsl_system_rev |= ((cpu_rev >> 8) & 0xFF) << 4; + fsl_system_rev += 0x10; + /* Chip silicon minor revision */ + fsl_system_rev |= cpu_rev & 0xFF; + + return fsl_system_rev; } void init_aips(void) diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a9b86c1..2f518c5 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -117,15 +117,19 @@ unsigned imx_ddr_size(void) #if defined(CONFIG_DISPLAY_CPUINFO) +#define MXC_CPU_MX51 0x51 +#define MXC_CPU_MX53 0x53 +#define MXC_CPU_MX6SL 0x60 +#define MXC_CPU_MX6DL_S 0x61 +#define MXC_CPU_MX6Q_D 0x63 + const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_MX6Q: - return "6Q"; /* Quad-core version of the mx6 */ - case MXC_CPU_MX6DL: - return "6DL"; /* Dual Lite version of the mx6 */ - case MXC_CPU_MX6SOLO: - return "6SOLO"; /* Solo version of the mx6 */ + case MXC_CPU_MX6Q_D: + return "6Q/D"; /* Quad/Dual version of the mx6 */ + case MXC_CPU_MX6DL_S: + return "6DL/S"; /* Dual-Lite/Solo version of the mx6 */ case MXC_CPU_MX6SL: return "6SL"; /* Solo-Lite version of the mx6 */ case MXC_CPU_MX51: diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 93ad1c6..a2e88bb 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -24,13 +24,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 - #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); unsigned imx_ddr_size(void); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 3193297..0278317 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -24,13 +24,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#define MXC_CPU_MX51 0x51 -#define MXC_CPU_MX53 0x53 -#define MXC_CPU_MX6SL 0x60 -#define MXC_CPU_MX6DL 0x61 -#define MXC_CPU_MX6SOLO 0x62 -#define MXC_CPU_MX6Q 0x63 - #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); -- 1.7.9.5

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[U-Boot] fpga parallel flash loader
by Klemen Dovrtel 27 Mar '13

27 Mar '13

Hello everybody, I have got the Spartan 3E Smple Pack with Intel Parallel Flash. I would like to load the parallel flash with the design I synthesized with ISE. So i need some kind of loader for the parallel flash which will run on the fpga. Can this be done with U-Boot? Regards, Klemen

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[U-Boot] [PATCH 00/13] video: exynos: Add DT support for exynos_fb and exynos_dp drivers
by Ajay Kumar 27 Mar '13

27 Mar '13

Ajay Kumar (13): [PATCH 01/13] video: exynos_fb: Remove callbacks from the driver [PATCH 02/13] video: exynos_dp: Remove callbacks from the driver [PATCH 03/13] video: exynos_fb: Make fimd_ctrl global [PATCH 04/13] EXYNOS: FDT: Add compatible strings for FIMD [PATCH 05/13] video: exynos_fb: add DT support for FIMD driver [PATCH 06/13] EXYNOS5: Add device node for FIMD [PATCH 07/13] SMDK5250: Add device node for FIMD [PATCH 08/13] video: exynos_dp: Make dp_regs global [PATCH 09/13] EXYNOS5: FDT: Add compatible strings for FIMD [PATCH 10/13] video: exynos_dp: Add function to parse DP DT node [PATCH 11/13] EXYNOS5: Add device node for DP [PATCH 12/13] SMDK5250: Add device node for DP [PATCH 13/13] SMDK5250: Use statically defined structures only in non DT case arch/arm/dts/exynos5250.dtsi | 13 ++ arch/arm/include/asm/arch-exynos/dp_info.h | 1 - board/samsung/dts/exynos5250-smdk5250.dts | 40 +++++ board/samsung/smdk5250/smdk5250.c | 16 +- board/samsung/trats/trats.c | 6 +- board/samsung/universal_c210/universal.c | 23 +-- doc/device-tree-bindings/video/exynos-dp.txt | 69 ++++++++ doc/device-tree-bindings/video/exynos-fb.txt | 92 +++++++++++ drivers/video/exynos_dp.c | 76 ++++++++- drivers/video/exynos_dp_lowlevel.c | 69 +++----- drivers/video/exynos_dp_lowlevel.h | 1 + drivers/video/exynos_fb.c | 230 +++++++++++++++++++++++++-- drivers/video/exynos_fimd.c | 44 +++-- include/fdtdec.h | 2 + include/lcd.h | 9 -- lib/fdtdec.c | 2 + 16 files changed, 574 insertions(+), 119 deletions(-) create mode 100644 doc/device-tree-bindings/video/exynos-dp.txt create mode 100644 doc/device-tree-bindings/video/exynos-fb.txt -- 1.8.0

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[U-Boot] Displaying characters on the display in u-boot
by Bhargav A K 27 Mar '13

27 Mar '13

Hi All I have been able to display a splash screen in u-boot by converting the splash image to a header (using GIMP) and loading it into a GFX register (OMAP 4470). Now I have to display text(character) on the display. I read about CONFIG_CFB_CONSOLE in the u-boot documentation. How exactly does it work, is it the right method to display characters on the screen ? Please give me some direction with this issue.. Kind regards Bhargav SASKEN BUSINESS DISCLAIMER: This message may contain confidential, proprietary or legally privileged information. In case you are not the original intended Recipient of the message, you must not, directly or indirectly, use, disclose, distribute, print, or copy any part of this message and you are requested to delete it and inform the sender. Any views expressed in this message are those of the individual sender unless otherwise stated. Nothing contained in this message shall be construed as an offer or acceptance of any offer by Sasken Communication Technologies Limited ("Sasken") unless sent with that express intent and with due authority of Sasken. Sasken has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email. Read Disclaimer at http://www.sasken.com/extras/mail_disclaimer.html

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Re: [U-Boot] [PATCH] Exynos5: clock: Update the equation to calculate PLL output frequency
by Akshay Saraswat 27 Mar '13

27 Mar '13

>On Fri, Mar 22, 2013 at 5:26 AM, Akshay Saraswat <akshay.s(a)samsung.com> wrote: >> According to the latest exynos5 user manual, the equation for >> calculating PLL output was changed to >> FOUT= MDIV x FIN/(PDIV x 2^SDIV) >> earlier it was >> FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) >> So updating the clock code accordingly. >> >> Signed-off-by: Hatim Ali <hatim.rv(a)samsung.com> >> Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> > >Acked-by: Simon Glass <sjg(a)chromium.org> > >I think this is EVT1 silicon, right? > Yes, this is for evt1 silicon. >> --- >> arch/arm/cpu/armv7/exynos/clock.c | 6 ++---- >> 1 file changed, 2 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c >> index 956427c..5299bc7 100644 >> --- a/arch/arm/cpu/armv7/exynos/clock.c >> +++ b/arch/arm/cpu/armv7/exynos/clock.c >> @@ -73,10 +73,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) >> /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ >> fout = (m + k / 1024) * (freq / (p * (1 << s))); >> } else { >> - if (s < 1) >> - s = 1; >> - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ >> - fout = m * (freq / (p * (1 << (s - 1)))); >> + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ >> + fout = m * (freq / (p * (1 << s))); >> } >> >> return fout; >> -- >> 1.8.0 >> > Regards, Akshay Saraswat

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[U-Boot] [PATCH] powerpc/tools/pblimage: use SYS_TEXT_BASE instead of hardcoded value
by Shaohui Xie 27 Mar '13

27 Mar '13

That the pblimage can be built according to the SYS_TEXT_BASE, then building a different size of pblimage is available. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- tools/pblimage.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/pblimage.c b/tools/pblimage.c index 508a747..60277a4 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -29,10 +29,9 @@ * The PBL can load up to 64 bytes at a time, so we split the U-Boot * image into 64 byte chunks. PBL needs a command for each piece, of * the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE - * is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit, - * so it starts from 0x81F80000. + * is the start offset and PBL only cares about low 24-bit. */ -static uint32_t next_pbl_cmd = 0x81F80000; +static uint32_t next_pbl_cmd = 0x81000000 | (CONFIG_SYS_TEXT_BASE & 0xFFFFFF); /* * need to store all bytes in memory for calculating crc32, then write the * bytes to image file for PBL boot. -- 1.8.0

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[U-Boot] [PATCH 0/4] EXYNOS5: Enable dwmmc
by Amar 27 Mar '13

27 Mar '13

This patch set enables the dwmmc for Exynos5250 on SMDK5250. Also does the required driver changes. This patch set is based on: "EXYNOS: mmc: support DesignWare Controller for Samsung-SoC" "Exynos: clock: support get_mmc_clk for exynos" Amar (4): MMC: DWMMC: Modified fifo size computation MMC: EXYNOS: Added call back function for clock get EXYNOS: CLOCK: Initialised the local variable SMDK5250: Initialise and enable dwmmc channels arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- board/samsung/smdk5250/smdk5250.c | 32 ++++++++++++++++++++++++++------ drivers/mmc/dw_mmc.c | 2 ++ drivers/mmc/exynos_dw_mmc.c | 13 ++++++++++++- include/configs/smdk5250.h | 4 ++-- 5 files changed, 44 insertions(+), 11 deletions(-)

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[U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
by Rajeshwari Shinde 27 Mar '13

27 Mar '13

This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi <arun.m(a)samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> --- arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..676a388 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include <common.h> #include <asm/io.h> +#include <asm/system.h> + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1<<9), + CACHE_DATA_RAM_SETUP = (1<<5), + CACHE_TAG_RAM_LATENCY = (2<<6), + CACHE_DATA_RAM_LATENCY = (2<<0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,32 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + if (cpu_is_exynos5()) + exynos5_set_l2cache_params(); +} +#endif + -- 1.7.4.4

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[U-Boot] [PATCH] arm: omap: emif: Support for ddr3 after warm reset
by Lokesh Vutla 27 Mar '13

27 Mar '13

EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/cpu/armv7/omap-common/emif-common.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 9eb1279..8811958 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1072,6 +1072,12 @@ static void do_sdram_init(u32 base) else ddr3_init(base, regs); } + if (!in_sdram && warm_reset() && + (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { + set_lpmode_selfrefresh(base); + emif_reset_phy(base); + ddr3_leveling(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); @@ -1259,10 +1265,10 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!(in_sdram || warm_reset())) { - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + if (!in_sdram) { + if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else + else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } -- 1.7.9.5

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