November 2013 - U-Boot

[U-Boot] [PATCH 13/34] zynq: Add zynq zed board support
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Zed is a complete development board based on the Xilinx Zynq-7000 All Programmable SoC. APSOC: - XC7Z020-CLG484-1 Memory: - 512 MB DDR3 - 256 Mb Quad-SPI Flash( - Full size SD/MMC card cage Connectivity: - 10/100/1000 Ethernet - USB OTG (Device/Host/OTG) - USB-UART Expansion: - FMC (Low Pin Count) - Pmod. headers (2x6) Video/Display: - HDMI output (1080p60 + audio) - VGA connector - 128 x 32 OLED - User LEDs (9) User inputs: - Slide switches (8) - Push button switches (7) Audio: - 24-bit stereo audio CODEC - Stereo line in/out - Headphone - Microphone input Analog: - Xilinx XADC header - Supports 4 analog inputs - 2 Differential / 4 Single-ended Debug: - On-board USB JTAG programming port - ARM Debug Access Port (DAP) For more info - http://zedboard.org/product/zedboard Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- boards.cfg | 1 + include/configs/zynq_zed.h | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 include/configs/zynq_zed.h diff --git a/boards.cfg b/boards.cfg index 64c693b..4a2286c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -345,6 +345,7 @@ Active arm armv7 u8500 st-ericsson snowball Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> +Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren(a)nvidia.com> Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding(a)avionic-design.de> Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding(a)avionic-design.de> diff --git a/include/configs/zynq_zed.h b/include/configs/zynq_zed.h new file mode 100644 index 0000000..1d3dcf7 --- /dev/null +++ b/include/configs/zynq_zed.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration for Zynq Evaluation and Development Board - ZedBoard + * See zynq_common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZED_H +#define __CONFIG_ZYNQ_ZED_H + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_QSPI +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include <configs/zynq-common.h> + +#endif /* __CONFIG_ZYNQ_ZED_H */ -- 1.8.3

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[U-Boot] [PATCH 12/34] zynq: Add zynq zc70x board support
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

The Zynq-7000 APSOC zc702 and zc706 enabled complte embedded processing includes ASIC and FPGA design. ZC702-: APSOC: - XC7Z020-CLG484-1 Memory: - DDR3 Component Memory 1GB - 16MB Quad SPI Flash - IIC - 1 KB EEPROM Connectivity: - Gigabit Ethernet GMII, RGMII and SGMII. - USB OTG - Host USB - IIC Bus Headers/HUB - 1 CAN with Wake on CAN - USB-UART Video/Display: - HDMI Video OUT - 8X LEDs Control & I/O: - 3 User Push Buttons - 2 User Switches - 8 User LEDs For more info on zc702 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm ZC706-: APSOC: - XC7Z045 FFG900 -2 AP SoC Memory: - DDR3 Component Memory 1GB (PS) - DDR3 SODIM Memory 1GB (PL) - 2X16MB Quad SPI Flash (dual parallel) - IIC - 1 KB EEPROM Connectivity: - PCIe Gen2x4 - SFP+ and SMA Pairs - GigE RGMII Ethernet (PS) - USB OTG 1 (PS) - Host USB - IIC Bus Headers/HUB (PS) - 1 CAN with Wake on CAN (PS) - USB-UART Video/Display: - HDMI 8 color RGB 4.4.4 1080P-60 OUT - HDMI IN 8 color RGB 4.4.4 Control & I/O: - 2 User Push Buttons/Dip Switch, 2 User LEDs - IIC access to GPIO - SDIO (SD Card slot) - 3 User Push Buttons, 2 User Switches, 8 User LEDs For more info on zc706 board: - http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- boards.cfg | 1 + include/configs/zynq-common.h | 9 --------- include/configs/zynq_zc70x.h | 26 ++++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 9 deletions(-) create mode 100644 include/configs/zynq_zc70x.h diff --git a/boards.cfg b/boards.cfg index 058ca3f..64c693b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -344,6 +344,7 @@ Active arm armv7 socfpga altera socfpga Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier(a)linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> +Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr(a)monstr.eu>:Jagannadha Sutradharudu Teki <jagannadh.teki(a)gmail.com> Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren(a)nvidia.com> Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding(a)avionic-design.de> Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding(a)avionic-design.de> diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 200401c..d69c59b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -36,7 +36,6 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Zynq Serial driver */ -#define CONFIG_ZYNQ_SERIAL_UART1 #ifdef CONFIG_ZYNQ_SERIAL_UART0 # define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 # define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE @@ -60,8 +59,6 @@ #endif /* Ethernet driver */ -#define CONFIG_ZYNQ_GEM0 -#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 #if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) # define CONFIG_NET_MULTI # define CONFIG_ZYNQ_GEM @@ -71,7 +68,6 @@ # define CONFIG_PHY_MARVELL #endif -#define CONFIG_ZYNQ_SPI /* SPI */ #ifdef CONFIG_ZYNQ_SPI # define CONFIG_SPI_FLASH @@ -89,10 +85,6 @@ # define CONFIG_SPI_FLASH_WINBOND #endif -/* NOR */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ZYNQ_SDHCI0 /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -106,7 +98,6 @@ # define CONFIG_DOS_PARTITION #endif -#define CONFIG_ZYNQ_I2C0 /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C diff --git a/include/configs/zynq_zc70x.h b/include/configs/zynq_zc70x.h new file mode 100644 index 0000000..559cd19 --- /dev/null +++ b/include/configs/zynq_zc70x.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2013 Xilinx, Inc. + * + * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards + * See zynq_common.h for Zynq common configs + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQ_ZC70X_H +#define __CONFIG_ZYNQ_ZC70X_H + +#define CONFIG_ZYNQ_SERIAL_UART1 +#define CONFIG_ZYNQ_GEM0 +#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ZYNQ_QSPI +#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_I2C0 +#define CONFIG_ZYNQ_BOOT_FREEBSD + +#include <configs/zynq-common.h> + +#endif /* __CONFIG_ZYNQ_ZC70X_H */ -- 1.8.3

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[U-Boot] [PATCH 11/34] zynq-common: Enable CONFIG_ZYNQ_QSPI
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Tested qspi on zynq board with stmicro, spansion and winbond flashes by enabling CONFIG_ZYNQ_QSPI. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq-common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 438215b..200401c 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -79,6 +79,16 @@ # define CONFIG_CMD_SF #endif +/* QSPI */ +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_CMD_SF +# define CONFIG_SF_DEFAULT_SPEED 30000000 +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_WINBOND +#endif + /* NOR */ #define CONFIG_SYS_NO_FLASH -- 1.8.3

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[U-Boot] [PATCH 09/34] zynq-common: Rename zynq with zynq-common
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

zynq.h -> zynq-common.h, zynq-common is Common configuration options for all Zynq boards. zynq.h is no longer exists hense removed from boards.cfg Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- boards.cfg | 2 -- include/configs/{zynq.h => zynq-common.h} | 9 ++++++--- 2 files changed, 6 insertions(+), 5 deletions(-) rename include/configs/{zynq.h => zynq-common.h} (95%) diff --git a/boards.cfg b/boards.cfg index 5e10125..058ca3f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -344,8 +344,6 @@ Active arm armv7 socfpga altera socfpga Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier(a)linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965(a)freescale.com> -Active arm armv7 zynq xilinx zynq zynq - Michal Simek <monstr(a)monstr.eu> -Active arm armv7 zynq xilinx zynq zynq_dcc zynq:ZYNQ_DCC Michal Simek <monstr(a)monstr.eu> Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren(a)nvidia.com> Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Thierry Reding <thierry.reding(a)avionic-design.de> Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Thierry Reding <thierry.reding(a)avionic-design.de> diff --git a/include/configs/zynq.h b/include/configs/zynq-common.h similarity index 95% rename from include/configs/zynq.h rename to include/configs/zynq-common.h index 680d503..438215b 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq-common.h @@ -1,11 +1,14 @@ /* * (C) Copyright 2012 Michal Simek <monstr(a)monstr.eu> + * (C) Copyright 2013 Xilinx, Inc. + * + * Common configuration options for all Zynq boards. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_ZYNQ_H -#define __CONFIG_ZYNQ_H +#ifndef __CONFIG_ZYNQ_COMMON_H +#define __CONFIG_ZYNQ_COMMON_H /* High Level configuration Options */ #define CONFIG_ARMV7 @@ -171,4 +174,4 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -#endif /* __CONFIG_ZYNQ_H */ +#endif /* __CONFIG_ZYNQ_COMMON_H */ -- 1.8.3

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[U-Boot] [PATCH 08/34] zynq: Add GEM0, GEM1 configs support
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Zynq ethernet controller support two GEM's like CONFIG_ZYNQ_GEM0 and CONFIG_ZYNQ_GEM1 enabled both so-that the respective board will define these macros based on their usage. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 1bcb28d..680d503 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -57,10 +57,16 @@ #endif /* Ethernet driver */ -#define CONFIG_NET_MULTI -#define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 +#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) +# define CONFIG_NET_MULTI +# define CONFIG_ZYNQ_GEM +# define CONFIG_MII +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define CONFIG_PHYLIB +# define CONFIG_PHY_MARVELL +#endif #define CONFIG_ZYNQ_SPI /* SPI */ @@ -103,12 +109,6 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_MAY_FAIL -/* MII and Phylib */ -#define CONFIG_MII -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_PHYLIB -#define CONFIG_PHY_MARVELL - /* Environment */ #define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -- 1.8.3

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[U-Boot] [PATCH 06/34] zynq: Enable cache options
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

- Enable cache command - Turn-off L2 cache - Turn-on D-cache Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index abeb2da..f32008b 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -16,6 +16,16 @@ # define CONFIG_CPU_FREQ_HZ 800000000 #endif +/* Cache options */ +#define CONFIG_CMD_CACHE +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + /* Serial drivers */ #define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ -- 1.8.3

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[U-Boot] [PATCH 05/34] zynq: Minor config cleanup
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Cleanups mostly on: - Add comments - Re-order configs - Remove #define CONFIG_ZYNQ_SDHCI Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 76 ++++++++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 8ccc667..abeb2da 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -7,33 +7,51 @@ #ifndef __CONFIG_ZYNQ_H #define __CONFIG_ZYNQ_H -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ +/* High Level configuration Options */ +#define CONFIG_ARMV7 #define CONFIG_ZYNQ /* CPU clock */ -#define CONFIG_CPU_FREQ_HZ 800000000 +#ifndef CONFIG_CPU_FREQ_HZ +# define CONFIG_CPU_FREQ_HZ 800000000 +#endif +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#define CONFIG_BAUDRATE 115200 - -/* XPSS Serial driver */ +/* Zynq Serial driver */ #define CONFIG_ZYNQ_SERIAL #define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000 #define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +/* DCC driver */ +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + /* Ethernet driver */ #define CONFIG_NET_MULTI #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM0 #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 -#define CONFIG_ZYNQ_SDHCI -#define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SPI +/* SPI */ +#ifdef CONFIG_ZYNQ_SPI +# define CONFIG_SPI_FLASH +# define CONFIG_SPI_FLASH_SST +# define CONFIG_CMD_SF +#endif + +/* NOR */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ZYNQ_SDHCI0 /* MMC */ #if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1) # define CONFIG_MMC @@ -48,7 +66,6 @@ #endif #define CONFIG_ZYNQ_I2C0 - /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C @@ -58,26 +75,6 @@ # define CONFIG_SYS_I2C_SLAVE 1 #endif -#if defined(CONFIG_ZYNQ_DCC) -# define CONFIG_ARM_DCC -# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ -#endif - -#define CONFIG_ZYNQ_SPI - -/* SPI */ -#ifdef CONFIG_ZYNQ_SPI -# define CONFIG_SPI_FLASH -# define CONFIG_SPI_FLASH_SST -# define CONFIG_CMD_SF -#endif - -/* Enable the PL to be downloaded */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA - #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY @@ -91,12 +88,9 @@ #define CONFIG_PHY_MARVELL /* Environment */ +#define CONFIG_ENV_SIZE 0x10000 /* Env. sector size */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_SYS_MALLOC_LEN 0x400000 +#define CONFIG_SYS_LOAD_ADDR 0 /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -111,8 +105,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LOAD_ADDR 0 - /* Physical Memory map */ #define CONFIG_SYS_TEXT_BASE 0 @@ -123,15 +115,25 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) +#define CONFIG_SYS_MALLOC_LEN 0x400000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -/* OF */ + +/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + +/* Open Firmware flat tree */ +#define CONFIG_OF_LIBFDT + +/* FIT support */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -#define CONFIG_OF_LIBFDT /* Boot FreeBSD/vxWorks from an ELF image */ #if defined(CONFIG_ZYNQ_BOOT_FREEBSD) -- 1.8.3

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[U-Boot] [PATCH 04/34] zynq: Cleanup on memory configs
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Cleanup on memory configuration options: - Add comment - Re-order configs Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index f9a071d..8ccc667 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -13,14 +13,6 @@ /* CPU clock */ #define CONFIG_CPU_FREQ_HZ 800000000 -/* Ram */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_TEXT_BASE 0 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} @@ -105,11 +97,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_MALLOC_LEN 0x400000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "zynq-uboot> " @@ -126,7 +113,21 @@ #define CONFIG_SYS_LOAD_ADDR 0 +/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) /* OF */ #define CONFIG_FIT #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ -- 1.8.3

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[U-Boot] [PATCH 02/34] zynq: Enable Boot FreeBSD/vxWorks
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

This enabled Boot FreeBSD/vxWorks from an ELF image support Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index a6dbd0e..6ac1350 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -130,6 +130,13 @@ #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT +/* Boot FreeBSD/vxWorks from an ELF image */ +#if defined(CONFIG_ZYNQ_BOOT_FREEBSD) +# define CONFIG_API +# define CONFIG_CMD_ELF +# define CONFIG_SYS_MMC_MAX_DEVICE 1 +#endif + /* Commands */ #include <config_cmd_default.h> -- 1.8.3

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[U-Boot] [PATCH 01/34] zynq: Enable CONFIG_FIT_VERBOSE
by Jagannadha Sutradharudu Teki 05 Nov '13

05 Nov '13

Enabled fit_format_{error,warning}() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- include/configs/zynq.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 4c6e6e8..a6dbd0e 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -127,6 +127,7 @@ /* OF */ #define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ #define CONFIG_OF_LIBFDT /* Commands */ -- 1.8.3

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