October 2013 - U-Boot

[U-Boot] [PATCH v2] Tegra114: Add support for more clock sources for T114 periphs
by Tom Warren 22 Jan '14

22 Jan '14

Some T114 peripherals can take up to 8 different clock sources (parents), including 4 new ones that don't exist on previous chips (PLLC2/C3/MEM2/SRC2). Expand clock/pll code/tables to support these additional bits/sources. Changes were made to some common code. Testing on T30/T20 showed no changes in periph clock sources/divisors. Also, peripheral clock sources that no longer exist on T114 were removed from the clock_periph_type table (CVE, TVDAC, etc.), and periphs that are gone or not needed in early init are no longer brought out of reset/enabled (FUSE, IRAMA/B/C/D, etc.). Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- v2: - Removed some periph enables/resets that are not needed for early init - Fixed an assert test for a divisor value (s/b >0, not >=0) - Remove some unused code arch/arm/cpu/arm720t/tegra114/cpu.c | 8 - arch/arm/cpu/tegra-common/clock.c | 21 +- arch/arm/cpu/tegra114-common/clock.c | 422 +++++++++++++--------- arch/arm/cpu/tegra30-common/clock.c | 6 - arch/arm/include/asm/arch-tegra/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra/clock.h | 17 + arch/arm/include/asm/arch-tegra114/clock-tables.h | 178 +++++---- 7 files changed, 390 insertions(+), 265 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 8f7bce4..c8e54b6 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -152,18 +152,11 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_CACHE2, 1); clock_set_enable(PERIPH_ID_GPIO, 1); clock_set_enable(PERIPH_ID_TMR, 1); - clock_set_enable(PERIPH_ID_RTC, 1); clock_set_enable(PERIPH_ID_CPU, 1); clock_set_enable(PERIPH_ID_EMC, 1); clock_set_enable(PERIPH_ID_I2C5, 1); - clock_set_enable(PERIPH_ID_FUSE, 1); - clock_set_enable(PERIPH_ID_PMC, 1); clock_set_enable(PERIPH_ID_APBDMA, 1); clock_set_enable(PERIPH_ID_MEM, 1); - clock_set_enable(PERIPH_ID_IRAMA, 1); - clock_set_enable(PERIPH_ID_IRAMB, 1); - clock_set_enable(PERIPH_ID_IRAMC, 1); - clock_set_enable(PERIPH_ID_IRAMD, 1); clock_set_enable(PERIPH_ID_CORESIGHT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_EMC1, 1); @@ -192,7 +185,6 @@ void t114_init_clocks(void) reset_set_enable(PERIPH_ID_COP, 0); reset_set_enable(PERIPH_ID_EMC, 0); reset_set_enable(PERIPH_ID_I2C5, 0); - reset_set_enable(PERIPH_ID_FUSE, 0); reset_set_enable(PERIPH_ID_APBDMA, 0); reset_set_enable(PERIPH_ID_MEM, 0); reset_set_enable(PERIPH_ID_CORESIGHT, 0); diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb91..62a2191 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -304,13 +304,24 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); - } else { + + switch (mux_bits) { + case MASK_BITS_31_30: clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, source << OUT_CLK_SOURCE_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE3_MASK, + source << OUT_CLK_SOURCE3_SHIFT); + break; + + case MASK_BITS_29_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, + source << OUT_CLK_SOURCE4_SHIFT); + break; } + udelay(2); return 0; } @@ -332,7 +343,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, if (extra_div) *extra_div = xdiv; - assert(divider >= 0); + assert(divider > 0); if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U; debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index e9a1a80..0626bcd 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -46,13 +46,22 @@ enum clock_type_id { CLOCK_TYPE_MCPT, CLOCK_TYPE_PCM, CLOCK_TYPE_PCMT, - CLOCK_TYPE_PCMT16, CLOCK_TYPE_PDCT, CLOCK_TYPE_ACPT, CLOCK_TYPE_ASPTE, CLOCK_TYPE_PMDACD2T, CLOCK_TYPE_PCST, + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + CLOCK_TYPE_COUNT, CLOCK_TYPE_NONE = -1, /* invalid clock type */ }; @@ -61,12 +70,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -92,9 +95,6 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), - CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_31_30}, { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, @@ -109,7 +109,45 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_29_28}, + + /* Additional clock types on T114 */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, }; /* @@ -122,110 +160,120 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), - TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), /* 0x08 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), /* 0x10 */ - TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_G3D, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_G2D, CLOCK_TYPE_MC2CC3P_A), /* 0x18 */ - TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */ - TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_EPP, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_MPE, CLOCK_TYPE_M), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), /* 0x20 */ - TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), /* 0x28 */ - TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), /* 0x30 */ - TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x38h */ /* Jumps to reg offset 0x3B0h */ - TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_G3D2, CLOCK_TYPE_MC2CC3P_A), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), - /* 0x40 */ - TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */ + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), - /* 0x48 */ + /* 0x50 */ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), - TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */ + TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x50 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */ + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), }; /* @@ -244,7 +292,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(COP), NONE(TRIGSYS), NONE(RESERVED3), - NONE(RTC), + NONE(RESERVED4), NONE(TMR), PERIPHC_UART1, PERIPHC_UART2, /* and vfir 0x68 */ @@ -252,7 +300,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 8 */ NONE(GPIO), PERIPHC_SDMMC2, - NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ + PERIPHC_SPDIF_IN, PERIPHC_I2S1, PERIPHC_I2C1, PERIPHC_NDFLASH, @@ -291,7 +339,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 40 */ NONE(KFUSE), - NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ + NONE(SBC1), /* SBC1, SPI1 */ PERIPHC_NOR, NONE(RESERVED43), PERIPHC_SBC2, @@ -301,16 +349,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 48 */ NONE(DSI), - PERIPHC_TVO, /* also CVE 0x40 */ - PERIPHC_MIPI, + NONE(RESERVED49), + PERIPHC_HSI, PERIPHC_HDMI, NONE(CSI), - PERIPHC_TVDAC, + NONE(RESERVED53), PERIPHC_I2C2, PERIPHC_UART3, /* 56 */ - NONE(RESERVED56), + NONE(MIPI_CAL), PERIPHC_EMC, NONE(USB2), NONE(USB3), @@ -320,7 +368,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(BSEV), /* Upper word 95:64 */ - PERIPHC_SPEEDO, + NONE(RESERVED64), PERIPHC_UART4, PERIPHC_UART5, PERIPHC_I2C3, @@ -335,41 +383,41 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(PCIEXCLK), NONE(AVPUCQ), NONE(RESERVED76), - NONE(RESERVED77), - NONE(RESERVED78), + NONE(TRACECLKIN), + NONE(SOC_THERM), NONE(DTV), /* 80 */ PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, NONE(DSIB), - NONE(RESERVED83), - NONE(IRAMA), - NONE(IRAMB), - NONE(IRAMC), - NONE(IRAMD), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), /* 88 */ - NONE(CRAM2), - NONE(RESERVED89), - NONE(MDOUBLER), - NONE(RESERVED91), - NONE(SUSOUT), + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), NONE(RESERVED93), NONE(RESERVED94), - NONE(RESERVED95), + NONE(XUSB_DEV), /* V word: 31:0 */ NONE(CPUG), NONE(CPULP), PERIPHC_G3D2, PERIPHC_MSELECT, - PERIPHC_TSENSOR, + NONE(V_RESERVED4), PERIPHC_I2S3, PERIPHC_I2S4, PERIPHC_I2C4, - /* 08 */ + /* 104 */ PERIPHC_SBC5, PERIPHC_SBC6, PERIPHC_AUDIO, @@ -379,63 +427,63 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { PERIPHC_DAM2, PERIPHC_HDA2CODEC2X, - /* 16 */ + /* 112 */ NONE(ATOMICS), - NONE(RESERVED17), - NONE(RESERVED18), - NONE(RESERVED19), - NONE(RESERVED20), - NONE(RESERVED21), - NONE(RESERVED22), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), PERIPHC_ACTMON, - /* 24 */ - NONE(RESERVED24), - NONE(RESERVED25), - NONE(RESERVED26), - NONE(RESERVED27), + /* 120 */ + NONE(V_RESERVED24), + NONE(V_RESERVED25), + NONE(V_RESERVED26), + NONE(V_RESERVED27), PERIPHC_SATA, PERIPHC_HDA, - NONE(RESERVED30), - NONE(RESERVED31), + NONE(V_RESERVED30), + NONE(V_RESERVED31), /* W word: 31:0 */ NONE(HDA2HDMICODEC), - NONE(RESERVED1_SATACOLD), - NONE(RESERVED2_PCIERX0), - NONE(RESERVED3_PCIERX1), - NONE(RESERVED4_PCIERX2), - NONE(RESERVED5_PCIERX3), - NONE(RESERVED6_PCIERX4), - NONE(RESERVED7_PCIERX5), - - /* 40 */ + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ NONE(CEC), - NONE(PCIE2_IOBIST), - NONE(EMC_IOBIST), - NONE(HDMI_IOBIST), - NONE(SATA_IOBIST), - NONE(MIPI_IOBIST), - NONE(EMC1_IOBIST), - NONE(XUSB), - - /* 48 */ - NONE(CILAB), - NONE(CILCD), - NONE(CILE), - NONE(DSIA_LP), - NONE(DSIB_LP), - NONE(RESERVED21_ENTROPY), - NONE(RESERVED22_W), - NONE(RESERVED23_W), - - /* 56 */ - NONE(RESERVED24_W), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(W_RESERVED22), + NONE(W_RESERVED23), + + /* 152 */ + NONE(W_RESERVED24), NONE(AMX0), NONE(ADX0), NONE(DVFS), NONE(XUSB_SS), - NONE(EMC_DLL), + NONE(W_RESERVED29), NONE(MC1), NONE(EMC1), }; @@ -510,7 +558,7 @@ int get_periph_clock_source(enum periph_id periph_id, *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - if (type == CLOCK_TYPE_PCMT16) + if (type == CLOCK_TYPE_PC2CC3M_T16) *divider_bits = 16; else *divider_bits = 8; @@ -583,21 +631,61 @@ enum periph_id clk_id_to_periph_id(int clk_id) switch (clk_id) { case PERIPH_ID_RESERVED3: + case PERIPH_ID_RESERVED4: case PERIPH_ID_RESERVED16: - case PERIPH_ID_RESERVED24: + case PERIPH_ID_RESERVED25: case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED39: case PERIPH_ID_RESERVED43: case PERIPH_ID_RESERVED45: - case PERIPH_ID_RESERVED56: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: case PERIPH_ID_RESERVED76: - case PERIPH_ID_RESERVED77: - case PERIPH_ID_RESERVED78: - case PERIPH_ID_RESERVED83: - case PERIPH_ID_RESERVED89: - case PERIPH_ID_RESERVED91: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: case PERIPH_ID_RESERVED93: case PERIPH_ID_RESERVED94: - case PERIPH_ID_RESERVED95: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_V_RESERVED24: + case PERIPH_ID_V_RESERVED25: + case PERIPH_ID_V_RESERVED26: + case PERIPH_ID_V_RESERVED27: + case PERIPH_ID_V_RESERVED30: + case PERIPH_ID_V_RESERVED31: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED22: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED24: + case PERIPH_ID_W_RESERVED29: return PERIPH_ID_NONE; default: return clk_id; diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 74bd22b..89c3529 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -60,12 +60,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index a4c17e7..8200090 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -243,6 +243,9 @@ enum { #define OUT_CLK_SOURCE_SHIFT 30 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE3_SHIFT 29 +#define OUT_CLK_SOURCE3_MASK (7U << OUT_CLK_SOURCE3_SHIFT) + #define OUT_CLK_SOURCE4_SHIFT 28 #define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..9495179 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -20,6 +20,12 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_COUNT, }; +enum { + MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ + MASK_BITS_31_29, + MASK_BITS_29_28, +}; + #include <asm/arch/clock-tables.h> /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -305,4 +311,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); /* SoC-specific TSC init */ void arch_timer_init(void); +/** + * Enable a peripheral clock with a certain clock source/divisor + * + * @param periph_id peripheral to enable/change + * @param src PLL id of required parent clock + * @param divisor required integer divisor (not 7.1) + * @return 0 if ok + * -1 on error (bad divisor, etc.). + */ +int clock_periph_enable(enum periph_id pid, int src, int divisor); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index d8fa0e1..19b8acf 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -40,7 +40,17 @@ enum clock_id { CLOCK_ID_OSC, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ + + /* + * These are clock ids that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + CLOCK_ID_NONE = -1, }; @@ -53,7 +63,7 @@ enum periph_id { PERIPH_ID_COP, PERIPH_ID_TRIGSYS, PERIPH_ID_RESERVED3, - PERIPH_ID_RTC, + PERIPH_ID_RESERVED4, PERIPH_ID_TMR, PERIPH_ID_UART1, PERIPH_ID_UART2, @@ -80,7 +90,7 @@ enum periph_id { /* 24 */ PERIPH_ID_3D, - PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, PERIPH_ID_DISP2, PERIPH_ID_DISP1, PERIPH_ID_HOST1X, @@ -93,10 +103,10 @@ enum periph_id { PERIPH_ID_AHBDMA, PERIPH_ID_APBDMA, PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, + PERIPH_ID_RESERVED36, PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, + PERIPH_ID_RESERVED38, + PERIPH_ID_RESERVED39, /* 40 */ PERIPH_ID_KFUSE, @@ -110,16 +120,16 @@ enum periph_id { /* 48 */ PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, PERIPH_ID_HDMI, PERIPH_ID_CSI, - PERIPH_ID_TVDAC, + PERIPH_ID_RESERVED53, PERIPH_ID_I2C2, PERIPH_ID_UART3, /* 56 */ - PERIPH_ID_RESERVED56, + PERIPH_ID_MIPI_CAL, PERIPH_ID_EMC, PERIPH_ID_USB2, PERIPH_ID_USB3, @@ -129,7 +139,7 @@ enum periph_id { PERIPH_ID_BSEV, /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_SPEEDO, + PERIPH_ID_RESERVED64, PERIPH_ID_UART4, PERIPH_ID_UART5, PERIPH_ID_I2C3, @@ -144,29 +154,29 @@ enum periph_id { PERIPH_ID_PCIEXCLK, PERIPH_ID_AVPUCQ, PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, PERIPH_ID_DTV, /* 80 */ PERIPH_ID_NANDSPEED, PERIPH_ID_I2CSLOW, PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, PERIPH_ID_RESERVED93, PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, + PERIPH_ID_XUSB_DEV, PERIPH_ID_VW_FIRST, /* V word: 31:0 */ @@ -174,7 +184,7 @@ enum periph_id { PERIPH_ID_CPULP, PERIPH_ID_3D2, PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, + PERIPH_ID_V_RESERVED4, PERIPH_ID_I2S3, PERIPH_ID_I2S4, PERIPH_ID_I2C4, @@ -191,61 +201,61 @@ enum periph_id { /* 112 */ PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, PERIPH_ID_ACTMON, /* 120 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, + PERIPH_ID_V_RESERVED24, + PERIPH_ID_V_RESERVED25, + PERIPH_ID_V_RESERVED26, + PERIPH_ID_V_RESERVED27, PERIPH_ID_SATA, PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, /* W word: 31:0 */ PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_RESERVED1_SATACOLD, - PERIPH_ID_RESERVED2_PCIERX0, - PERIPH_ID_RESERVED3_PCIERX1, - PERIPH_ID_RESERVED4_PCIERX2, - PERIPH_ID_RESERVED5_PCIERX3, - PERIPH_ID_RESERVED6_PCIERX4, - PERIPH_ID_RESERVED7_PCIERX5, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, /* 136 */ PERIPH_ID_CEC, - PERIPH_ID_PCIE2_IOBIST, - PERIPH_ID_EMC_IOBIST, - PERIPH_ID_HDMI_IOBIST, - PERIPH_ID_SATA_IOBIST, - PERIPH_ID_MIPI_IOBIST, - PERIPH_ID_EMC1_IOBIST, - PERIPH_ID_XUSB, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, /* 144 */ - PERIPH_ID_CILAB, - PERIPH_ID_CILCD, - PERIPH_ID_CILE, - PERIPH_ID_DSIA_LP, - PERIPH_ID_DSIB_LP, - PERIPH_ID_RESERVED21_ENTROPY, - PERIPH_ID_RESERVED22_W, - PERIPH_ID_RESERVED23_W, + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_W_RESERVED22, + PERIPH_ID_W_RESERVED23, /* 152 */ - PERIPH_ID_RESERVED24_W, + PERIPH_ID_W_RESERVED24, PERIPH_ID_AMX0, PERIPH_ID_ADX0, PERIPH_ID_DVFS, PERIPH_ID_XUSB_SS, - PERIPH_ID_EMC_DLL, + PERIPH_ID_W_RESERVED29, PERIPH_ID_MC1, PERIPH_ID_EMC1, @@ -290,7 +300,7 @@ enum periphc_internal_id { PERIPHC_DISP2, /* 0x10 */ - PERIPHC_CVE, + PERIPHC_10h, PERIPHC_11h, PERIPHC_VI, PERIPHC_13h, @@ -305,17 +315,17 @@ enum periphc_internal_id { PERIPHC_VFIR, PERIPHC_EPP, PERIPHC_MPE, - PERIPHC_MIPI, + PERIPHC_HSI, PERIPHC_UART1, PERIPHC_UART2, /* 0x20 */ PERIPHC_HOST1X, PERIPHC_21h, - PERIPHC_TVO, + PERIPHC_22h, PERIPHC_HDMI, PERIPHC_24h, - PERIPHC_TVDAC, + PERIPHC_25h, PERIPHC_I2C2, PERIPHC_EMC, @@ -337,10 +347,20 @@ enum periphc_internal_id { PERIPHC_NOR, PERIPHC_CSITE, PERIPHC_I2S0, - PERIPHC_37h, + PERIPHC_DTV, - PERIPHC_VW_FIRST, /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ PERIPHC_G3D2 = PERIPHC_VW_FIRST, PERIPHC_MSELECT, PERIPHC_TSENSOR, @@ -350,9 +370,9 @@ enum periphc_internal_id { PERIPHC_SBC5, PERIPHC_SBC6, - /* 0x40 */ + /* 0x48 */ PERIPHC_AUDIO, - PERIPHC_41h, + PERIPHC_49h, PERIPHC_DAM0, PERIPHC_DAM1, PERIPHC_DAM2, @@ -360,21 +380,21 @@ enum periphc_internal_id { PERIPHC_ACTMON, PERIPHC_EXTPERIPH1, - /* 0x48 */ + /* 0x50 */ PERIPHC_EXTPERIPH2, PERIPHC_EXTPERIPH3, PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, PERIPHC_SATAOOB, PERIPHC_SATA, PERIPHC_HDA, -- 1.8.1.5

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[U-Boot] Boot Linux kernel with initramfs fails
by Axel Lin 17 Jan '14

17 Jan '14

Hi, When I boot Linux kernel with FIT Image, the kernel does not unpacking initramfs. ( The root cause is "initrd_start is NULL".) The initramfs is built-in with kernel, so I don't specify ramdisk in my kernel.its file. Is this a known issue or do I need special setting to boot a Linux kernel with initramfs? BTW, bootm shows below messages: => bootm ## Loading kernel from FIT Image at 00400000 ... Using 'conf@1' configuration Trying 'kernel@1' kernel subimage Description: kernel Type: Kernel Image Compression: uncompressed Data Start: 0x004000e8 Data Size: 2496848 Bytes = 2.4 MiB Architecture: ARM OS: Linux Load Address: 0x00000000 Entry Point: 0x00000000 Verifying Hash Integrity ... OK ## Loading fdt from FIT Image at 00400000 ... Using 'conf@1' configuration Trying 'fdt@1' fdt subimage Description: gpl327xx.dtb Type: Flat Device Tree Compression: uncompressed Data Start: 0x00661ae8 Data Size: 2174 Bytes = 2.1 KiB Architecture: ARM Hash algo: sha1 Hash value: 674b5443523a23ad8de49b161932fd3a1d7f90ea Verifying Hash Integrity ... sha1+ OK Booting using the fdt blob at 0x661ae8 Loading Kernel Image ... OK ## initrd_high = 0xffffffff, copy_to_ram = 1 ramdisk load start = 0x00000000, ramdisk load end = 0x00000000 Loading Device Tree to 019b4000, end 019b787d ... OK Below is part of my boot messages: NET: Registered protocol family 1 BEGIN::: populate_rootfs... ^^^ My debug message, so I know populate_rootfs() is executed. populate_rootfs... initrd_start is NULL ^^^ My debug message, I got "initrd_start is NULL". That is why the initramfs is not unpack. ROMFS MTD (C) 2007 Red Hat, Inc. io scheduler noop registered (default) TCP: cubic registered NET: Registered protocol family 10 sit: IPv6 over IPv4 tunneling driver Warning: unable to open an initial console. VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6 Please append a correct "root=" boot option; here are the available partitions: Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.0-rc1-00018-g16fc5bc-dirty #131 [<0000bda8>] (unwind_backtrace+0x0/0xf0) from [<0000ac0c>] (show_stack+0x10/0x14) [<0000ac0c>] (show_stack+0x10/0x14) from [<001fcff8>] (panic+0x7c/0x1c4) [<001fcff8>] (panic+0x7c/0x1c4) from [<0026ddb4>] (mount_block_root+0x1f4/0x2b4) [<0026ddb4>] (mount_block_root+0x1f4/0x2b4) from [<0026e000>] (prepare_namespace+0x128/0x18c) [<0026e000>] (prepare_namespace+0x128/0x18c) from [<0026da74>] (kernel_init_freeable+0x164/0x1a8) [<0026da74>] (kernel_init_freeable+0x164/0x1a8) from [<001fb808>] (kernel_init+0x8/0xe4) [<001fb808>] (kernel_init+0x8/0xe4) from [<00008f70>] (ret_from_fork+0x14/0x24) (Test on latest u-boot git tree.) Regards, Axel

3 3

[U-Boot] [PATCH] cmd_sf: Mention in the help text that mode, addr, offset and len must be given in hex.
by Jakob Unterwurzacher 08 Jan '14

08 Jan '14

These parameters are always interpreted as hex, even without 0x prefix. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher(a)theobroma-systems.com> --- common/cmd_sf.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 0a17782..0f7c0a3 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -531,6 +531,7 @@ U_BOOT_CMD( "sf erase offset [+]len - erase `len' bytes from `offset'\n" " `+len' round up `len' to block size\n" "sf update addr offset len - erase and write `len' bytes from memory\n" - " at `addr' to flash at `offset'" + " at `addr' to flash at `offset'\n" + "Parameters mode, addr, offset and len must be in hex." SF_TEST_HELP ); -- 1.7.2.5

2 1

[U-Boot] [PATCH] spi: soft_spi: Support NULL din/dout buffers
by Andrew Ruder 08 Jan '14

08 Jan '14

This mirrors the conventions used in other SPI drivers (kirkwood, davinci, atmel, et al) where the din/dout buffer can be NULL when the received/transmitted data isn't important. This reduces the need for allocating additional buffers when write-only/read-only functionality is needed. In the din == NULL case, the received data is simply not stored. In the dout == NULL case, zeroes are transmitted. Signed-off-by: Andrew Ruder <andrew.ruder(a)elecsyscorp.com> --- drivers/spi/soft_spi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 5d22351..5fdd091 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -137,9 +137,15 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * Check if it is time to work on a new byte. */ if((j % 8) == 0) { - tmpdout = *txd++; + if (txd) { + tmpdout = *txd++; + } else { + tmpdout = 0; + } if(j != 0) { - *rxd++ = tmpdin; + if (rxd) { + *rxd++ = tmpdin; + } } tmpdin = 0; } @@ -164,9 +170,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, * bits over to left-justify them. Then store the last byte * read in. */ - if((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; + if (rxd) { + if((bitlen % 8) != 0) + tmpdin <<= 8 - (bitlen % 8); + *rxd++ = tmpdin; + } if (flags & SPI_XFER_END) spi_cs_deactivate(slave); -- 1.8.4.rc3

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[U-Boot] [PATCH] Fix problems in chip select selection in imx23, 28 spi code
by Asok Subramanian 08 Jan '14

08 Jan '14

Fix problems in chip select selection in imx23,28 spi code The spi function code for imx23,28 currently does not work for chip select other than 0. This is because the register HW_SSP_CTRL0 is first reset and the code does not load the CS bits again into HW_SSP_CTRL0 after the reset. The proposed fix reloads the CS bits after the reset. Signed-off-by: Asok Subramanian <asok at vyassoft.com> --- drivers/spi/mxs_spi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 3cf7142..15681dc 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -32,6 +32,7 @@ struct mxs_spi_slave { uint32_t max_khz; uint32_t mode; struct mxs_ssp_regs *regs; + unsigned int cs; }; static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) @@ -74,6 +75,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxs_slave->max_khz = max_hz / 1000; mxs_slave->mode = mode; mxs_slave->regs = mxs_ssp_regs_by_bus(bus); + mxs_slave->cs = cs; ssp_regs = mxs_slave->regs; reg = readl(&ssp_regs->hw_ssp_ctrl0); @@ -102,7 +104,7 @@ int spi_claim_bus(struct spi_slave *slave) mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0); + writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT | (mxs_slave->cs) << MXS_SSP_CHIPSELECT_SHIFT, &ssp_regs->hw_ssp_ctrl0); reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; -- 1.7.9.5

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[U-Boot] [PATCH] Add code for spi half duplex operation for enc28j60
by Asok Subramanian 08 Jan '14

08 Jan '14

Add code for spi half duplex operation for enc28j60 The current code assumes full duplex spi operation. But there are processors like imx23 which only permit half duplex operation. This fix does half duplex operation based on the definition of CONFIG_SPI_HALF_DUPLEX Signed-off-by: Asok Subramanian <asok at vyassoft.com> --- drivers/net/enc28j60.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index ec33764..753fe26 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -157,9 +157,17 @@ static u8 enc_r8(enc_dev_t *enc, const u16 reg) enc_set_bank(enc, reg); dout[0] = CMD_RCR(reg); +#ifndef CONFIG_SPI_HALF_DUPLEX spi_xfer(enc->slave, nbytes * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); return din[nbytes-1]; +#else + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + return din[0]; +#endif } /* @@ -175,6 +183,7 @@ static u16 enc_r16(enc_dev_t *enc, const u16 reg) enc_set_bank(enc, reg); dout[0] = CMD_RCR(reg); +#ifndef CONFIG_SPI_HALF_DUPLEX spi_xfer(enc->slave, nbytes * 8, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); result = din[nbytes-1]; @@ -183,6 +192,20 @@ static u16 enc_r16(enc_dev_t *enc, const u16 reg) SPI_XFER_BEGIN | SPI_XFER_END); result |= din[nbytes-1] << 8; return result; +#else + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + result = din[0]; + dout[0]++; /* next register */ + spi_xfer(enc->slave, (nbytes -1) * 8, dout, NULL, + SPI_XFER_BEGIN ); + spi_xfer(enc->slave, 8, NULL, din, + SPI_XFER_END ); + result |= din[0] << 8; + return result; +#endif } /* -- 1.7.9.5

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[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
by Armando Visconti 08 Jan '14

08 Jan '14

This patch adds the support for the ARM PL022 SPI controller for the standard variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO. Signed-off-by: Armando Visconti <armando.visconti(a)st.com> Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Acked-by: Stefan Roese <sr(a)denx.de> --- v5->v6 1. Make use of spi_alloc_slave() macro. 2. Changed the identation on 'if statement' as requested by Jagan. drivers/spi/Makefile | 1 + drivers/spi/pl022_spi.c | 308 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 drivers/spi/pl022_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d08609e..b6443b1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o +COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..5b47413 --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,308 @@ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c + * by Atmel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* SSP registers mapping */ +struct pl022 { + u32 ssp_cr0; /* 0x000 */ + u32 ssp_cr1; /* 0x004 */ + u32 ssp_dr; /* 0x008 */ + u32 ssp_sr; /* 0x00c */ + u32 ssp_cpsr; /* 0x010 */ + u32 ssp_imsc; /* 0x014 */ + u32 ssp_ris; /* 0x018 */ + u32 ssp_mis; /* 0x01c */ + u32 ssp_icr; /* 0x020 */ + u32 ssp_dmacr; /* 0x024 */ + u8 reserved_1[0x080 - 0x028]; + u32 ssp_itcr; /* 0x080 */ + u32 ssp_itip; /* 0x084 */ + u32 ssp_itop; /* 0x088 */ + u32 ssp_tdr; /* 0x08c */ + u8 reserved_2[0xFE0 - 0x090]; + u32 ssp_pid0; /* 0xfe0 */ + u32 ssp_pid1; /* 0xfe4 */ + u32 ssp_pid2; /* 0xfe8 */ + u32 ssp_pid3; /* 0xfec */ + u32 ssp_cid0; /* 0xff0 */ + u32 ssp_cid1; /* 0xff4 */ + u32 ssp_cid2; /* 0xff8 */ + u32 ssp_cid3; /* 0xffc */ +}; + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_8BIT_MODE (0x07) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 + +/* SSP Control Register 0 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MAX (0xFE) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + struct spi_slave slave; + void *regs; + unsigned int freq; +}; + +static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave *slave) +{ + return container_of(slave, struct pl022_spi_slave, slave); +} + +/* + * Following three functions should be provided by the + * board support package. + */ +int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void __weak spi_cs_activate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void __weak spi_cs_deactivate(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_init(void) +{ + /* do nothing */ +} + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* PL022 version is 0x00041022 */ + if ((readl(&pl022->ssp_pid0) == 0x22) && + (readl(&pl022->ssp_pid1) == 0x10) && + ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && + (readl(&pl022->ssp_pid3) == 0x00)) + return 1; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct pl022_spi_slave *ps; + struct pl022 *pl022; + u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ps = spi_alloc_slave(struct pl022_spi_slave, bus, cs); + if (!ps) + return NULL; + + ps->freq = max_hz; + + switch (bus) { + case 0: + ps->regs = (void *)CONFIG_SYS_SPI_BASE; + break; +#ifdef CONFIG_SYS_SPI_BASE1 + case 1: + ps->regs = (void *)CONFIG_SYS_SPI_BASE1; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE2 + case 2: + ps->regs = (void *)CONFIG_SYS_SPI_BASE2; + break; +#endif +#ifdef CONFIG_SYS_SPI_BASE3 + case 3: + ps->regs = (void *)CONFIG_SYS_SPI_BASE3; + break; +#endif + default: + free(ps); + return NULL; + } + + pl022 = (struct pl022 *)ps->regs; + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) { + free(ps); + return NULL; + } + + /* Set requested polarity and 8bit mode */ + cr0 = SSP_CR0_8BIT_MODE; + cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; + cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; + + writel(cr0, &pl022->ssp_cr0); + + /* Program the SSPClk frequency */ + prescaler = CONFIG_SYS_SPI_CLK / ps->freq; + + if (prescaler <= 0xFF) { + cpsr = prescaler; + } else { + for (scr = 1; scr <= SSP_SCR_MAX; scr++) { + if (!(prescaler % scr)) { + cpsr = prescaler / scr; + if (cpsr <= SSP_CPSR_MAX) + break; + } + } + + if (scr > SSP_SCR_MAX) { + scr = SSP_SCR_MAX; + cpsr = prescaler / scr; + cpsr &= SSP_CPSR_MAX; + } + } + + if (cpsr & 0x1) + cpsr++; + + writel(cpsr, &pl022->ssp_cpsr); + cr0 = readl(&pl022->ssp_cr0); + writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); + + return &ps->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + + free(ps); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Enable the SPI hardware */ + setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + + /* Disable the SPI hardware */ + writel(0x0, &pl022->ssp_cr1); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct pl022_spi_slave *ps = to_pl022_spi(slave); + struct pl022 *pl022 = (struct pl022 *)ps->regs; + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + ret = -1; + + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (len_tx < len) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { + value = (txp != NULL) ? *txp++ : 0; + writel(value, &pl022->ssp_dr); + len_tx++; + } + + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { + value = readl(&pl022->ssp_dr); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} -- 1.7.11.7

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[U-Boot] [PATCH 0/8] Secure boot improvements and test on Beaglebone Black
by Simon Glass 08 Jan '14

08 Jan '14

This series adds a few improvements to the image signing feature to make it easier to use on the Beaglebone Black. - Add a DEV_TREE_BIN option to make it easier to include the correct FDT (with embedded public keys) into the U-Boot image - Enable cache for more TI boards (to speed things up) - Increase malloc size - Enable CONFIG_OF_CONTROL, FIT and secure boot on am33xx/omap (RFC only, not sure we want this, although we could create a separate config for it) I also have a change to adjust mkimage to automatically make space in the FDT when adding hashes and signatures. Included here is the ENOSPC patch, but the fit_image.c patch will wait until the dumpimage tool is merged, since I am changing the same code. With this, secure boot was tested successfully on Beaglebone Black. Simon Glass (8): am33xx/omap: Allow cache enable for all Sitara/OMAP hash: Export functions to find and show hash fdt: Add DEV_TREE_BIN option to specify a device tree binary file fdt: Update functions which write to an FDT to return -ENOSPC arm: ti: Increase malloc size to 16MB for armv7 boards RFC: am33xx/omap: Enable CONFIG_OF_CONTROL RFC: am33xx/omap: Enable FIT support RFC: am33xx/omap: Enable secure boot with CONFIG_FIT_SIGNATURE Makefile | 8 +- arch/arm/cpu/armv7/omap-common/Makefile | 4 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 41 -- arch/arm/cpu/armv7/omap-common/omap-cache.c | 56 +++ arch/arm/cpu/armv7/omap3/board.c | 8 - arch/arm/dts/am33xx.dtsi | 649 +++++++++++++++++++++++++ arch/arm/dts/dt-bindings/gpio/gpio.h | 15 + arch/arm/dts/dt-bindings/pinctrl/am33xx.h | 41 ++ arch/arm/dts/dt-bindings/pinctrl/omap.h | 54 ++ board/siemens/common/board.c | 9 - board/ti/dts/am335x-bone-common.dtsi | 262 ++++++++++ board/ti/dts/am335x-boneblack.dts | 17 + board/ti/dts/tps65217.dtsi | 56 +++ common/hash.c | 13 +- common/image-fit.c | 4 +- doc/README.fdt-control | 16 +- include/configs/am335x_evm.h | 9 + include/configs/ti_armv7_common.h | 2 +- include/hash.h | 22 + include/rsa.h | 3 +- lib/rsa/rsa-sign.c | 28 +- 21 files changed, 1236 insertions(+), 81 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/omap-cache.c create mode 100644 arch/arm/dts/am33xx.dtsi create mode 100644 arch/arm/dts/dt-bindings/gpio/gpio.h create mode 100644 arch/arm/dts/dt-bindings/pinctrl/am33xx.h create mode 100644 arch/arm/dts/dt-bindings/pinctrl/omap.h create mode 100644 board/ti/dts/am335x-bone-common.dtsi create mode 100644 board/ti/dts/am335x-boneblack.dts create mode 100644 board/ti/dts/tps65217.dtsi -- 1.8.4

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[U-Boot] [PATCH v2] exynos5250: remove redundant SPI and PMIC related configs
by Inderpal Singh 07 Jan '14

07 Jan '14

They have been defined once already. Hence remove the redundant definitions. Signed-off-by: Inderpal Singh <inderpal.singh(a)linaro.org> --- v1 was posted as the first patch of [1] Changes in v2: - split from the patchset at [1] - removed redundant configs for PMIC - rebased to latest u-boot-samsung master branch [1] http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/157101 include/configs/exynos5250-dt.h | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 62b83d4..03b07b2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -246,11 +246,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_I2C_EDID -/* PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_I2C -#define CONFIG_PMIC_MAX77686 - /* SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -278,27 +273,6 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX77686 -/* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH - -#ifdef CONFIG_SPI_FLASH -#define CONFIG_EXYNOS_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_SF_DEFAULT_SPEED 50000000 -#define EXYNOS5_SPI_NUM_CONTROLLERS 5 -#endif - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X -- 1.7.9.5

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[U-Boot] [PATCH 0/4] Add support for TI TPS65090
by Simon Glass 02 Jan '14

02 Jan '14

This series adds support for the TPS65090 PMIC as used on the Samsung ARM Chromebook. It is plumbed into smdk5250 for now, while we await the exynos5-dt board being applied upstream. Aaron Durbin (3): exynos5: Enable tps65090 on smdk5250 power: Explicitly select pmic device's bus exynos5: support tps65090 pmic Tom Wai-Hong Tam (1): power: Add support for TPS65090 PMU chip. board/samsung/smdk5250/smdk5250.c | 33 +++- doc/device-tree-bindings/power/tps65090.txt | 21 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_tps65090.c | 296 ++++++++++++++++++++++++++++ drivers/power/power_i2c.c | 4 + include/configs/exynos5250-dt.h | 1 + include/fdtdec.h | 1 + include/power/tps65090_pmic.h | 83 ++++++++ lib/fdtdec.c | 1 + 9 files changed, 433 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/power/tps65090.txt create mode 100644 drivers/power/pmic/pmic_tps65090.c create mode 100644 include/power/tps65090_pmic.h -- 1.8.1.3

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