October 2013 - U-Boot

[U-Boot] [PATCH] Add support for SX151x SPI GPIO Expanders
by Viktar Palstsiuk 30 Oct '13

30 Oct '13

Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk(a)promwad.com> --- drivers/gpio/Makefile | 1 + drivers/gpio/sx151x.c | 255 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/sx151x.h | 30 ++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/gpio/sx151x.c create mode 100644 include/sx151x.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 71ddb00..9f13342 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o COBJS-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o COBJS-$(CONFIG_ADI_GPIO2) += adi_gpio2.o COBJS-$(CONFIG_TCA642X) += tca642x.o +COBJS-$(CONFIG_SX151X) += sx151x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/sx151x.c b/drivers/gpio/sx151x.c new file mode 100644 index 0000000..06a5758 --- /dev/null +++ b/drivers/gpio/sx151x.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2013 + * Viktar Palstsiuk, Promwad, viktar.palstsiuk(a)promwad.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for Semtech SX151x SPI GPIO Expanders + */ + +#include <common.h> +#include <spi.h> +#include <sx151x.h> + +#ifndef CONFIG_SX151X_SPI_BUS +#define CONFIG_SX151X_SPI_BUS 0 +#endif + +/* + * The SX151x registers + */ + +#ifdef CONFIG_SX151X_GPIO_COUNT_8 +/* 8bit: SX1511 */ +#define SX151X_REG_DIR 0x07 +#define SX151X_REG_DATA 0x08 +#else +/* 16bit: SX1512 */ +#define SX151X_REG_DIR 0x0F +#define SX151X_REG_DATA 0x11 +#endif +#define SX151X_REG_RESET 0x7D + +static int sx151x_spi_write(int chip, unsigned char reg, unsigned char val) +{ + struct spi_slave *slave; + unsigned char buf[2]; + int ret; + + slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000, + SPI_MODE_0); + if (!slave) + return 0; + + spi_claim_bus(slave); + + buf[0] = reg; + buf[1] = val; + + ret = spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + if (ret < 0) + printf("spi%d.%d write fail: can't write %02x to %02x: %d\n", + CONFIG_SX151X_SPI_BUS, chip, val, reg, ret); + else + printf("spi%d.%d write 0x%02x to register 0x%02x\n", + CONFIG_SX151X_SPI_BUS, chip, val, reg); + spi_release_bus(slave); + spi_free_slave(slave); + + return ret; +} + +static int sx151x_spi_read(int chip, unsigned char reg) +{ + struct spi_slave *slave; + int ret; + + slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000, + SPI_MODE_0); + if (!slave) + return 0; + + spi_claim_bus(slave); + + ret = spi_w8r8(slave, reg | 0x80); + if (ret < 0) + printf("spi%d.%d read fail: can't read %02x: %d\n", + CONFIG_SX151X_SPI_BUS, chip, reg, ret); + else + printf("spi%d.%d read register 0x%02x: 0x%02x\n", + CONFIG_SX151X_SPI_BUS, chip, reg, ret); + + spi_release_bus(slave); + spi_free_slave(slave); + + return ret; +} + +static inline void sx151x_find_cfg(int gpio, unsigned char *reg, unsigned char *mask) +{ + *reg -= gpio / 8; + *mask = 1 << (gpio % 8); +} + +static s32 sx151x_write_cfg(int chip, unsigned char gpio, unsigned char reg, int val) +{ + unsigned char mask; + unsigned char data; + int ret; + + sx151x_find_cfg(gpio, &reg, &mask); + ret = sx151x_spi_read(chip, reg); + if (ret < 0) + return ret; + else + data = ret; + data &= ~mask; + data |= (val << (gpio % 8)) & mask; + return sx151x_spi_write(chip, reg, data); +} + +int sx151x_get_value(int chip, int gpio) +{ + u8 reg = SX151X_REG_DATA; + u8 mask; + s32 ret; + + sx151x_find_cfg(gpio, &reg, &mask); + ret = sx151x_spi_read(chip, reg); + if (ret >= 0) + ret = (ret & mask) != 0 ? 1 : 0; + + return ret; +} + +int sx151x_set_value(int chip, int gpio, int val) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DATA, (val ? 1 : 0)); +} + +int sx151x_direction_input(int chip, int gpio) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 1); +} + +int sx151x_direction_output(int chip, int gpio) +{ + return sx151x_write_cfg(chip, gpio, SX151X_REG_DIR, 0); +} + +int sx151x_reset(int chip) +{ + int err; + + err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x12); + if (err < 0) + return err; + + err = sx151x_spi_write(chip, SX151X_REG_RESET, 0x34); + return err; +} + +#ifdef CONFIG_CMD_SX151X + +int do_sx151x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret = CMD_RET_USAGE, chip = 0, gpio = 0, val = 0; + + if (argc < 3) + return CMD_RET_USAGE; + + /* arg2 used as chip number */ + chip = simple_strtoul(argv[2], NULL, 10); + + if (strcmp(argv[1], "reset") == 0) { + ret = sx151x_reset(chip); + if (!ret) { + printf("Device at spi%d.%d was reset\n", + CONFIG_SX151X_SPI_BUS, chip); + } + return ret; + } + + if (argc < 4) + return CMD_RET_USAGE; + + /* arg3 used as gpio number */ + gpio = simple_strtoul(argv[3], NULL, 10); + + if (strcmp(argv[1], "get") == 0) { + ret = sx151x_get_value(chip, gpio); + if (ret < 0) + printf("Failed to get value at spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else { + printf("Value at spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, ret); + ret = 0; + } + return ret; + } + + if (argc < 5) + return CMD_RET_USAGE; + + /* arg4 used as value or direction */ + val = simple_strtoul(argv[4], NULL, 10); + + if (strcmp(argv[1], "set") == 0) { + ret = sx151x_set_value(chip, gpio, val); + if (ret < 0) + printf("Failed to set value at spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else + printf("New value at spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, val); + return ret; + } else if (strcmp(argv[1], "dir") == 0) { + if (val == 0) + ret = sx151x_direction_output(chip, gpio); + else + ret = sx151x_direction_input(chip, gpio); + + if (ret < 0) + printf("Failed to set direction of spi%d.%d gpio %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio); + else + printf("New direction of spi%d.%d gpio %d is %d\n", + CONFIG_SX151X_SPI_BUS, chip, gpio, val); + return ret; + } + + printf("Please see usage\n"); + + return ret; +} + +U_BOOT_CMD( + sx151x, 5, 1, do_sx151x, + "sx151x gpio access", + "dir chip gpio 0|1\n" + " - set gpio direction (0 for output, 1 for input)\n" + "sx151x get chip gpio\n" + " - get gpio value\n" + "sx151x set chip gpio 0|1\n" + " - set gpio value\n" + "sx151x reset chip\n" + " - reset chip" +); + +#endif /* CONFIG_CMD_SX151X */ diff --git a/include/sx151x.h b/include/sx151x.h new file mode 100644 index 0000000..603f468 --- /dev/null +++ b/include/sx151x.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2013 + * Viktar Palstsiuk, Promwad, viktar.palstsiuk(a)promwad.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SX151X_H_ +#define __SX151X_H_ + +int sx151x_get_value(int chip, int gpio); +int sx151x_set_value(int chip, int gpio, int val); +int sx151x_direction_input(int chip, int gpio); +int sx151x_direction_output(int chip, int gpio); +int sx151x_reset(int chip); + +#endif /* __SX151X_H_ */ -- 1.8.4.rc3

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[U-Boot] [PATCH v2 0/2] ARM: tegra: Add the Tamonten-NG Evaluation carrier boards
by Alban Bedel 30 Oct '13

30 Oct '13

Hi all, This new serie has been rebased on the current master from denx and the SKU 0xb1 names has been changed to SKU_ID_TM30MQS_A3 to better reflect nvidia's internal namming. Alban Bedel (2): ARM: tegra: support SKU b1 of Tegra30 ARM: tegra: Add the Tamonten™ NG Evaluation Carrier board arch/arm/cpu/tegra-common/ap.c | 1 + arch/arm/include/asm/arch-tegra/tegra.h | 1 + .../common/pinmux-config-tamonten-ng.h | 385 +++++++++++++++++++++ board/avionic-design/common/tamonten-ng.c | 129 +++++++ board/avionic-design/dts/tegra30-tamonten.dtsi | 74 ++++ board/avionic-design/dts/tegra30-tec-ng.dts | 8 + board/avionic-design/tec-ng/Makefile | 32 ++ boards.cfg | 1 + include/configs/tec-ng.h | 84 +++++ 9 files changed, 715 insertions(+) create mode 100644 board/avionic-design/common/pinmux-config-tamonten-ng.h create mode 100644 board/avionic-design/common/tamonten-ng.c create mode 100644 board/avionic-design/dts/tegra30-tamonten.dtsi create mode 100644 board/avionic-design/dts/tegra30-tec-ng.dts create mode 100644 board/avionic-design/tec-ng/Makefile create mode 100644 include/configs/tec-ng.h -- 1.8.4

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[U-Boot] [PATCH 1/2] arm: zynq: Do not remap OCM to high address
by Michal Simek 30 Oct '13

30 Oct '13

In case where ps-ddr is not used, do not remap OCM to high address and keep it from 0x0. Linux SMP requires to have memory at 0x0. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv7/zynq/cpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 2bb3843..0ca5d8a 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -16,13 +16,15 @@ void lowlevel_init(void) int arch_cpu_init(void) { zynq_slcr_unlock(); - /* remap DDR to zero, FILTERSTART */ - writel(0, &scu_base->filter_start); /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); +#if (CONFIG_SYS_SDRAM_BASE == 0) + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ writel(0x1F, &slcr_base->ocm_cfg); /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ @@ -33,6 +35,7 @@ int arch_cpu_init(void) writel(0x0, &slcr_base->ddr_urgent_sel); /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); +#endif zynq_slcr_lock(); -- 1.8.2.3

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[U-Boot] [U-boot] DFU and fastboot question
by TigerLiu＠viatech.com.cn 30 Oct '13

30 Oct '13

Hi, experts: In U-boot mini summit 2013, not talk about android fastboot protocol support in U-boot mainline code? In the ppt which introduced DFU, it said: Google Chromebook use DFU tool? I am curious: Why Google not continue to use fastboot tool in Chromebook? Best wishes,

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[U-Boot] [PATCH] video, formike: change tag/val write
by Heiko Schocher 30 Oct '13

30 Oct '13

write first the "tag" 8 bit value and then the "val" 8-bit to the display. Tested on the rut board. Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/formike.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/video/formike.c b/drivers/video/formike.c index b9b6822..1383158 100644 --- a/drivers/video/formike.c +++ b/drivers/video/formike.c @@ -27,10 +27,11 @@ static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, int ret; buf[0] = tag; - buf[1] = val; - flags |= SPI_XFER_END; + ret = spi_xfer(spi, 8, buf, NULL, flags); + buf[0] = val; + flags = SPI_XFER_END; + ret = spi_xfer(spi, 8, buf, NULL, flags); - ret = spi_xfer(spi, 16, buf, NULL, flags); #ifdef KWH043ST20_F01_SPI_DEBUG printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", tag, val, ret); -- 1.8.3.1

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[U-Boot] [PATCH] video, cfb_console: make background and foreground color configurable
by Heiko Schocher 30 Oct '13

30 Oct '13

make CONSOLE_BG_COL/CONSOLE_FG_COL configurable through board config file. Clear video screen in video_init(). Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> --- README | 5 +++++ drivers/video/cfb_console.c | 38 ++++++++++++++++++++------------------ include/video_fb.h | 5 +++++ 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/README b/README index e6e0465..232c96a 100644 --- a/README +++ b/README @@ -705,6 +705,11 @@ The following options need to be configured: the "silent" environment variable. See doc/README.silent for more information. + CONFIG_SYS_CONSOLE_BG_COL: define the backgroundcolor, default + is 0x00. + CONFIG_SYS_CONSOLE_FG_COL: define the foregroundcolor, default + is 0xa0. + - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index a2946c7..6db4073 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -2108,6 +2108,24 @@ defined(CONFIG_SANDBOX) || defined(CONFIG_X86) return 0; } +void video_clear(void) +{ + if (!video_fb_address) + return; +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + 0, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS, /* frame height */ + bgx /* fill color */ + ); +#else + memsetl(video_fb_address, + (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); +#endif +} + static int video_init(void) { unsigned char color8; @@ -2194,6 +2212,8 @@ static int video_init(void) } eorx = fgx ^ bgx; + video_clear(); + #ifdef CONFIG_VIDEO_LOGO /* Plot the logo and get start point of console */ debug("Video: Drawing the logo ...\n"); @@ -2297,21 +2317,3 @@ int video_get_screen_columns(void) { return CONSOLE_COLS; } - -void video_clear(void) -{ - if (!video_fb_address) - return; -#ifdef VIDEO_HW_RECTFILL - video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ - 0, /* dest pos x */ - 0, /* dest pos y */ - VIDEO_VISIBLE_COLS, /* frame width */ - VIDEO_VISIBLE_ROWS, /* frame height */ - bgx /* fill color */ - ); -#else - memsetl(video_fb_address, - (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); -#endif -} diff --git a/include/video_fb.h b/include/video_fb.h index 028e2a6..6cd4e37 100644 --- a/include/video_fb.h +++ b/include/video_fb.h @@ -18,8 +18,13 @@ #ifndef _VIDEO_FB_H_ #define _VIDEO_FB_H_ +#if defined(CONFIG_SYS_CONSOLE_FG_COL) && defined(CONFIG_SYS_CONSOLE_BG_COL) +#define CONSOLE_BG_COL CONFIG_SYS_CONSOLE_BG_COL +#define CONSOLE_FG_COL CONFIG_SYS_CONSOLE_FG_COL +#else #define CONSOLE_BG_COL 0x00 #define CONSOLE_FG_COL 0xa0 +#endif /* * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT -- 1.8.3.1

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[U-Boot] [PATCH] video: ipu_disp: Fix clock polarity logic
by Fabio Estevam 30 Oct '13

30 Oct '13

Currently the HDMI splash screen image quality on mx6solo does not show a very stable image. By comparing the IPU driver from U-boot with the one from FSL 4.1.0 BSP, we can see that there is an inverted logic for setting the DI_GEN_POL_CLK bit. >From FSL BSP [1] we have: if (!sig.clk_pol) di_gen |= DI_GEN_POLARITY_DISP_CLK; Applying the same logic into U-boot fixes the HDMI image stability. [1] git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/ipu3/… Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- drivers/video/ipu_disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index 2e91356..22ac142 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -1178,7 +1178,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, if (sig.Vsync_pol) di_gen |= DI_GEN_POLARITY_3; - if (sig.clk_pol) + if (!sig.clk_pol) di_gen |= DI_GEN_POL_CLK; } -- 1.8.1.2

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[U-Boot] [PATCH 1/2] powerpc: spiflash:Add corenet devices support in eSPI SPL
by Priyanka Jain 30 Oct '13

30 Oct '13

Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- drivers/mtd/spi/fsl_espi_spl.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 6263d8c..e5ac79b 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -31,6 +31,10 @@ void spi_boot(void) hang(); } +#ifdef CONFIG_FSL_CORENET + offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; +#else /* * Load U-Boot image from SPI flash into RAM */ @@ -50,6 +54,7 @@ void spi_boot(void) code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ code_len = code_len - CONFIG_SPL_MAX_SIZE; +#endif /* copy code to DDR */ spi_flash_read(flash, offset, code_len, (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST); -- 1.7.4.1

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[U-Boot] [PATCH 1/2] esdhc: memset mmc struct before putting into use
by Haijun Zhang 30 Oct '13

30 Oct '13

struct mmc should be clear to all '0' after malloc to avoid unexpect variable value. Like mmc->has_init = xxx. In this case mmcinfo will believe the card had been initialized before and skip the initialization. Test on P5040 and T4240, Error Log: => mmcinfo Device: FSL_SDHC Manufacturer ID: 0 OEM: 0 Name: Tran Speed: 0 Rd Block Len: 0 MMC version 0.0 High Capacity: No Capacity: 0 Bytes Bus Width: 0-bit => Signed-off-by: Haijun Zhang <Haijun.Zhang(a)freescale.com> Signed-off-by: Xie Shaohui-B21989 <B21989(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a7170b4..d4c1eef 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -521,6 +521,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (!mmc) return -ENOMEM; + memset(mmc, 0, sizeof(struct mmc)); sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; -- 1.8.4

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[U-Boot] [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0
by Haijun Zhang 30 Oct '13

30 Oct '13

eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Add some new register and it simple description. Signed-off-by: Haijun Zhang <haijun.zhang(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 62 +++++++++++++++++++++++++++++-------------------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 589288b..f3d4b90 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -40,31 +40,43 @@ DECLARE_GLOBAL_DATA_PTR; struct fsl_esdhc { - uint dsaddr; - uint blkattr; - uint cmdarg; - uint xfertyp; - uint cmdrsp0; - uint cmdrsp1; - uint cmdrsp2; - uint cmdrsp3; - uint datport; - uint prsstat; - uint proctl; - uint sysctl; - uint irqstat; - uint irqstaten; - uint irqsigen; - uint autoc12err; - uint hostcapblt; - uint wml; - uint mixctrl; - char reserved1[4]; - uint fevt; - char reserved2[168]; - uint hostver; - char reserved3[780]; - uint scr; + uint dsaddr; /* SDMA system address register */ + uint blkattr; /* Block attributes register */ + uint cmdarg; /* Command argument register */ + uint xfertyp; /* Transfer type register */ + uint cmdrsp0; /* Command response 0 register */ + uint cmdrsp1; /* Command response 1 register */ + uint cmdrsp2; /* Command response 2 register */ + uint cmdrsp3; /* Command response 3 register */ + uint datport; /* Buffer data port register */ + uint prsstat; /* Present state register */ + uint proctl; /* Protocol control register */ + uint sysctl; /* System Control Register */ + uint irqstat; /* Interrupt status register */ + uint irqstaten; /* Interrupt status enable register */ + uint irqsigen; /* Interrupt signal enable register */ + uint autoc12err; /* Auto CMD error status register */ + uint hostcapblt; /* Host controller capabilities register */ + uint wml; /* Watermark level register */ + uint mixctrl; /* For USDHC */ + char reserved1[4]; /* reserved */ + uint fevt; /* Force event register */ + uint admaes; /* ADMA error status register */ + uint adsaddr; /* ADMA system address register */ + char reserved2[160]; /* reserved */ + uint hostver; /* Host controller version register */ + char reserved3[4]; /* reserved */ + uint dmaerraddr; /* DMA error address register */ + char reserved4[4]; /* reserved */ + uint dmaerrattr; /* DMA error attribute register */ + char reserved5[4]; /* reserved */ + uint hostcapblt2; /* Host controller capabilities register 2 */ + char reserved6[8]; /* reserved */ + uint tcr; /* Tuning control register */ + char reserved7[28]; /* reserved */ + uint sddirctl; /* SD direction control register */ + char reserved8[712]; /* reserved */ + uint scr; /* eSDHC control register */ }; /* Return the XFERTYP flags for a given command and data packet */ -- 1.8.4

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