January 2013 - U-Boot

[U-Boot] [U-BOOT] help on mmc driver
by Jagannadha Sutradharudu Teki 25 Jan '13

25 Jan '13

Hi, I need some help on mmc driver development on u-boot. Few questions: 1. is mmc framework in u-boot supports all type of card interfaces like SD, MMC, and eMMC 2. If I write a driver do I need to develop the common driver for all or a separate drivers for individual cards. 3. Is there any drivers in current u-boot drivers/mmc have individual card interfaces support (SD & MMC & eMMC) 4. is there any drivers in current u-boot driver/mmc for common card intefaces (SD | MMC | eMMC) Request for help. Thanks, Jagan. This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

2 2

[U-Boot] [PATCH v5 2/2] board: add support for amcore board
by Angelo Dureghello 25 Jan '13

25 Jan '13

2 2

[U-Boot] [PATCH v2] integrator: pass a Device Tree by default
by Linus Walleij 25 Jan '13

25 Jan '13

This, enabled the FDT library for the Integrators, updates the Integrator/CP default command to load and pass a Device Tree when booting the kernel from the on-board ethernet, define same environment for the Integrator/AP and move the load address around to something even. Signed-off-by: Linus Walleij <linus.walleij(a)linaro.org> --- ChangeLog v1->v2: - Skip definition of $loadaddr, rely on CONFIG_LOAD_ADDR instead. --- include/configs/integrator-common.h | 3 ++- include/configs/integratorap.h | 7 +++++-- include/configs/integratorcp.h | 9 ++++++--- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 564b418..f4a182c 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -30,7 +30,7 @@ #define CONFIG_SYS_MEMTEST_END 0x10000000 #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x800 /* default load address */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ @@ -41,6 +41,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ /* diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index c6907b5..f409f2a 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -62,9 +62,12 @@ */ #include <config_cmd_default.h> -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" -#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTCOMMAND "setenv servip 192.168.1.100 ; " \ + "setenv fdtaddr 0x00800000 ; " \ + "echo \"\\\\$loadaddr = $loadaddr, \\\\$fdtaddr=$fdtaddr\" ; " \ + "echo \"load binaries then: bootm $loadaddr - $fdtaddr\"" /* * Miscellaneous configurable options diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index ca02a6f..9446edb 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -60,11 +60,14 @@ #include <config_cmd_default.h> #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" -#define CONFIG_BOOTCOMMAND "tftpboot ; bootm" #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104 -#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" +#define CONFIG_BOOTCOMMAND "setenv servip 192.168.1.100 ; " \ + "setenv fdtaddr 0x00800000 ; " \ + "bootp $loadaddr $servip:uImage ; " \ + "bootp $fdtaddr $servip:integratorcp.dtb ; " \ + "bootm $loadaddr - $fdtaddr" /* * Miscellaneous configurable options -- 1.8.1

2 1

Re: [U-Boot] Nand flash R/W,saveenv issue..
by Marek Vasut 25 Jan '13

25 Jan '13

Dear Manukumar, > Hello, CCing someone who might actually help you, CCing the uboot mailing list, please keep it that way. > i can able to detect nand flash. > but i had an issue that i could not do operation(Read/write) > on nand flash. > i tried to erase the nand flash i got the error as below: > > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > > even if i try to saveenv then also is not saving the envionment > variables > > processor used: P1012 > nand flash: samsung K9F5608U0D > > please reply ASAP. > > manukumar > signal-networks Best regards, Marek Vasut

9 39

[U-Boot] [RFC] powerpc/lib: unsafe register handling in wait_ticks
by Mats Kärrman 25 Jan '13

25 Jan '13

Hi, If watchdog is enabled, the arch/powerpc/lib/ticks.S::wait_ticks() function calls the function specified by the WATCHDOG_RESET macro. The wait_ticks function depends on the registers r0, r6 and r7 being preserved however that is not guaranteed if the reset function is a C function. The following patch changes to using r14+r15 instead of r6+r7 and saves all necessary registers on the stack. As I'm quite fresh to PowerPC assembly language I would appreciate any feedback on the implementation. On a side note, one could wonder why this function is not written in C language to start with. Best regards, Mats Kärrman --- a/arch/powerpc/lib/ticks.S +++ b/arch/powerpc/lib/ticks.S @@ -50,19 +50,24 @@ wait_ticks: stwu r1, -16(r1) mflr r0 /* save link register */ stw r0, 20(r1) /* Use r0 or GDB will be unhappy */ - mr r7, r3 /* save tick count */ + stw r14, 12(r1) /* save used registers */ + stw r15, 8(r1) + mr r14, r3 /* save tick count */ bl get_ticks /* Get start time */ /* Calculate end time */ - addc r7, r4, r7 /* Compute end time lower */ - addze r6, r3 /* and end time upper */ + addc r14, r4, r14 /* Compute end time lower */ + addze r15, r3 /* and end time upper */ WATCHDOG_RESET /* Trigger watchdog, if needed */ 1: bl get_ticks /* Get current time */ - subfc r4, r4, r7 /* Subtract current time from end time */ - subfe. r3, r3, r6 + subfc r4, r4, r14 /* Subtract current time from end time */ + subfe. r3, r3, r15 bge 1b /* Loop until time expired */ - mtlr r0 /* restore link register */ + lwz r15, 8(r1) /* restore saved registers */ + lwz r14, 12(r1) + lwz r0, 20(r1) addi r1,r1,16 + mtlr r0 blr

3 3

[U-Boot] [PATCH] powerpc/p2041: skip waiting for SERDES bank 3 reset done
by Anatolij Gustschin 25 Jan '13

25 Jan '13

Bank 3 is not present on P2041, do not try to wait for RSTDONE for this bank. This fixes the bank 3 reset wait timeout and thus speeds up booting on P2041RDB. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Shaohui Xie <Shaohui.Xie(a)freescale.com> Cc: Andy Fleming <afleming(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5495dc5..2cea1dc 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -579,6 +579,10 @@ void fsl_serdes_init(void) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); if (serdes_lane_enabled(lane)) { +#if defined(CONFIG_PPC_P2041) + if (!is_serdes_prtcl_valid(lane_prtcl)) + continue; +#endif have_bank[serdes_get_bank_by_lane(lane)] = 1; serdes_prtcl_map |= (1 << lane_prtcl); } -- 1.7.11.7

2 5

[U-Boot] How to add new device driver from Linux driver source
by "Chen, Jack C.W. (陳志偉 IES)" 25 Jan '13

25 Jan '13

Dears, Our system used u-boot as the boot code, and it would be like to support SD card. We get the SD controller driver from vendor, it is linux source code. Do you have any comments or documents about how to port this source code into u-boot source tree. We would like to build it and try if this can work or should do modify on this source. Thanks Jack

2 1

[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

5 11

[U-Boot] s3c2416 support in u-boot
by Woody Wu 25 Jan '13

25 Jan '13

Hi, It's a surprise that I don't find s3c2416 related files in the arch/cpu/arm926ejs directory. Where is the s3c2416 support in the u-boot code? Thanks in advance. -- woody I can't go back to yesterday - because I was a different person then.

1 0

[U-Boot] [PATCH][v2] powerpc/p2041: fix serdes reference clock frequency display for PC board
by Shaohui Xie 25 Jan '13

25 Jan '13

PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for v2: fix logical error and use braces around multi-line if bodies. board/freescale/p2041rdb/p2041rdb.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 4e4d18f..6476c8b 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -227,6 +227,17 @@ int misc_init_r(void) "'00' is unsupported\n"); else actual[i] = freq[i][clock]; + + /* + * PC board uses a different CPLD with PB board, this CPLD + * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB + * board has cpld_ver_sub = 0, and pcba_ver = 4. + */ + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) + && (CPLD_READ(pcba_ver) == 5)) { + /* PC board bank2 frequency */ + actual[i] = freq[i-1][clock]; + } } for (i = 0; i < NUM_SRDS_BANKS; i++) { -- 1.6.4

1 0