January 2013 - U-Boot

[U-Boot] [PATCH 1/3] mxs: Use SoC agnostic configuration option for power switch setting
by Otavio Salvador 26 Jan '13

26 Jan '13

The power switch option is compatible with i.MX23 and i.MX28 so the configration option needs to reflect it. We choose 'CONFIG_SPL_MXS_PSWITCH_WAIT' for the option name. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- arch/arm/cpu/arm926ejs/mxs/mxs_init.h | 2 +- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h index 2ddc5bc..084def5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs_init.h +++ b/arch/arm/cpu/arm926ejs/mxs/mxs_init.h @@ -30,7 +30,7 @@ void early_delay(int delay); void mxs_power_init(void); -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void); #else static inline void mxs_power_wait_pswitch(void) { } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e9d6302..287c698 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -921,7 +921,7 @@ void mxs_power_init(void) early_delay(1000); } -#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void) { struct mxs_power_regs *power_regs = -- 1.8.1

2 4

[U-Boot] [PATCH 0/9 v6] Add TMU support for Exynos5250 based SMDK5250
by Akshay Saraswat 26 Jan '13

26 Jan '13

This patch series adds support for TMU driver using device tree for Exynos5250 based SMDK5250 board. Changes since v5: - Patch-1: Added 'Acked-by' and fixed few nits. - Patch-2: Added 'Acked-by'. - Patch-3: Added 'Acked-by' and fixed few nits. - Patch-4: Added 'Acked-by'. - Patch-5: Added 'Acked-by'. - Patch-6: Fixed few nits. - Patch-7: Added 'Acked-by'. - Patch-8: New Patch. - Patch-9: New Patch. Akshay Saraswat (9): EXYNOS5: TMU: Add driver for Thermal Management Unit EXYNOS5: Implement board_poweroff for Thermal Management Unit EXYNOS5: FDT: Add TMU device node values EXYNOS5: TMU: Add TMU init and status check EXYNOS5: Config: Enable support for Exynos TMU driver TMU: Add TMU support in dtt command EXYNOS5: Config: Enable dtt command for TMU EXYNOS5: TMU: Add hardware tripping EXYNOS5: FDT: Add a H/W-trip member to TMU node arch/arm/cpu/armv7/exynos/power.c | 25 ++ arch/arm/dts/exynos5250.dtsi | 5 + arch/arm/include/asm/arch-exynos/exynos-tmu.h | 58 +++++ arch/arm/include/asm/arch-exynos/power.h | 6 + board/samsung/dts/exynos5250-smdk5250.dts | 13 + board/samsung/smdk5250/smdk5250.c | 35 +++ common/cmd_dtt.c | 22 ++ doc/device-tree-bindings/exynos/tmu.txt | 49 ++++ drivers/power/Makefile | 1 + drivers/power/exynos-tmu.c | 317 +++++++++++++++++++++++++ include/configs/exynos5250-dt.h | 5 + include/fdtdec.h | 1 + include/tmu.h | 46 ++++ lib/fdtdec.c | 1 + 14 files changed, 584 insertions(+) create mode 100644 arch/arm/include/asm/arch-exynos/exynos-tmu.h create mode 100644 doc/device-tree-bindings/exynos/tmu.txt create mode 100644 drivers/power/exynos-tmu.c create mode 100644 include/tmu.h -- 1.7.9.5

2 12

[U-Boot] a couple questions about CONFIG_SYS_LONGHELP
by Robert P. J. Day 26 Jan '13

26 Jan '13

first, is there any need for so many header files to define the macro CONFIG_SYS_LONGHELP individually? a quick count of how many u-boot source files do just that: $ grep -r "define.*CONFIG_SYS_LONGHELP" * | wc -l 479 $ is it really necessary for almost 500 source files to each define that macro? and second, i'm not sure how to read this out of cmd_pci.c: ===== start #ifdef CONFIG_SYS_LONGHELP static char pci_help_text[] = "[bus] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" #ifdef CONFIG_CMD_PCI_ENUM "pci enum\n" " - re-enumerate PCI buses\n" #endif "pci header b.d.f\n" " - show header of PCI device 'bus.device.function'\n" "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" " - display PCI configuration space (CFG)\n" "pci next[.b, .w, .l] b.d.f address\n" " - modify, read and keep CFG address\n" "pci modify[.b, .w, .l] b.d.f address\n" " - modify, auto increment CFG address\n" "pci write[.b, .w, .l] b.d.f address value\n" " - write to CFG address"; #endif U_BOOT_CMD( pci, 5, 1, do_pci, "list and access PCI Configuration Space", pci_help_text ); ===== end note how, if CONFIG_SYS_LONGHELP is defined, the symbol "pci_help_text" is created as the text, but its *usage* just below in the U_BOOT_CMD macro is *outside* of that preprocessor check. how would that work if CONFIG_SYS_LONGHELP is undefined? not at my dev host right this minute so i can't test, but it just looks ... weird. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

2 5

[U-Boot] [PATCH 1/1] OMAP3: igep00x0: fix a build warning on IGEP boards
by Javier Martinez Canillas 26 Jan '13

26 Jan '13

commit b689cd5 OMAP3: use a single board file for IGEP devices introduced the following build warning: igep00x0.h:168:24: warning: backslash-newline at end of file [enabled by default] This patch fixes the issue. Signed-off-by: Javier Martinez Canillas <javier.martinez(a)collabora.co.uk> --- board/isee/igep00x0/igep00x0.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 3a84335..ea1e9ac 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -167,4 +167,4 @@ static void setup_net_chip(void); #define MUX_IGEP0030() \ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ -- 1.7.7.6

2 1

[U-Boot] [PATCH v6 2/2] board: add support for amcore board
by Angelo Dureghello 26 Jan '13

26 Jan '13

1 0

[U-Boot] [PATCH] cmd_usb.c: Make usb help info consistent for "start".
by Robert P. J. Day 26 Jan '13

26 Jan '13

Make USB help info for "start" subcommand consistent with other USB subcommands. Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- unless there's something different about the "start" subcommand, this would seem to make sense for consistency. diff --git a/common/cmd_usb.c b/common/cmd_usb.c index dacdc2d..f04ee73 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -575,7 +575,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( usb, 5, 1, do_usb, "USB sub-system", - "start - start (scan) USB controller\n" + "usb start - start (scan) USB controller\n" "usb reset - reset (rescan) USB controller\n" "usb stop [f] - stop USB [f]=force stop\n" "usb tree - show USB device tree\n" @@ -601,7 +601,7 @@ U_BOOT_CMD( U_BOOT_CMD( usb, 5, 1, do_usb, "USB sub-system", - "start - start (scan) USB controller\n" + "usb start - start (scan) USB controller\n" "usb reset - reset (rescan) USB controller\n" "usb tree - show USB device tree\n" "usb info [dev] - show available USB devices" rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 1

[U-Boot] Please pull u-boot-ti/master
by Tom Rini 26 Jan '13

26 Jan '13

Hello, The following changes since commit 7cb70a34b976e68f6348ea0718780e8f38901482: fdt: fix dts preprocessor options (2013-01-17 09:07:59 -0700) are available in the git repository at: git://git.denx.de/u-boot-ti.git master for you to fetch changes up to e25a6b504bb0c6e7a3a20cc0d2afacb6d88d29b1: AM335X: Set fdt_high for AM335X devices to enable booting with Device Tree (2013-01-25 17:10:43 -0500) ---------------------------------------------------------------- Javier Martinez Canillas (3): OMAP3: use a single board file for IGEP devices OMAP3: igep00x0: add boot status GPIO LED omap4: allow the use of a plain text env file instead boot scripts Jeff Lance (1): Add DDR3 support for AM335x-EVM (Version 1.5A) Lars Poeschel (3): am33xx: add a pulldown macro to pinmux config pcm051: Add support for Phytec phyCORE-AM335x am335x: display msg when reading MAC from efuse hvaibhav(a)ti.com (1): AM335X: Set fdt_high for AM335X devices to enable booting with Device Tree MAINTAINERS | 3 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 34 +++ arch/arm/include/asm/arch-am33xx/mux.h | 3 +- board/isee/igep0020/igep0020.h | 151 ---------- board/isee/igep0030/Makefile | 43 --- board/isee/igep0030/igep0030.c | 117 -------- board/isee/{igep0020 => igep00x0}/Makefile | 2 +- .../{igep0020/igep0020.c => igep00x0/igep00x0.c} | 51 +++- .../{igep0030/igep0030.h => igep00x0/igep00x0.h} | 35 ++- board/phytec/pcm051/Makefile | 46 +++ board/phytec/pcm051/board.c | 266 +++++++++++++++++ board/phytec/pcm051/board.h | 33 +++ board/phytec/pcm051/mux.c | 133 +++++++++ board/ti/am335x/board.c | 43 ++- boards.cfg | 9 +- include/configs/am335x_evm.h | 1 + include/configs/igep00x0.h | 5 + include/configs/omap4_common.h | 17 +- include/configs/pcm051.h | 301 ++++++++++++++++++++ 19 files changed, 951 insertions(+), 342 deletions(-) delete mode 100644 board/isee/igep0020/igep0020.h delete mode 100644 board/isee/igep0030/Makefile delete mode 100644 board/isee/igep0030/igep0030.c rename board/isee/{igep0020 => igep00x0}/Makefile (98%) rename board/isee/{igep0020/igep0020.c => igep00x0/igep00x0.c} (86%) rename board/isee/{igep0030/igep0030.h => igep00x0/igep00x0.h} (93%) create mode 100644 board/phytec/pcm051/Makefile create mode 100644 board/phytec/pcm051/board.c create mode 100644 board/phytec/pcm051/board.h create mode 100644 board/phytec/pcm051/mux.c create mode 100644 include/configs/pcm051.h -- Tom

3 2

[U-Boot] Please pull u-boot-mpc85xx.git
by Andy Fleming 25 Jan '13

25 Jan '13

README.mips: update known issues and TODOs (2013-01-16 10:52:08 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master for you to fetch changes up to 1342f7dd2c864889ce3ef6a78fe74155fd1f9a8f: corenet: Disable video on P2020DS (2013-01-25 10:32:22 -0600) ---------------------------------------------------------------- Anatolij Gustschin (1): mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUE Andy Fleming (1): corenet: Disable video on P2020DS Hongtao Jia (2): powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs powerpc/mpc8544ds: Add USB controller support for MPC8544DS James Yang (5): Move DDR command parsing to separate function Fix data stage name matching issue Add copy command to FSL DDR interactive README.fsl-ddr typos and update to reflect hotkey powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commands Poonam Aggrwal (2): powerpc/mpc85xx: Few updates for B4860 cpu changes powerpc/mpc85xx:Add support of B4420 SoC Prabhakar Kushwaha (8): board/T4240qds:Fix TLB and LAW size of NAND flash boards/T4240qds:Fix IFC AMASK init as per FPGA register space board/freescale/common:Add support of QTAG register powerpc/mpc85xx:Fix Core cluster configuration loop powerpc/t4240qds: Print FPGA detail version powerpc/mpc85xx: Add BSC9132/BSC9232 processor support powerpc/85xx: Add BSC9132QDS support board/common: Add support for QIXIS read/write using i2c Scott Wood (1): powerpc/mpc85xx: add support for MMUv2 page sizes Shaohui Xie (1): powerpc/p2041: move Lanes mux to board early init Shaveta Leekha (3): powerpc/qixis: enable qixis dump command and add switch dumping command powerpc/b4860qds: Add support to dump switch settings on b4860qds board powerpc/t4240qds: Add support to dump switch settings on t4240qds board Shengzhou Liu (1): powerpc/t4240: Adding workaround errata A-005871 Timur Tabi (1): powerpc/t4qds: move VSC3316 config data from t4qds.h to t4qds.c Vakul Garg (1): powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' Valentin Longchamp (2): powerpc/p2041: add RCW file for P2041RDB powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDB York Sun (4): powerpc/mpc85xx: Reserve default boot page powerpc/t4240qds: Update IFC timing for NOR flash powerpc/b4860qds: Added Support for B4860QDS powerpc/mpc8xxx: Enable entering DDR debugging by key press MAINTAINERS | 4 + arch/powerpc/cpu/mpc85xx/Makefile | 5 + arch/powerpc/cpu/mpc85xx/b4860_ids.c | 6 + arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 60 ++ arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 96 +++ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 + arch/powerpc/cpu/mpc85xx/cpu_init.c | 44 +- arch/powerpc/cpu/mpc85xx/fdt.c | 24 + arch/powerpc/cpu/mpc85xx/start.S | 2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 19 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 4 + arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 3 +- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 324 ++++++--- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 78 +- arch/powerpc/include/asm/config_mpc85xx.h | 39 +- arch/powerpc/include/asm/immap_85xx.h | 34 +- arch/powerpc/include/asm/mmu.h | 52 +- arch/powerpc/include/asm/processor.h | 2 + board/freescale/b4860qds/Makefile | 54 ++ board/freescale/b4860qds/b4860qds.c | 505 +++++++++++++ board/freescale/b4860qds/b4860qds.h | 26 + board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 ++ board/freescale/b4860qds/b4860qds_qixis.h | 37 + board/freescale/b4860qds/ddr.c | 190 +++++ board/freescale/b4860qds/eth_b4860qds.c | 338 +++++++++ board/freescale/b4860qds/law.c | 44 ++ board/freescale/b4860qds/pci.c | 39 + board/freescale/b4860qds/tlb.c | 127 ++++ board/freescale/bsc9132qds/Makefile | 52 ++ board/freescale/bsc9132qds/README | 150 ++++ board/freescale/bsc9132qds/bsc9132qds.c | 406 +++++++++++ board/freescale/bsc9132qds/ddr.c | 209 ++++++ board/freescale/bsc9132qds/law.c | 35 + board/freescale/bsc9132qds/tlb.c | 92 +++ board/freescale/common/qixis.c | 107 ++- board/freescale/common/qixis.h | 13 + board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 + board/freescale/p2041rdb/eth.c | 39 - board/freescale/p2041rdb/p2041rdb.c | 44 ++ board/freescale/t4qds/law.c | 2 +- board/freescale/t4qds/t4qds.c | 83 ++- board/freescale/t4qds/t4qds.h | 11 - board/freescale/t4qds/tlb.c | 2 +- boards.cfg | 12 + doc/README.b4860qds | 330 +++++++++ doc/README.fsl-ddr | 33 +- drivers/net/fm/Makefile | 1 + drivers/net/fm/b4860.c | 79 +++ include/configs/B4860QDS.h | 820 ++++++++++++++++++++++ include/configs/BSC9132QDS.h | 667 ++++++++++++++++++ include/configs/MPC8544DS.h | 12 + include/configs/MPC8572DS.h | 2 +- include/configs/P2020DS.h | 2 +- include/configs/P2041RDB.h | 2 + include/configs/t4qds.h | 12 +- 57 files changed, 5260 insertions(+), 205 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c create mode 100644 board/freescale/b4860qds/Makefile create mode 100644 board/freescale/b4860qds/b4860qds.c create mode 100644 board/freescale/b4860qds/b4860qds.h create mode 100644 board/freescale/b4860qds/b4860qds_crossbar_con.h create mode 100644 board/freescale/b4860qds/b4860qds_qixis.h create mode 100644 board/freescale/b4860qds/ddr.c create mode 100644 board/freescale/b4860qds/eth_b4860qds.c create mode 100644 board/freescale/b4860qds/law.c create mode 100644 board/freescale/b4860qds/pci.c create mode 100644 board/freescale/b4860qds/tlb.c create mode 100644 board/freescale/bsc9132qds/Makefile create mode 100644 board/freescale/bsc9132qds/README create mode 100644 board/freescale/bsc9132qds/bsc9132qds.c create mode 100644 board/freescale/bsc9132qds/ddr.c create mode 100644 board/freescale/bsc9132qds/law.c create mode 100644 board/freescale/bsc9132qds/tlb.c create mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg create mode 100644 doc/README.b4860qds create mode 100644 drivers/net/fm/b4860.c create mode 100644 include/configs/B4860QDS.h create mode 100644 include/configs/BSC9132QDS.h

3 3

[U-Boot] [PATCH v5 2/2] OMAP3: igep00x0: add boot status GPIO LED
by Javier Martinez Canillas 25 Jan '13

25 Jan '13

This patch adds an GPIO LED boot status for IGEP boards. The GPIO LED used is the red LED0 while the Linux kernel uses the green LED0 as the boot status. By using different GPIO LEDs, the user can know in which step of the boot process the board currently is. Signed-off-by: Javier Martinez Canillas <javier.martinez(a)collabora.co.uk> --- Changes since v4: - Since gpio_direction_output() sets the value, there is no need to call gpio_set_value() as suggested by Igor Grinberg. Changes since v3: - Avoid code duplication but having a single show_boot_progress() function as suggested by Wolfgang Denk. Changes since v2: - Use show_boot_progress() instead implementing yet another boot status signalling as suggested by Wolfgang Denk. Changes since v1: - Don't set gd->bd->bi_arch_number since is done in arch/arm/lib/board.c - Use CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020 instead of check bi_arch_number as suggested by Igor Grinberg. board/isee/igep00x0/igep00x0.c | 13 +++++++++++++ board/isee/igep00x0/igep00x0.h | 8 ++++++++ include/configs/igep00x0.h | 3 +++ 3 files changed, 24 insertions(+), 0 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index fe3522a..931416a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -60,6 +60,19 @@ int board_init(void) return 0; } +#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) +void show_boot_progress(int val) +{ + if (val < 0) { + /* something went wrong */ + return; + } + + if (!gpio_request(IGEP00X0_GPIO_LED, "")) + gpio_direction_output(IGEP00X0_GPIO_LED, 1); +} +#endif + #ifdef CONFIG_SPL_BUILD /* * Routine: omap_rev_string diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 3133e41..fefdb89 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -23,6 +23,14 @@ #ifndef _IGEP00X0_H_ #define _IGEP00X0_H_ +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) +#define IGEP00X0_GPIO_LED 27 +#endif + +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) +#define IGEP00X0_GPIO_LED 16 +#endif + const omap3_sysinfo sysinfo = { DDR_STACKED, #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 15e233b..47f637e 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -82,6 +82,9 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* define to enable boot progress via leds */ +#define CONFIG_SHOW_BOOT_PROGRESS + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 -- 1.7.7.6

3 8

[U-Boot] [PATCH v2 1/2] OMAP3: use a single board file for IGEP devices
by Javier Martinez Canillas 25 Jan '13

25 Jan '13

Even when the IGEPv2 board and the IGEP Computer-on-Module are different from a form factor point of view, they are very similar in the fact that share many components and how they are wired. So, it is possible (and better) to have a single board file for both devices and just use the CONFIG_MACH_TYPE to make a differentiation between each board when needed. This change avoids code duplication by removing 298 lines of code and makes future maintenance easier. Signed-off-by: Javier Martinez Canillas <javier.martinez(a)collabora.co.uk> --- Changes since v1 (suggested by Igor Grinberg): - Remove unnecesary ifdeffery - set CONFIG_CMD_NET just if CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020 - Move board specific muxes configuration to set_muxconf_regs() board/isee/igep0020/Makefile | 43 --------- board/isee/igep0020/igep0020.c | 177 ------------------------------------- board/isee/igep0020/igep0020.h | 151 -------------------------------- board/isee/igep0030/Makefile | 43 --------- board/isee/igep0030/igep0030.c | 118 ------------------------- board/isee/igep0030/igep0030.h | 151 -------------------------------- board/isee/igep00x0/Makefile | 43 +++++++++ board/isee/igep00x0/igep00x0.c | 189 ++++++++++++++++++++++++++++++++++++++++ board/isee/igep00x0/igep00x0.h | 163 ++++++++++++++++++++++++++++++++++ boards.cfg | 8 +- include/configs/igep00x0.h | 2 + 11 files changed, 401 insertions(+), 687 deletions(-) delete mode 100644 board/isee/igep0020/Makefile delete mode 100644 board/isee/igep0020/igep0020.c delete mode 100644 board/isee/igep0020/igep0020.h delete mode 100644 board/isee/igep0030/Makefile delete mode 100644 board/isee/igep0030/igep0030.c delete mode 100644 board/isee/igep0030/igep0030.h create mode 100644 board/isee/igep00x0/Makefile create mode 100644 board/isee/igep00x0/igep00x0.c create mode 100644 board/isee/igep00x0/igep00x0.h diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile deleted file mode 100644 index 00463e1..0000000 --- a/board/isee/igep0020/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := igep0020.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c deleted file mode 100644 index a8257a3..0000000 --- a/board/isee/igep0020/igep0020.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <netdev.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/omap_gpmc.h> -#include <asm/mach-types.h> -#include "igep0020.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* GPMC definitions for LAN9221 chips */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, -}; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: omap_rev_string - * Description: For SPL builds output board rev - */ -void omap_rev_string(void) -{ -} - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) -{ - *mr = MICRON_V_MR_165; -#ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -#else - if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - - } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } -#endif -} -#endif - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -#if defined(CONFIG_CMD_NET) -static void setup_net_chip(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); - - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } -} -#endif - -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) -int board_mmc_init(bd_t *bis) -{ - omap_mmc_init(0, 0, 0); - return 0; -} -#endif - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - twl4030_power_init(); - -#if defined(CONFIG_CMD_NET) - setup_net_chip(); -#endif - - dieid_num_r(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h deleted file mode 100644 index 3335ecc..0000000 --- a/board/isee/igep0020/igep0020.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _IGEP0020_H_ -#define _IGEP0020_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "IGEP v2 board", -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "ONENAND", -#else - "NAND", -#endif -}; - -static void setup_net_chip(void); - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ -#endif diff --git a/board/isee/igep0030/Makefile b/board/isee/igep0030/Makefile deleted file mode 100644 index cbc03d4..0000000 --- a/board/isee/igep0030/Makefile +++ /dev/null @@ -1,43 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := igep0030.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c deleted file mode 100644 index 107cb7f..0000000 --- a/board/isee/igep0030/igep0030.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <twl4030.h> -#include <asm/io.h> -#include <asm/arch/mem.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mux.h> -#include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> -#include "igep0030.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: omap_rev_string - * Description: For SPL builds output board rev - */ -void omap_rev_string(void) -{ -} - -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) -{ - *mr = MICRON_V_MR_165; -#ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -#else - if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - - } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } -#endif -} -#endif - -#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) -int board_mmc_init(bd_t *bis) -{ - omap_mmc_init(0, 0, 0); - return 0; -} -#endif - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - twl4030_power_init(); - - dieid_num_r(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h deleted file mode 100644 index a93339d..0000000 --- a/board/isee/igep0030/igep0030.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2010 - * ISEE 2007 SL, <www.iseebcn.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _IGEP0030_H_ -#define _IGEP0030_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 IGEP module", -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "ONENAND", -#else - "NAND", -#endif -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ - -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ -#endif diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile new file mode 100644 index 0000000..f595954 --- /dev/null +++ b/board/isee/igep00x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := igep00x0.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c new file mode 100644 index 0000000..fe3522a --- /dev/null +++ b/board/isee/igep00x0/igep00x0.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl4030.h> +#include <netdev.h> +#include <asm/gpio.h> +#include <asm/arch/omap_gpmc.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "igep00x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) +/* GPMC definitions for LAN9221 chips */ +static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, +}; +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +void omap_rev_string(void) +{ +} + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; +#ifdef CONFIG_BOOT_NAND + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; +#else + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(256 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } +#endif +} +#endif + +#if defined(CONFIG_CMD_NET) +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, + GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 64 as output pin and send a magic pulse through it */ + if (!gpio_request(64, "")) { + gpio_direction_output(64, 0); + gpio_set_value(64, 1); + udelay(1); + gpio_set_value(64, 0); + udelay(1); + gpio_set_value(64, 1); + } +} +#else +static inline void setup_net_chip(void) {} +#endif + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0); + return 0; +} +#endif + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + twl4030_power_init(); + + setup_net_chip(); + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); + +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) + MUX_IGEP0020(); +#endif + +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) + MUX_IGEP0030(); +#endif +} + +#if defined(CONFIG_CMD_NET) +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} +#endif diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h new file mode 100644 index 0000000..3133e41 --- /dev/null +++ b/board/isee/igep00x0/igep00x0.h @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2010 + * ISEE 2007 SL, <www.iseebcn.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _IGEP00X0_H_ +#define _IGEP00X0_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) + "OMAP3 IGEP v2 board", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) + "OMAP3 IGEP COM Module", +#endif +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "ONENAND", +#else + "NAND", +#endif +}; + +static void setup_net_chip(void); + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ +#endif + +#define MUX_IGEP0020() \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ + +#define MUX_IGEP0030() \ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ + diff --git a/boards.cfg b/boards.cfg index 91504c0..35fbc85 100644 --- a/boards.cfg +++ b/boards.cfg @@ -253,10 +253,10 @@ cm_t35 arm armv7 cm_t35 - omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 dig297 arm armv7 dig297 comelit omap3 -igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND -igep0020_nand arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND -igep0030_nand arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND +igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND +igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND +igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND +igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND am3517_evm arm armv7 am3517evm logicpd omap3 mt_ventoux arm armv7 mt_ventoux teejet omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index be7937d..15e233b 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -112,7 +112,9 @@ #ifdef CONFIG_BOOT_NAND #define CONFIG_CMD_NAND #endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#endif #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_NFS /* NFS support */ -- 1.7.7.6

3 2