August 2012 - U-Boot

[U-Boot] [PATCH] rtc: imxdi: Initial support
by Benoît Thébaudeau 09 Aug '12

09 Aug '12

Add support for Freescale's i.MX DryIce RTC, present on i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- .../drivers/rtc/Makefile | 1 + /dev/null => u-boot-66714b1/drivers/rtc/imxdi.c | 224 ++++++++++++++++++++ 2 files changed, 225 insertions(+) create mode 100644 u-boot-66714b1/drivers/rtc/imxdi.c diff --git u-boot-66714b1.orig/drivers/rtc/Makefile u-boot-66714b1/drivers/rtc/Makefile index faf4fcd..aeeea37 100644 --- u-boot-66714b1.orig/drivers/rtc/Makefile +++ u-boot-66714b1/drivers/rtc/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git u-boot-66714b1/drivers/rtc/imxdi.c u-boot-66714b1/drivers/rtc/imxdi.c new file mode 100644 index 0000000..c2be842 --- /dev/null +++ u-boot-66714b1/drivers/rtc/imxdi.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2009-2012 ADVANSEE + * Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> + * + * Based on the Linux rtc-imxdi.c driver, which is: + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2010 Orex Computed Radiography + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Freescale i.MX DryIce RTC + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> + +#if defined(CONFIG_CMD_DATE) + +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +/* DryIce Register Definitions */ + +#define DTCMR 0x00 /* Time Counter MSB Reg */ +#define DTCLR 0x04 /* Time Counter LSB Reg */ + +#define DCAMR 0x08 /* Clock Alarm MSB Reg */ +#define DCALR 0x0c /* Clock Alarm LSB Reg */ +#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ + +#define DCR 0x10 /* Control Reg */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ + +#define DSR 0x14 /* Status Reg */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DIER 0x18 /* Interrupt Enable Reg */ +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ + +/* + * This function attempts to clear the dryice write-error flag. + * + * A dryice write error is similar to a bus fault and should not occur in + * normal operation. Clearing the flag requires another write, so the root + * cause of the problem may need to be fixed before the flag can be cleared. + */ +static void clear_write_error(void) +{ + int cnt; + + puts("### Warning: RTC - Register write error!\n"); + + /* clear the write error flag */ + __raw_writel(DSR_WEF, IMX_DRYICE_BASE + DSR); + + /* wait for it to take effect */ + for (cnt = 0; cnt < 1000; cnt++) { + if ((__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) == 0) + return; + udelay(10); + } + puts("### Error: RTC - Cannot clear write-error flag!\n"); +} + +/* + * Write a dryice register and wait until it completes. + * + * This function uses interrupt flags to determine when the + * write has completed. + */ +static int di_write_wait(u32 val, int reg) +{ + int cnt; + int ret = 0; + int rc = 0; + + /* do the register write */ + __raw_writel(val, IMX_DRYICE_BASE + reg); + + /* wait for the write to finish */ + for (cnt = 0; cnt < 100; cnt++) { + if ((__raw_readl(IMX_DRYICE_BASE + DSR) & + (DSR_WCF | DSR_WEF)) != 0) { + ret = 1; + break; + } + udelay(10); + } + if (ret == 0) + printf("### Warning: RTC - Write-wait timeout " + "val = 0x%.8x reg = 0x%.8x\n", val, reg); + + /* check for write error */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) { + clear_write_error(); + rc = -1; + } + + return rc; +} + +/* + * Initialize dryice hardware + */ +static int di_init(void) +{ + int rc = 0; + + /* mask all interrupts */ + __raw_writel(0, IMX_DRYICE_BASE + DIER); + + /* put dryice into valid state */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_NVF) { + rc = di_write_wait(DSR_NVF | DSR_SVF, DSR); + if (rc) + goto err; + } + + /* initialize alarm */ + rc = di_write_wait(DCAMR_UNSET, DCAMR); + if (rc) + goto err; + rc = di_write_wait(0, DCALR); + if (rc) + goto err; + + /* clear alarm flag */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_CAF) { + rc = di_write_wait(DSR_CAF, DSR); + if (rc) + goto err; + } + + /* the timer won't count if it has never been written to */ + if (__raw_readl(IMX_DRYICE_BASE + DTCMR) == 0) { + rc = di_write_wait(0, DTCMR); + if (rc) + goto err; + } + + /* start keeping time */ + if (!(__raw_readl(IMX_DRYICE_BASE + DCR) & DCR_TCE)) { + rc = di_write_wait(__raw_readl(IMX_DRYICE_BASE + DCR) | DCR_TCE, + DCR); + if (rc) + goto err; + } + + return 0; + +err: + return rc; +} + +int rtc_get(struct rtc_time *tmp) +{ + unsigned long now; + int rc; + + rc = di_init(); + if (rc) + goto err; + + now = __raw_readl(IMX_DRYICE_BASE + DTCMR); + to_tm(now, tmp); + +err: + return rc; +} + +int rtc_set(struct rtc_time *tmp) +{ + unsigned long now; + int rc; + + rc = di_init(); + if (rc) + goto err; + + now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + /* zero the fractional part first */ + rc = di_write_wait(0, DTCLR); + if (rc == 0) + rc = di_write_wait(now, DTCMR); + +err: + return rc; +} + +void rtc_reset(void) +{ + di_init(); +} + +#endif

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[U-Boot] early_malloc outline
by Tomas Hlavacek 09 Aug '12

09 Aug '12

Hello all! In u-boot-dm mailinglist we had a discussion about implementation of early_malloc (not only) for U-Boot Driver Model. The intention is to have a simple malloc() function in the early stage of init before relocation and before RAM is up and running. There was an experimental patch that added the early heap to GD structure. In the following discussion Graeme Russ pointed out that there is a pre-console buffer which does the similar thing. And we should not explode GD by adding the early heap (which is going to be few hundreds of bytes long) into it. He suggested to create an independent area locked in cache lines for early heap in order to allow split GD and early heap into more non-contiguous blocks. Pavel Hermann said that we would have to copy data twice (first before the RAM is up and running and caches are still off and second after RAM and dlmalloc is initialized). Marek Vasut said (earlier in the discussion) that we do not need to care about few hundred of bytes, especially after copying them into RAM. And Wolfgang Denk resisted. He also pointed out that there are other possibilities where early memory may be allocated - on-chip-memory, external SRAM and others and these should be kept in mind including existing size restrictions. (I apologize for eventual misinterpretation and I am sorry that we do not have a link to the u-boot-dm mailinglist archive nor GMANE. But I can eventually Fwd. needed pieces of the discussion.) We would like to hear opinions on the early_malloc idea to find a broadly acceptable solution. Can/should we use some existing mechanism? Or would it be considered a viable option to choose different beginning address for early heap, use it (in architecture-specific way) and keep the pointer to the beginning in GD. Then copy the early heap to memory before caches are flushed and in case of DM copy again data from early heap to new destinations that has been obtained through malloc() when it is initialized? Tomas -- Tomáš Hlaváček <tmshlvck(a)gmail.com>

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[U-Boot] [PATCH] powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
by York Sun 09 Aug '12

09 Aug '12

Workaround for erratum NMG_CPU_A011 can be enabled by hwconfig with syntax fsl_cpu_a011:enable This workaround is not enabled by default. Enabling this workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. Signed-off-by: York Sun <yorksun(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 6 +++++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 24 +++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/release.S | 15 +++++++++++++++ 3 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 4e1a54a..858b3f8 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -27,6 +27,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + extern int enable_cpu_a011_workaround; +#endif __maybe_unused u32 svr = get_svr(); #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) @@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * The SVR has been checked by cpu_init_r(). */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + if (enable_cpu_a011_workaround) puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4f03d25..10f142e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,6 +38,7 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <hwconfig.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -47,6 +48,8 @@ #include "../../../../drivers/block/fsl_sata.h" +#define HWCONFIG_BUFFER_SIZE 128 + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE @@ -311,11 +314,30 @@ int cpu_init_r(void) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* + * CPU22 and NMG_CPU_A011 share the same workaround. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * NMG_CPU_A011 is activated by hwconfig with syntax: + * fsl_cpu_a011:enable */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + + if (hwconfig_arg_cmp_f("fsl_cpu_a011", "enable", buf) > 0) { + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3); + } +#endif + if (enable_cpu_a011_workaround) { flush_dcache(); mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); sync(); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 1860684..b8d4a37 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -163,6 +163,12 @@ __secondary_start_page: cmpw r3,r5 bge 2f 1: +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + lis r3,toreset(enable_cpu_a011_workaround)@ha + lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) + cmpwi r3,0 + beq 2f +#endif mfspr r3,L1CSR2 oris r3,r3,(L1CSR2_DCWS)@h mtspr L1CSR2,r3 @@ -346,6 +352,15 @@ __bootpg_addr: __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 0 + /* Fill in the empty space. The actual reset vector is * the last word of the page */ __secondary_start_code_end: -- 1.7.0.4

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[U-Boot] [PATCH 1/4] rmobile: armadillo-800eva: Change init function of SCIFA1
by Nobuhiro Iwamatsu 09 Aug '12

09 Aug '12

This initializes GPIO, without using PFC framework in board_early_init_f function. It is because it cannot initialize normally when PFC is used. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> --- board/atmark-techno/armadillo-800eva/armadillo-800eva.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c index a075865..0e9c222 100644 --- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c +++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c @@ -243,6 +243,9 @@ void s_init(void) #define I2C1_MSTP323 (1 << 23) #define GETHER_MSTP309 (1 << 9) +#define GPIO_SCIFA1_TXD (0xE60520C4) +#define GPIO_SCIFA1_RXD (0xE60520C3) + int board_early_init_f(void) { /* TMU */ @@ -256,9 +259,8 @@ int board_early_init_f(void) clrbits_le32(MSTPCR3, I2C1_MSTP323); /* SCIFA1 */ - r8a7740_pinmux_init(); - gpio_request(GPIO_FN_SCIFA1_RXD, NULL); - gpio_request(GPIO_FN_SCIFA1_TXD, NULL); + writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */ + writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */ /* IICCR */ writew(GPIO_ICCR_DATA, GPIO_ICCR); -- 1.7.10

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[U-Boot] Fcall to lib_ppc/board.c/trap_init() results in Machine Check Exception
by Vic 09 Aug '12

09 Aug '12

uboot sets up the trap handler (function trap_init called from lib_ppc/board.c). As soon this is called the processor seems to be getting an machine check exception/trap. (Refer to the logs below) This also apparently causes processor to freeze, such that I am not able to read any CPU registers using JTAG etc If we do not make calls to trap_init uboot cont. to work properly, but without fixing this issue we can not move ahead, as we need interrupt handling to work for the next stage. I understand that may be this exception already accrued @ some point before trap_init call was done, but I am looking for ideas on how to debug it... Vic PS: Last message from uboot on console. ** pre trap_init() Machine Check Exception. Caused by (from msr): regs 0fed0a00 Instruction Synchronous Machine Check

1 0

[U-Boot] [PATCH v2] powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional
by York Sun 09 Aug '12

09 Aug '12

This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun(a)freescale.com> --- Change since v1: Merged with patch "Change NMG_CPU_A011 workaround condition" Merged with patch "Enable workaround for erratum CPU_A011 for P3041" Added hwconfig variable length check arch/powerpc/cpu/mpc85xx/cmd_errata.c | 6 ++++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 37 +++++++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/release.S | 15 +++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 4e1a54a..858b3f8 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -27,6 +27,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + extern int enable_cpu_a011_workaround; +#endif __maybe_unused u32 svr = get_svr(); #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) @@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * The SVR has been checked by cpu_init_r(). */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + if (enable_cpu_a011_workaround) puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index fc6c287..74863b4 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -38,6 +38,7 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> +#include <hwconfig.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -47,6 +48,8 @@ #include "../../../../drivers/block/fsl_sata.h" +#define HWCONFIG_BUFFER_SIZE 128 + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE @@ -311,11 +314,41 @@ int cpu_init_r(void) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) /* + * CPU22 and NMG_CPU_A011 share the same workaround. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 - * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable */ - if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) + enable_cpu_a011_workaround = 0; + else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { flush_dcache(); mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); sync(); diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 1860684..1555a9b 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -163,6 +163,12 @@ __secondary_start_page: cmpw r3,r5 bge 2f 1: +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + lis r3,toreset(enable_cpu_a011_workaround)@ha + lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) + cmpwi r3,0 + beq 2f +#endif mfspr r3,L1CSR2 oris r3,r3,(L1CSR2_DCWS)@h mtspr L1CSR2,r3 @@ -346,6 +352,15 @@ __bootpg_addr: __spin_table: .space CONFIG_MAX_CPUS*ENTRY_SIZE + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 1 + /* Fill in the empty space. The actual reset vector is * the last word of the page */ __secondary_start_code_end: diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b6c44bb..7e61f71 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -399,6 +399,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -- 1.7.0.4

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[U-Boot] [PATCH v2 1/2] USB: EHCI: Initialize multiple USB controllers at once
by Jim Lin 09 Aug '12

09 Aug '12

Add support for command line "usb reset" or "usb start" to initialize , "usb stop" to stop multiple USB controllers at once. Other command like "usb tree" also supports multiple controllers. New added definitions in header file are: CONFIG_USB_MULTI CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- Changes in v2: - Renaming from CONFIG_USB_INIT_MULTI to CONFIG_USB_MULTI - Define CONFIG_USB_MAX_CONTROLLER_COUNT as 1 if not defined - Remove volatile from structure ehci_ctrl of ehci-hcd.c for a checkpatch.pl warning - Modify include/usb.h common/cmd_usb.c | 10 +++ common/usb.c | 98 +++++++++++++++++++++++++- common/usb_hub.c | 4 + drivers/usb/host/ehci-hcd.c | 167 +++++++++++++++++++++++++++++++----------- drivers/usb/host/ehci.h | 5 ++ include/usb.h | 12 +++ 6 files changed, 251 insertions(+), 45 deletions(-) diff --git a/common/cmd_usb.c b/common/cmd_usb.c index a8e3ae5..8d3093b 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -554,7 +554,17 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (strncmp(argv[1], "tree", 4) == 0) { printf("\nDevice Tree:\n"); +#ifdef CONFIG_USB_MULTI + for (i = 0; i < USB_MAX_DEVICE; i++) { + dev = usb_get_dev_index(i); + if (dev == NULL) + break; + if (dev->parent == NULL) + usb_show_tree(dev); + } +#else usb_show_tree(usb_get_dev_index(0)); +#endif return 0; } if (strncmp(argv[1], "inf", 3) == 0) { diff --git a/common/usb.c b/common/usb.c index 1b40228..065c70c 100644 --- a/common/usb.c +++ b/common/usb.c @@ -77,6 +77,89 @@ static int asynch_allowed; char usb_started; /* flag for the started/stopped USB status */ +#ifdef CONFIG_USB_MULTI +/********************************************************************** +***** + * Init USB Device + */ +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define +CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif + +int usb_init(void) +{ + void *ctrl; + int i; + struct usb_device *dev; + + running = 0; + dev_index = 0; + asynch_allowed = 1; + usb_hub_reset(); + + /* first make all devices unknown */ + for (i = 0; i < USB_MAX_DEVICE; i++) { + memset(&usb_dev[i], 0, sizeof(struct usb_device)); + usb_dev[i].devnum = -1; + } + + /* init low_level USB */ + printf("USB: "); + for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { + /* init low_level USB */ + ctrl = usb_lowlevel_init(i); + /* + * if lowlevel init is OK, scan the bus for devices + * i.e. search HUBs and configure them + */ + if (ctrl) { + running = 1; + + printf("scanning bus for devices... "); + dev = usb_alloc_new_device(ctrl); + /* + * device 0 is always present + * (root hub, so let it analyze) + */ + if (dev) + usb_new_device(dev); + } + } + + if (running) { + if (!dev_index) + printf("No USB Device found\n"); + else + printf("%d USB Device(s) found\n", dev_index); +#ifdef CONFIG_USB_KEYBOARD + drv_usb_kbd_init(); +#endif + USB_PRINTF("scan end\n"); + usb_started = 1; + return 0; + } else { + printf("Error, couldn't init Lowlevel part\n"); + usb_started = 0; + return -1; + } +} + +/********************************************************************** +******** + * Stop USB this stops the LowLevel Part and deregisters USB devices. + */ +int usb_stop(void) +{ + int i; + + if (usb_started) { + asynch_allowed = 1; + usb_started = 0; + usb_hub_reset(); + for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) + usb_lowlevel_stop(i); + } + return 0; +} +#else /********************************************************************** * some forward declerations... */ @@ -127,6 +210,7 @@ int usb_stop(void) } return res; } +#endif /* * disables the asynch behaviour of the control message. This is used for data @@ -750,11 +834,18 @@ struct usb_device *usb_get_dev_index(int index) return &usb_dev[index]; } - +#ifdef CONFIG_USB_MULTI +/* Save input pointer 'controller' into device structure. + * returns a pointer of a new device structure or NULL, if + * no device struct is available + */ +struct usb_device *usb_alloc_new_device(void *controller) #else /* returns a pointer of a new device structure or NULL, if * no device struct is available */ struct usb_device *usb_alloc_new_device(void) +#endif { int i; USB_PRINTF("New Device %d\n", dev_index); @@ -768,6 +859,9 @@ struct usb_device *usb_alloc_new_device(void) for (i = 0; i < USB_MAXCHILDREN; i++) usb_dev[dev_index].children[i] = NULL; usb_dev[dev_index].parent = NULL; +#ifdef CONFIG_USB_MULTI + usb_dev[dev_index].controller = controller; #endif dev_index++; return &usb_dev[dev_index - 1]; } @@ -945,6 +1039,7 @@ int usb_new_device(struct usb_device *dev) return 0; } +#ifndef CONFIG_USB_MULTI /* build device Tree */ static void usb_scan_devices(void) { @@ -969,5 +1064,6 @@ static void usb_scan_devices(void) #endif USB_PRINTF("scan end\n"); } +#endif /* EOF */ diff --git a/common/usb_hub.c b/common/usb_hub.c index f35ad95..8f2e3e3 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -243,7 +243,11 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) mdelay(200); /* Allocate a new device struct for it */ +#ifdef CONFIG_USB_MULTI + usb = usb_alloc_new_device(dev->controller); +#else usb = usb_alloc_new_device(); +#endif if (portstatus & USB_PORT_STAT_HIGH_SPEED) usb->speed = USB_SPEED_HIGH; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 2a82a29..7f8c734 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -29,13 +29,24 @@ #include "ehci.h" -int rootdev; +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define +CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif + +static struct ehci_ctrl { + struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ + struct ehci_hcor *hcor; + int rootdev; + uint16_t portreset; + struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN))); + struct QH qh_pool __attribute__((aligned(USB_DMA_MINALIGN))); + struct qTD td_pool[3] __attribute__((aligned(USB_DMA_MINALIGN))); + int qtd_counter; +} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; + struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ volatile struct ehci_hcor *hcor; -static uint16_t portreset; -DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN); - #define ALIGN_END_ADDR(type, ptr, size) \ ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) @@ -207,10 +218,8 @@ static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) { - ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); - ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN); - int qtd_counter = 0; - + struct QH *qh; + struct qTD *qtd; volatile struct qTD *vtd; unsigned long ts; uint32_t *tdp; @@ -219,6 +228,13 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, uint32_t cmd; int timeout; int ret = 0; + struct ehci_ctrl *ctrl; +#ifdef CONFIG_USB_MULTI + ctrl = dev->controller; +#else + ctrl = &ehcic[0]; +#endif + hcor = ctrl->hcor; debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, buffer, length, req); @@ -229,6 +245,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, le16_to_cpu(req->value), le16_to_cpu(req->value), le16_to_cpu(req->index)); + qh = &ctrl->qh_pool; + ctrl->qtd_counter = 0; + qtd = &ctrl->td_pool; memset(qh, 0, sizeof(struct QH)); memset(qtd, 0, 3 * sizeof(*qtd)); @@ -244,7 +263,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, * qh_overlay.qt_next ...... 13-10 H * - qh_overlay.qt_altnext */ - qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); + qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | + QH_LINK_TYPE_QH); c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && usb_pipeendpoint(pipe) == 0) ? 1 : 0; endpt = (8 << 28) | @@ -274,19 +293,21 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, * * [ buffer, buffer_hi ] loaded with "req". */ - qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_altnext = + cpu_to_hc32(QT_NEXT_TERMINATE); token = (0 << 31) | (sizeof(*req) << 16) | (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); - qtd[qtd_counter].qt_token = cpu_to_hc32(token); - if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) { + qtd[ctrl->qtd_counter].qt_token = cpu_to_hc32(token); + if (ehci_td_buffer(&qtd[ctrl->qtd_counter], req, sizeof(*req)) + != 0) { printf("unable construct SETUP td\n"); goto fail; } /* Update previous qTD! */ - *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); - tdp = &qtd[qtd_counter++].qt_next; + *tdp = cpu_to_hc32((uint32_t)&qtd[ctrl->qtd_counter]); + tdp = &qtd[ctrl->qtd_counter++].qt_next; toggle = 1; } @@ -300,22 +321,25 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, * * [ buffer, buffer_hi ] loaded with "buffer". */ - qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_next = + cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_altnext = + cpu_to_hc32(QT_NEXT_TERMINATE); token = (toggle << 31) | (length << 16) | ((req == NULL ? 1 : 0) << 15) | (0 << 12) | (3 << 10) | ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); - qtd[qtd_counter].qt_token = cpu_to_hc32(token); - if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) { + qtd[ctrl->qtd_counter].qt_token = cpu_to_hc32(token); + if (ehci_td_buffer(&qtd[ctrl->qtd_counter], buffer, length) + != 0) { printf("unable construct DATA td\n"); goto fail; } /* Update previous qTD! */ - *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); - tdp = &qtd[qtd_counter++].qt_next; + *tdp = cpu_to_hc32((uint32_t)&qtd[ctrl->qtd_counter]); + tdp = &qtd[ctrl->qtd_counter++].qt_next; } if (req != NULL) { @@ -326,30 +350,32 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, * qt_altnext ............. 07-04 H * qt_token ............... 0B-08 H */ - qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_next = + cpu_to_hc32(QT_NEXT_TERMINATE); + qtd[ctrl->qtd_counter].qt_altnext = + cpu_to_hc32(QT_NEXT_TERMINATE); token = (toggle << 31) | (0 << 16) | (1 << 15) | (0 << 12) | (3 << 10) | ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); - qtd[qtd_counter].qt_token = cpu_to_hc32(token); + qtd[ctrl->qtd_counter].qt_token = cpu_to_hc32(token); /* Update previous qTD! */ - *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]); - tdp = &qtd[qtd_counter++].qt_next; + *tdp = cpu_to_hc32((uint32_t)&qtd[ctrl->qtd_counter]); + tdp = &qtd[ctrl->qtd_counter++].qt_next; } - qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH); + ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | + QH_LINK_TYPE_QH); /* Flush dcache */ - flush_dcache_range((uint32_t)qh_list, - ALIGN_END_ADDR(struct QH, qh_list, 1)); + flush_dcache_range((uint32_t)&ctrl->qh_list, + ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3)); /* Set async. queue head pointer. */ - ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list); + ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list); usbsts = ehci_readl(&hcor->or_usbsts); ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); @@ -368,12 +394,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, /* Wait for TDs to be processed. */ ts = get_timer(0); - vtd = &qtd[qtd_counter - 1]; + vtd = &qtd[ctrl->qtd_counter - 1]; timeout = USB_TIMEOUT_MS(pipe); do { /* Invalidate dcache */ - invalidate_dcache_range((uint32_t)qh_list, - ALIGN_END_ADDR(struct QH, qh_list, 1)); + invalidate_dcache_range((uint32_t)&ctrl->qh_list, + ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); invalidate_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); invalidate_dcache_range((uint32_t)qtd, @@ -476,6 +502,14 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, int len, srclen; uint32_t reg; uint32_t *status_reg; + struct ehci_ctrl *ctrl; +#ifdef CONFIG_USB_MULTI + ctrl = dev->controller; +#else + ctrl = &ehcic[0]; +#endif + hcor = ctrl->hcor; + hccr = ctrl->hccr; if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { printf("The request port(%d) is not configured\n", @@ -548,7 +582,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, break; case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): debug("USB_REQ_SET_ADDRESS\n"); - rootdev = le16_to_cpu(req->value); + ctrl->rootdev = le16_to_cpu(req->value); break; case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: debug("USB_REQ_SET_CONFIGURATION\n"); @@ -598,7 +632,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; if (reg & EHCI_PS_OCC) tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; - if (portreset & (1 << le16_to_cpu(req->index))) + if (ctrl->portreset & (1 << le16_to_cpu(req->index))) tmpbuf[2] |= USB_PORT_STAT_C_RESET; srcptr = tmpbuf; @@ -650,7 +684,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); if (!ret) - portreset |= + ctrl->portreset |= 1 << le16_to_cpu(req->index); else printf("port(%d) reset error\n", @@ -683,7 +717,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; break; case USB_PORT_FEAT_C_RESET: - portreset &= ~(1 << le16_to_cpu(req->index)); + ctrl->portreset &= ~(1 << + le16_to_cpu(req->index)); break; default: debug("unknown feature %x\n", le16_to_cpu(req->value)); @@ -719,27 +753,52 @@ unknown: return -1; } +#ifdef CONFIG_USB_MULTI +int usb_lowlevel_stop(int index) +{ + return ehci_hcd_stop(index); +} +#else int usb_lowlevel_stop(void) { return ehci_hcd_stop(); } +#endif -int usb_lowlevel_init(void) +void *usb_lowlevel_multi_init(int index) { uint32_t reg; uint32_t cmd; + struct QH *qh_list; + +#ifdef CONFIG_USB_MULTI + if (ehci_hcd_init(index, &hccr, (struct ehci_hcor **)&hcor) != 0) + return NULL; + + /* EHCI spec section 4.1 */ + if (ehci_reset() != 0) + return NULL; +#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) + if (ehci_hcd_init(index, &hccr, (struct ehci_hcor **)&hcor) != 0) + return NULL; +#endif +#else if (ehci_hcd_init() != 0) - return -1; + return NULL; /* EHCI spec section 4.1 */ if (ehci_reset() != 0) - return -1; + return NULL; #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) if (ehci_hcd_init() != 0) - return -1; + return NULL; +#endif #endif + ehcic[index].hccr = hccr; + ehcic[index].hcor = hcor; + qh_list = &ehcic[index].qh_list; /* Set head of reclaim list */ memset(qh_list, 0, sizeof(*qh_list)); @@ -780,10 +839,24 @@ int usb_lowlevel_init(void) reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); - rootdev = 0; + ehcic[index].rootdev = 0; + + return ehcic + index; +} +#ifdef CONFIG_USB_MULTI +void *usb_lowlevel_init(int index) +{ + return usb_lowlevel_multi_init(index); } #else int +usb_lowlevel_init(void) { + if (usb_lowlevel_multi_init(0) == NULL) + return -1; return 0; } +#endif int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, @@ -801,14 +874,20 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *setup) { + struct ehci_ctrl *ctrl; if (usb_pipetype(pipe) != PIPE_CONTROL) { debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); return -1; } - if (usb_pipedevice(pipe) == rootdev) { - if (rootdev == 0) +#ifdef CONFIG_USB_MULTI + ctrl = dev->controller; +#else + ctrl = &ehcic[0]; +#endif + if (usb_pipedevice(pipe) == ctrl->rootdev) { + if (ctrl->rootdev == 0) dev->speed = USB_SPEED_HIGH; return ehci_submit_root(dev, pipe, buffer, length, setup); } diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index cc00ce4..1cc5c6e 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -201,7 +201,12 @@ struct QH { }; /* Low level init functions */ +#ifdef CONFIG_USB_MULTI +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor +**hcor); int ehci_hcd_stop(int index); #else int ehci_hcd_init(void); int ehci_hcd_stop(void); +#endif #endif /* USB_EHCI_H */ diff --git a/include/usb.h b/include/usb.h index ba3d169..628cfd5 100644 --- a/include/usb.h +++ b/include/usb.h @@ -140,6 +140,9 @@ struct usb_device { int portnr; struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; +#ifdef CONFIG_USB_MULTI + void *controller; /* hardware controller private data */ +#endif }; /********************************************************************** @@ -153,8 +156,13 @@ struct usb_device { defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \ defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) +#ifdef CONFIG_USB_MULTI +void *usb_lowlevel_init(int index); +int usb_lowlevel_stop(int index); +#else int usb_lowlevel_init(void); int usb_lowlevel_stop(void); +#endif int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len); int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, @@ -382,7 +390,11 @@ void usb_hub_reset(void); int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat); +#ifdef CONFIG_USB_MULTI +struct usb_device *usb_alloc_new_device(void *controller); #else struct usb_device *usb_alloc_new_device(void); +#endif int usb_new_device(struct usb_device *dev); #endif /*_USB_H_ */ -- 1.7.3 nvpublic

1 0

[U-Boot] [PATCH 2/2] tegra20: Initialize multiple USB controllers at once
by Jim Lin 09 Aug '12

09 Aug '12

Add support for command line "usb reset" or "usb start" to initialize , "usb stop" to stop multiple USB controllers at once. Other commands like "usb tree" also support multiple controllers. Example to add definitions in header file like include/configs/seaboard.h are: define CONFIG_USB_MULTI define CONFIG_USB_MAX_CONTROLLER_COUNT 3 Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- arch/arm/cpu/armv7/tegra20/usb.c | 15 +++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 4 ++++ drivers/usb/host/ehci-tegra.c | 15 +++++++++++++++ 3 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c index 178bb13..141d608 100644 --- a/arch/arm/cpu/armv7/tegra20/usb.c +++ b/arch/arm/cpu/armv7/tegra20/usb.c @@ -352,7 +352,11 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) if (portnum >= port_count) return -1; +#ifdef CONFIG_USB_MULTI + tegrausb_stop_port(portnum); +#else tegrausb_stop_port(); +#endif set_host_mode(&port[portnum]); usbctlr = port[portnum].reg; @@ -362,6 +366,16 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) return 0; } +#ifdef CONFIG_USB_MULTI +int tegrausb_stop_port(unsigned portnum) +{ + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + + usbctlr = port[portnum].reg; +#else int tegrausb_stop_port(void) { struct usb_ctlr *usbctlr; @@ -370,6 +384,7 @@ int tegrausb_stop_port(void) return -1; usbctlr = port[port_current].reg; +#endif /* Stop controller */ writel(0, &usbctlr->usb_cmd); diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h index 638033b..e7bc167 100644 --- a/arch/arm/include/asm/arch-tegra20/usb.h +++ b/arch/arm/include/asm/arch-tegra20/usb.h @@ -247,6 +247,10 @@ int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); * * @return 0 if ok, -1 if no port was active */ +#ifdef CONFIG_USB_MULTI +int tegrausb_stop_port(unsigned portnum); +#else int tegrausb_stop_port(void); +#endif #endif /* _TEGRA_USB_H_ */ diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 4646b29..fa2e1b1 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -50,6 +50,12 @@ void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) * Create the appropriate control structures to manage * a new EHCI host controller. */ +#ifdef CONFIG_USB_MULTI +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return tegrausb_start_port(index, hccr, hcor); +} +#else int ehci_hcd_init(void) { u32 our_hccr, our_hcor; @@ -66,13 +72,22 @@ int ehci_hcd_init(void) return 0; } +#endif /* * Destroy the appropriate control structures corresponding * the the EHCI host controller. */ +#ifdef CONFIG_USB_MULTI +int ehci_hcd_stop(int index) +{ + tegrausb_stop_port(index); + return 0; +} +#else int ehci_hcd_stop(void) { tegrausb_stop_port(); return 0; } +#endif -- 1.7.3 -- nvpublic

1 0

[U-Boot] [PATCH][v3] powerpc/CoreNet: add tool to support pbl image build.
by Shaohui Xie 09 Aug '12

09 Aug '12

Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- changes for v3: 1. dump config.mk, aligned to comment of Wolfgang Denk; 2. split one configuration file to two, one is for RCW, one is for PBI commands, add second entry in mkimage for second configuration file, aligned to comment of Wood Scott; 3. refined the README.pblimage; Makefile | 6 + board/freescale/corenet_ds/pbi.cfg | 51 ++++++ board/freescale/corenet_ds/rcw.cfg | 32 ++++ common/image.c | 1 + doc/README.pblimage | 114 +++++++++++++ include/configs/corenet_ds.h | 2 + include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 15 ++ tools/mkimage.h | 3 + tools/pblimage.c | 328 ++++++++++++++++++++++++++++++++++++ tools/pblimage.h | 36 ++++ 12 files changed, 591 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/pbi.cfg create mode 100644 board/freescale/corenet_ds/rcw.cfg create mode 100644 doc/README.pblimage create mode 100644 tools/pblimage.c create mode 100644 tools/pblimage.h diff --git a/Makefile b/Makefile index 57ad45b..98421b9 100644 --- a/Makefile +++ b/Makefile @@ -416,6 +416,11 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +$(obj)u-boot.pbl: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ + -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ + -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -773,6 +778,7 @@ clobber: tidy $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg new file mode 100644 index 0000000..50806ca --- /dev/null +++ b/board/freescale/corenet_ds/pbi.cfg @@ -0,0 +1,51 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 as 1MB SRAM +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/corenet_ds/rcw.cfg b/board/freescale/corenet_ds/rcw.cfg new file mode 100644 index 0000000..424c7c4 --- /dev/null +++ b/board/freescale/corenet_ds/rcw.cfg @@ -0,0 +1,32 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 diff --git a/common/image.c b/common/image.c index 202c8a1..71f55dc 100644 --- a/common/image.c +++ b/common/image.c @@ -143,6 +143,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_INVALID, NULL, "Invalid Image", }, { IH_TYPE_MULTI, "multi", "Multi-File Image", }, { IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",}, + { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, diff --git a/doc/README.pblimage b/doc/README.pblimage new file mode 100644 index 0000000..2b9bb5c --- /dev/null +++ b/doc/README.pblimage @@ -0,0 +1,114 @@ +------------------------------------------------------------------ +Freescale PBL(pre-boot loader) Boot Image generation using mkimage +------------------------------------------------------------------ + +The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and +NAND, etc. These SoCs use PBL to load RCW and/or pre-initialization +instructions. For more details refer section 5 Pre-boot loader +specifications of reference manual P3041RM/P4080RM/P5020RM at link: +http://www.freescale.com/webapp/search/Serp.jsp?Reference+Manuals + +Building PBL Boot Image and boot steps +-------------------------------------- + +1. Building PBL Boot Image. + The default Image is u-boot.pbl. + + For eSPI boot(available on P3041/P4080/P5020): + To build the eSPI boot image: + make <board_name>_SPIFLASH_config + make u-boot.pbl + + For SD boot(available on P3041/P4080/P5020): + To build the SD boot image: + make <board_name>_SDCARD_config + make u-boot.pbl + + For Nand boot(available on P3041/P5020): + To build the NAND boot image: + make <board_name>_NAND_config + make u-boot.pbl + + +2. pblimage support available with mkimage utility will generate Freescale PBL +boot image that can be flashed on the board eSPI flash, SD/MMC and NAND. +Following steps describe it in detail. + + 1). Boot from eSPI flash + Write u-boot.pbl to eSPI flash from offset 0x0. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>sf probe 0 + =>sf erase 0 100000 + =>sf write 100000 0 $filesize + Change SW1[1:5] = off off on off on. + + 2). Boot from SD/MMC + Write u-boot.pbl to SD/MMC from offset 0x1000. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>mmcinfo + =>mmc write 100000 8 441 + Change SW1[1:5] = off off on on off. + + 3). Boot from Nand + Write u-boot.pbl to Nand from offset 0x0. + for ex in u-boot: + =>tftp 100000 u-boot.pbl + =>nand info + =>nand erase 0 100000 + =>nand write 100000 0 $filesize + Change SW1[1:5] = off on off off on + Change SW7[1:4] = on off off on + +Board specific configuration file specifications: +------------------------------------------------ +1. Configuration files rcw.cfg and pbi.cfg must present in the +board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for +PBI instructions. File name must not be changed since they are used +in Makefile. +2. These files can have empty lines and lines starting with "#" as first +character to put comments + +Typical example of rcw.cfg file: +----------------------------------- + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +Typical example of pbi.cfg file: +----------------------------------- + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 + +------------------------------------------------ +Author: Shaohui Xie<Shaohui.Xie(a)freescale.com> diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d0894fd..d3b0222 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -31,6 +31,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw.cfg #endif #ifdef CONFIG_SRIOBOOT_SLAVE diff --git a/include/image.h b/include/image.h index bbf80f0..0913e35 100644 --- a/include/image.h +++ b/include/image.h @@ -164,6 +164,7 @@ #define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */ #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ +#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 64bcc4d..26f4927 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -90,6 +90,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o NOPED_OBJ_FILES-y += aisimage.o NOPED_OBJ_FILES-y += kwbimage.o +NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o @@ -203,6 +204,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \ $(obj)image.o \ $(obj)imximage.o \ $(obj)kwbimage.o \ + $(obj)pblimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index eeb1b10..e43b09f 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -39,6 +39,7 @@ struct mkimage_params params = { .comp = IH_COMP_GZIP, .dtc = MKIMAGE_DEFAULT_DTC_OPTIONS, .imagename = "", + .imagename2 = "", }; /* @@ -150,6 +151,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Freescale PBL Boot image generation/list support */ + init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ init_kwb_image_type (); /* Init Freescale imx Boot image generation/list support */ @@ -250,6 +253,15 @@ main (int argc, char **argv) usage (); params.imagename = *++argv; goto NXTARG; + case 'R': + if (--argc <= 0) + usage(); + /* + * This entry is for the second configuration + * file, if only one is not enough. + */ + params.imagename2 = *++argv; + goto NXTARG; case 's': params.skipcpy = 1; break; @@ -440,6 +452,9 @@ NXTARG: ; break; } } + } else if (params.type == IH_TYPE_PBLIMAGE) { + /* PBL has special Image format, implements its' own */ + pbl_load_uboot(ifd, &params); } else { copy_file (ifd, params.datafile, 0); } diff --git a/tools/mkimage.h b/tools/mkimage.h index 5fe1a48..ea45f5c 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -69,6 +69,7 @@ struct mkimage_params { unsigned int addr; unsigned int ep; char *imagename; + char *imagename2; char *datafile; char *imagefile; char *cmdname; @@ -147,6 +148,8 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void pbl_load_uboot(int fd, struct mkimage_params *mparams); +void init_pbl_image_type(void); void init_ais_image_type(void); void init_kwb_image_type (void); void init_imx_image_type (void); diff --git a/tools/pblimage.c b/tools/pblimage.c new file mode 100644 index 0000000..bfb39ca --- /dev/null +++ b/tools/pblimage.c @@ -0,0 +1,328 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "pblimage.h" + +/* + * The PBL can load up to 64 bytes at a time, so we split the U-Boot + * image into 64 byte chunks. PBL needs a command for each piece, of + * the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE + * is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit, + * so it starts from 0x81F80000. + */ +static uint32_t next_pbl_cmd = 0x81F80000; +/* + * need to store all bytes in memory for calculating crc32, then write the + * bytes to image file for PBL boot. + */ +static unsigned char mem_buf[600000]; +static unsigned char *pmem_buf = mem_buf; +static int pbl_size; +static char *fname = "Unknown"; +static int lineno = -1; +static struct pbl_header pblimage_header; + +static union +{ + char c[4]; + unsigned char l; +} endian_test = { {'l', '?', '?', 'b'} }; + +#define ENDIANNESS ((char)endian_test.l) + +static void generate_pbl_cmd(void) +{ + uint32_t val = next_pbl_cmd; + next_pbl_cmd += 0x40; + int i; + + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (val >> (i * 8)) & 0xff; + pbl_size++; + } +} + +static void pbl_fget(size_t size, FILE *stream) +{ + unsigned char c; + while (size && (c = fgetc(stream)) != EOF) { + *pmem_buf++ = c; + pbl_size++; + size--; + } +} + +/* load split u-boot with PBI command 81xxxxxx. */ +static void load_uboot(FILE *fp_uboot) +{ + while (next_pbl_cmd < 0x82000000) { + generate_pbl_cmd(); + pbl_fget(64, fp_uboot); + } +} + +static void check_get_hexval(char *token) +{ + uint32_t hexval; + int i; + + if (!sscanf(token, "%x", &hexval)) { + printf("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit(EXIT_FAILURE); + } + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (hexval >> (i * 8)) & 0xff; + pbl_size++; + } +} + +static void pbl_parser(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + size_t len = 0; + + fname = name; + fd = fopen(name, "r"); + if (fd == NULL) { + printf("Error:%s - Can't open\n", fname); + exit(EXIT_FAILURE); + } + + while ((getline(&line, &len, fd)) > 0) { + lineno++; + token = strtok_r(line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + for (line = token;; line = NULL) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + check_get_hexval(token); + } + } + if (line) + free(line); + fclose(fd); +} + +static uint32_t crc_table[256]; + +static void make_crc_table(void) +{ + uint32_t mask; + int i, j; + uint32_t poly; /* polynomial exclusive-or pattern */ + + /* + * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + * + x11 + x12 + x16 + x22 + x23 + x26 + x32. + */ + poly = 0x04c11db7; + + for (i = 0; i < 256; i++) { + mask = i << 24; + for (j = 0; j < 8; j++) { + if (mask & 0x80000000) + mask = (mask << 1) ^ poly; + else + mask <<= 1; + } + crc_table[i] = mask; + } +} + +unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len) +{ + uint32_t crc32_val = 0xffffffff; + uint32_t xor = 0x0; + int i; + + make_crc_table(); + + for (i = 0; i < len; i++) + crc32_val = (crc32_val << 8) ^ + crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; + + crc32_val = crc32_val ^ xor; + if (crc32_val < 0) { + crc32_val += 0xffffffff; + crc32_val += 1; + } + return crc32_val; +} + +static uint32_t reverse_byte(uint32_t val) +{ + uint32_t temp; + unsigned char *p1; + int j; + + temp = val; + p1 = (unsigned char *)&temp; + for (j = 3; j >= 0; j--) + *p1++ = (val >> (j * 8)) & 0xff; + return temp; +} + +/* write end command and crc command to memory. */ +static void add_end_cmd(void) +{ + uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, + 0x091380c0, 0x00000000}; + uint32_t crc32_pbl; + int i; + unsigned char *p = (unsigned char *)&pbl_end_cmd; + + if (ENDIANNESS == 'l') { + for (i = 0; i < 4; i++) + pbl_end_cmd[i] = reverse_byte(pbl_end_cmd[i]); + } + + for (i = 0; i < 16; i++) { + *pmem_buf++ = *p++; + pbl_size++; + } + + /* Add PBI CRC command. */ + *pmem_buf++ = 0x08; + *pmem_buf++ = 0x13; + *pmem_buf++ = 0x80; + *pmem_buf++ = 0x40; + pbl_size += 4; + + /* calculated CRC32 and write it to memory. */ + crc32_pbl = pbl_crc32(0, (const char *)mem_buf, pbl_size); + *pmem_buf++ = (crc32_pbl >> 24) & 0xff; + *pmem_buf++ = (crc32_pbl >> 16) & 0xff; + *pmem_buf++ = (crc32_pbl >> 8) & 0xff; + *pmem_buf++ = (crc32_pbl) & 0xff; + pbl_size += 4; + + if ((pbl_size % 16) != 0) { + for (i = 0; i < 8; i++) { + *pmem_buf++ = 0x0; + pbl_size++; + } + } + if ((pbl_size % 16 != 0)) { + printf("Error: Bad size of image file\n"); + exit(EXIT_FAILURE); + } +} + +void pbl_load_uboot(int ifd, struct mkimage_params *params) +{ + FILE *fp_uboot; + int size; + + /* parse the rcw.cfg file. */ + pbl_parser(params->imagename); + + /* parse the pbi.cfg file. */ + pbl_parser(params->imagename2); + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + + load_uboot(fp_uboot); + add_end_cmd(); + fclose(fp_uboot); + lseek(ifd, 0, SEEK_SET); + + size = pbl_size; + if (write(ifd, (const void *)&mem_buf, size) != size) { + fprintf(stderr, "Write error on %s: %s\n", + params->imagefile, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +static int pblimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_PBLIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int pblimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct pbl_header *pbl_hdr = (struct pbl_header *) ptr; + + /* Only a few checks can be done: search for magic numbers */ + if (ENDIANNESS == 'l') { + if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE)) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER)) + return -FDT_ERR_BADSTRUCTURE; + } else { + if (pbl_hdr->preamble != RCW_PREAMBLE) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != RCW_HEADER) + return -FDT_ERR_BADSTRUCTURE; + } + return 0; +} + +static void pblimage_print_header(const void *ptr) +{ + printf("Image Type: Freescale PBL Boot Image\n"); +} + +static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + /*nothing need to do, pbl_load_uboot takes care of whole file. */ +} + +/* pblimage parameters */ +static struct image_type_params pblimage_params = { + .name = "Freescale PBL Boot Image support", + .header_size = sizeof(struct pbl_header), + .hdr = (void *)&pblimage_header, + .check_image_type = pblimage_check_image_types, + .verify_header = pblimage_verify_header, + .print_header = pblimage_print_header, + .set_header = pblimage_set_header, +}; + +void init_pbl_image_type(void) +{ + pbl_size = 0; + mkimage_register(&pblimage_params); +} diff --git a/tools/pblimage.h b/tools/pblimage.h new file mode 100644 index 0000000..514a477 --- /dev/null +++ b/tools/pblimage.h @@ -0,0 +1,36 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef PBLIMAGE_H +#define PBLIMAGE_H + +#define RCW_BYTES 64 +#define RCW_PREAMBLE 0xaa55aa55 +#define RCW_HEADER 0x010e0100 + +struct pbl_header { + uint32_t preamble; + uint32_t rcwheader; + uint8_t rcw_data[RCW_BYTES]; +}; + +#endif /* PBLIMAGE_H */ -- 1.7.0.4

3 3

[U-Boot] [PATCH v3]: video: support exynos fimd driver for various exynos series
by Donghwa Lee 09 Aug '12

09 Aug '12

This patch supports exynos fimd driver for various exynos series different from existing it supports only exynos4 chip. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- Changes for v1: - moves exynos_fimd_get_base_offset() to exynos_fb.h Changes for v2: - moves exynos_fimd_get_base_offset() to asm/arch/fb.h to remove compiler warining. - remove useless reserved variable of exynos_fb structure arch/arm/include/asm/arch-exynos/fb.h | 25 ++++++++++- drivers/video/exynos_fimd.c | 76 ++++++++++++++++++-------------- 2 files changed, 67 insertions(+), 34 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h index b10b0da..c96683a 100644 --- a/arch/arm/include/asm/arch-exynos/fb.h +++ b/arch/arm/include/asm/arch-exynos/fb.h @@ -23,7 +23,7 @@ #define __ASM_ARM_ARCH_FB_H_ #ifndef __ASSEMBLY__ -struct exynos4_fb { +struct exynos_fb { unsigned int vidcon0; unsigned int vidcon1; unsigned int vidcon2; @@ -154,6 +154,18 @@ struct exynos4_fb { }; #endif +/* LCD IF register offset */ +#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0 +#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000 + +static inline unsigned int exynos_fimd_get_base_offset(void) +{ + if (cpu_is_exynos5()) + return EXYNOS5_LCD_IF_BASE_OFFSET; + else + return EXYNOS4_LCD_IF_BASE_OFFSET; +} + /* * Register offsets */ @@ -253,6 +265,8 @@ struct exynos4_fb { /* VIDTCON2 */ #define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) #define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23) +#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22) /* Window 0~4 Control - WINCONx */ #define EXYNOS_WINCON_DATAPATH_DMA (0 << 22) @@ -330,6 +344,8 @@ struct exynos4_fb { #define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) #define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) #define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) +#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23) +#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22) /* VIDOSD0C, VIDOSDxD */ #define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) @@ -354,6 +370,8 @@ struct exynos4_fb { /* Buffer Size */ #define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) #define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) +#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27) +#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26) /* WIN Color Map */ #define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff) @@ -443,4 +461,9 @@ struct exynos4_fb { #define EXYNOS_I80START_TRIG (1 << 1) #define EXYNOS_I80STATUS_TRIG_DONE (1 << 2) +/* DP_MIE_CLKCON */ +#define EXYNOS_DP_MIE_DISABLE (0 << 0) +#define EXYNOS_DP_CLK_ENABLE (1 << 1) +#define EXYNOS_MIE_CLK_ENABLE (3 << 0) + #endif /* _REGS_FB_H */ diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index f07568a..9aaa2c7 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -41,8 +41,8 @@ void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, static void exynos_fimd_set_dualrgb(unsigned int enabled) { - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); unsigned int cfg = 0; if (enabled) { @@ -60,8 +60,8 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled) static void exynos_fimd_set_par(unsigned int win_id) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); /* set window control */ cfg = readl((unsigned int)&fimd_ctrl->wincon0 + @@ -93,7 +93,10 @@ static void exynos_fimd_set_par(unsigned int win_id) EXYNOS_VIDOSD(win_id)); cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) | - EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1); + EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) | + EXYNOS_VIDOSD_RIGHT_X_E(1) | + EXYNOS_VIDOSD_BOTTOM_Y_E(0); + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b + EXYNOS_VIDOSD(win_id)); @@ -106,8 +109,8 @@ static void exynos_fimd_set_par(unsigned int win_id) static void exynos_fimd_set_buffer_address(unsigned int win_id) { unsigned long start_addr, end_addr; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); start_addr = (unsigned long)lcd_base_addr; end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * @@ -124,8 +127,8 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid) unsigned int cfg = 0, div = 0, remainder, remainder_div; unsigned long pixel_clock; unsigned long long src_clock; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); if (pvid->dual_lcd_enabled) { pixel_clock = pvid->vl_freq * @@ -153,9 +156,6 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid) cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED); - if (pixel_clock > MAX_CLOCK) - pixel_clock = MAX_CLOCK; - src_clock = (unsigned long long) get_lcd_clk(); /* get quotient and remainder. */ @@ -180,8 +180,8 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid) void exynos_set_trigger(void) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->trigcon); @@ -194,8 +194,8 @@ int exynos_is_i80_frame_done(void) { unsigned int cfg = 0; int status; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->trigcon); @@ -209,8 +209,8 @@ int exynos_is_i80_frame_done(void) static void exynos_fimd_lcd_on(void) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); /* display on */ cfg = readl(&fimd_ctrl->vidcon0); @@ -221,8 +221,8 @@ static void exynos_fimd_lcd_on(void) static void exynos_fimd_window_on(unsigned int win_id) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); /* enable window */ cfg = readl((unsigned int)&fimd_ctrl->wincon0 + @@ -239,8 +239,8 @@ static void exynos_fimd_window_on(unsigned int win_id) void exynos_fimd_lcd_off(void) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->vidcon0); cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); @@ -250,8 +250,8 @@ void exynos_fimd_lcd_off(void) void exynos_fimd_window_off(unsigned int win_id) { unsigned int cfg = 0; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl((unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id)); @@ -264,11 +264,15 @@ void exynos_fimd_window_off(unsigned int win_id) writel(cfg, &fimd_ctrl->winshmap); } + void exynos_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode; - struct exynos4_fb *fimd_ctrl = - (struct exynos4_fb *)samsung_get_base_fimd(); + unsigned int offset; + struct exynos_fb *fimd_ctrl = + (struct exynos_fb *)samsung_get_base_fimd(); + + offset = exynos_fimd_get_base_offset(); /* store panel info to global variable */ pvid = vid; @@ -297,25 +301,27 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) if (!pvid->vl_dp) cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; - writel(cfg, &fimd_ctrl->vidcon1); + writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset); /* set timing */ cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1); cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1); cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1); - writel(cfg, &fimd_ctrl->vidtcon0); + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset); cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1); cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1); cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1); - writel(cfg, &fimd_ctrl->vidtcon1); + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset); /* set lcd size */ - cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1); - cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1); + cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) | + EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1); - writel(cfg, &fimd_ctrl->vidtcon2); + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset); } /* set display mode */ @@ -331,7 +337,11 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) exynos_fimd_set_buffer_address(pvid->win_id); /* set buffer size */ - cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8); + cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | + EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | + EXYNOS_VIDADDR_OFFSIZE(0) | + EXYNOS_VIDADDR_OFFSIZE_E(0); + writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + EXYNOS_BUFFER_SIZE(pvid->win_id)); -- 1.7.4.1

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