August 2012 - U-Boot

[U-Boot] [PATCH] ARM: Fix malloc area size for versatile and integrator
by Marek Vasut 03 Feb '13

03 Feb '13

These boards couldn't save their environment because they couldn't malloc() the whole size of the sector. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/integratorcp.h | 2 +- include/configs/versatile.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 57610a6..511fa1f 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -56,7 +56,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128*1024) /* * Hardware drivers diff --git a/include/configs/versatile.h b/include/configs/versatile.h index bb835e0..6a9aa30 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -71,7 +71,7 @@ * Size of malloc() pool */ #define CONFIG_ENV_SIZE 8192 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128 * 1024) /* * Hardware drivers -- 1.7.9

3 5

[U-Boot] [PATCH V1 1/3] phy: add phy_connect_by_mask
by Troy Kisky 28 Jan '13

28 Jan '13

It is useful to be able to try a range of possible phy addresses to connect. Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- v2: no change --- drivers/net/phy/phy.c | 108 +++++++++++++++++++++++++++++++------------------ include/phy.h | 2 + 2 files changed, 71 insertions(+), 39 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index baef60f..a22d2e0 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -31,6 +31,7 @@ #include <miiphy.h> #include <phy.h> #include <errno.h> +#include <linux/err.h> /* Generic PHY support and helper functions */ @@ -573,6 +574,61 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) return 0; } +static struct phy_device *create_phy_by_mask(struct mii_dev *bus, + unsigned phy_mask, int devad, phy_interface_t interface) +{ + u32 phy_id = 0xffffffff; + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + int r = get_phy_id(bus, addr, devad, &phy_id); + if (r < 0) + return ERR_PTR(r); + /* If the PHY ID is mostly f's, we didn't find anything */ + if ((phy_id & 0x1fffffff) != 0x1fffffff) + return phy_device_create(bus, addr, phy_id, interface); + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *search_for_existing_phy(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + /* If we have one, return the existing device, with new interface */ + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + if (bus->phymap[addr]) { + bus->phymap[addr]->interface = interface; + return bus->phymap[addr]; + } + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + int i; + struct phy_device *phydev; + + phydev = search_for_existing_phy(bus, phy_mask, interface); + if (phydev) + return phydev; + /* Try Standard (ie Clause 22) access */ + /* Otherwise we have to try Clause 45 */ + for (i = 0; i < 5; i++) { + phydev = create_phy_by_mask(bus, phy_mask, + i ? i : MDIO_DEVAD_NONE, interface); + if (IS_ERR(phydev)) + return NULL; + if (phydev) + return phydev; + } + printf("Phy not found\n"); + return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface); +} + /** * get_phy_device - reads the specified PHY device and returns its @phy_device struct * @bus: the target MII bus @@ -584,38 +640,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) struct phy_device *get_phy_device(struct mii_dev *bus, int addr, phy_interface_t interface) { - u32 phy_id = 0x1fffffff; - int i; - int r; - - /* If we have one, return the existing device, with new interface */ - if (bus->phymap[addr]) { - bus->phymap[addr]->interface = interface; - - return bus->phymap[addr]; - } - - /* Try Standard (ie Clause 22) access */ - r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id); - if (r) - return NULL; - - /* If the PHY ID is mostly f's, we didn't find anything */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) - return phy_device_create(bus, addr, phy_id, interface); - - /* Otherwise we have to try Clause 45 */ - for (i = 1; i < 5; i++) { - r = get_phy_id(bus, addr, i, &phy_id); - if (r) - return NULL; - - /* If the phy_id is mostly Fs, there is no device there */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) - break; - } - - return phy_device_create(bus, addr, phy_id, interface); + return get_phy_device_by_mask(bus, 1 << addr, interface); } int phy_reset(struct phy_device *phydev) @@ -688,9 +713,8 @@ int miiphy_reset(const char *devname, unsigned char addr) return phy_reset(phydev); } -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) +struct phy_device *phy_connect_by_mask(struct mii_dev *bus, unsigned phy_mask, + struct eth_device *dev, phy_interface_t interface) { struct phy_device *phydev; @@ -701,11 +725,11 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, /* Wait 15ms to make sure the PHY has come out of hard reset */ udelay(15000); - phydev = get_phy_device(bus, addr, interface); + phydev = get_phy_device_by_mask(bus, phy_mask, interface); if (!phydev) { - printf("Could not get PHY for %s:%d\n", bus->name, addr); - + printf("Could not get PHY for %s: phy mask %x\n", + bus->name, phy_mask); return NULL; } @@ -714,7 +738,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, if (phydev->dev) printf("%s:%d is connected to %s. Reconnecting to %s\n", - bus->name, addr, phydev->dev->name, dev->name); + bus->name, phydev->addr, phydev->dev->name, dev->name); phydev->dev = dev; @@ -723,6 +747,12 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, return phydev; } +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, phy_interface_t interface) +{ + return phy_connect_by_mask(bus, 1 << addr, dev, interface); +} + /* * Start the PHY. Returns 0 on success, or a negative error code. */ diff --git a/include/phy.h b/include/phy.h index 3c30f11..aea462f 100644 --- a/include/phy.h +++ b/include/phy.h @@ -202,6 +202,8 @@ int phy_reset(struct phy_device *phydev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, phy_interface_t interface); +struct phy_device *phy_connect_by_mask(struct mii_dev *bus, unsigned phy_mask, + struct eth_device *dev, phy_interface_t interface); int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); -- 1.7.9.5

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Re: [U-Boot] Nand flash R/W,saveenv issue..
by Marek Vasut 25 Jan '13

25 Jan '13

Dear Manukumar, > Hello, CCing someone who might actually help you, CCing the uboot mailing list, please keep it that way. > i can able to detect nand flash. > but i had an issue that i could not do operation(Read/write) > on nand flash. > i tried to erase the nand flash i got the error as below: > > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > > even if i try to saveenv then also is not saving the envionment > variables > > processor used: P1012 > nand flash: samsung K9F5608U0D > > please reply ASAP. > > manukumar > signal-networks Best regards, Marek Vasut

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[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

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[U-Boot] Read-only env variables
by Joe Hershberger 15 Jan '13

15 Jan '13

Hi u-boot, I see u-boot supports readonly serial# and ethaddr, but I have a few other variables that I need to be read-only. I'm planning to implement a generic list of variables that cannot be changed or deleted. I'm interested to know what sort of specification people would find most appropriate. My current thought is to follow the same delimiter as the env itself, i.e. null separated list with double null terminator. This list would then be defined in the board config header. It also seems that you should be able to specify simple access rules for each variable name perhaps using "=<val>" after each var name where <val> could have constants (probably numbers for performance, but could be string literals) to define modes. Right now I'm thinking read-only, create-only, change-default, and change-only (i.e no delete) are the modes that make sense. I'm also interested if anyone would be opposed to simply using this new specification of readonly vars to implement the serial# and ethaddr protection. The CONFIG_HAS_UID is a bit odd... should that be available in general for read-only vars? Comments? Thanks, -Joe

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[U-Boot] [PATCH v3] davinci: cleanup davinci_sync_env_enetaddr() fucntion
by Manjunath Hadli 14 Jan '13

14 Jan '13

check for the return status for eth_getenv_enetaddr_by_index() and eth_setenv_enetaddr() functions and print appropriate message on failure. Signed-off-by: Manjunath Hadli <manjunath.hadli(a)ti.com> Cc: Tom Rini <trini(a)ti.com> Cc: Mike Frysinger <vapier(a)gentoo.org> Cc: Wolfgang Denk <wd(a)denx.de> --- Changes for v3: undo conversion of debug statement to printf(). Changes for v2: Removed additional check of comparing ethernet address is all zeros, As the core code already calls is_valid_ether_addr() and one of the checks in there is for all zeros. arch/arm/cpu/arm926ejs/davinci/misc.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c index 5f510b6..c310c69 100644 --- a/arch/arm/cpu/arm926ejs/davinci/misc.c +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -101,9 +101,10 @@ void davinci_emac_mii_mode_sel(int mode_sel) void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) { uint8_t env_enetaddr[6]; + int ret; - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (ret) { /* * There is no MAC address in the environment, so we * initialize it from the value in the EEPROM. @@ -111,8 +112,10 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); + ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); } + if (!ret) + printf("Failed to set mac address from EEPROM\n"); } #endif /* CONFIG_DRIVER_TI_EMAC */ -- 1.6.2.4

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[U-Boot] [PATCH V2 1/1] mx31/mx35/mx51/mx53/mx6: add watchdog
by Troy Kisky 13 Jan '13

13 Jan '13

Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- v2: add README.watchdog include mx31/mx35 watchdogs move to drivers/watchdog Please test on a mx31 and mx35 board. qong and mx31pdk would be best!! --- arch/arm/cpu/arm1136/mx31/timer.c | 39 ----------------- arch/arm/cpu/arm1136/mx35/generic.c | 6 --- arch/arm/cpu/armv7/imx-common/cpu.c | 5 --- arch/arm/include/asm/arch-mx31/clock.h | 2 - arch/arm/include/asm/arch-mx31/imx-regs.h | 15 +------ arch/arm/include/asm/arch-mx35/imx-regs.h | 12 +----- arch/arm/include/asm/arch-mx5/imx-regs.h | 11 +---- arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + board/davedenx/qong/qong.c | 9 +--- board/freescale/mx31pdk/mx31pdk.c | 9 +--- board/hale/tt01/tt01.c | 2 +- doc/README.watchdog | 33 +++++++++++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/imx_watchdog.c | 66 +++++++++++++++++++++++++++++ include/configs/mx31pdk.h | 1 + include/configs/qong.h | 1 + include/watchdog.h | 1 + 17 files changed, 112 insertions(+), 102 deletions(-) create mode 100644 doc/README.watchdog create mode 100644 drivers/watchdog/imx_watchdog.c diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index 72081a8..d6c52d7 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -161,42 +161,3 @@ ulong get_tbclk(void) { return CONFIG_MX31_CLK32; } - -void reset_cpu(ulong addr) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; - wdog->wcr = WDOG_ENABLE; - while (1) - ; -} - -#ifdef CONFIG_HW_WATCHDOG -void mxc_hw_watchdog_enable(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; - u16 secs; - - /* - * The timer watchdog can be set between - * 0.5 and 128 Seconds. If not defined - * in configuration file, sets 64 Seconds - */ -#ifdef CONFIG_SYS_WD_TIMER_SECS - secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF; - if (!secs) secs = 1; -#else - secs = 64; -#endif - setbits_le16(&wdog->wcr, (secs << WDOG_WT_SHIFT) | WDOG_ENABLE - | WDOG_WDZST); -} - - -void mxc_hw_watchdog_reset(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; - - writew(0x5555, &wdog->wsr); - writew(0xAAAA, &wdog->wsr); -} -#endif diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index ea1f730..1af870c 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -495,9 +495,3 @@ int get_clocks(void) #endif return 0; } - -void reset_cpu(ulong addr) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writew(4, &wdog->wcr); -} diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index fa1d468..ebded87 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -122,11 +122,6 @@ int cpu_mmc_init(bd_t *bis) } #endif -void reset_cpu(ulong addr) -{ - __raw_writew(4, WDOG1_BASE_ADDR); -} - u32 get_ahb_clk(void) { struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 852c19c..6cb2611 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -43,7 +43,5 @@ extern void mx31_set_gpr(enum iomux_gp_func gp, char en); void mx31_uart1_hw_init(void); void mx31_uart2_hw_init(void); void mx31_spi2_hw_init(void); -void mxc_hw_watchdog_enable(void); -void mxc_hw_watchdog_reset(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index bba37ac..594d613 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -68,17 +68,6 @@ struct cspi_regs { u32 test; }; -/* Watchdog Timer (WDOG) registers */ -#define WDOG_ENABLE (1 << 2) -#define WDOG_WT_SHIFT 8 -#define WDOG_WDZST (1 << 0) - -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ -}; - /* IIM Control Registers */ struct iim_regs { u32 iim_stat; @@ -673,8 +662,8 @@ struct esdc_regs { #define ARM_PPMRR 0x40000015 -#define WDOG_BASE 0x53FDC000 - +#define WDOG1_BASE_ADDR 0x53FDC000 +#define CONFIG_IMX_WATCHDOG /* cpu_reset implemented in watchdog */ /* * GPIO */ diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index b18b984..45b331f 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -76,7 +76,8 @@ #define GPIO2_BASE_ADDR 0x53FD0000 #define SDMA_BASE_ADDR 0x53FD4000 #define RTC_BASE_ADDR 0x53FD8000 -#define WDOG_BASE_ADDR 0x53FDC000 +#define WDOG1_BASE_ADDR 0x53FDC000 +#define CONFIG_IMX_WATCHDOG /* cpu_reset implemented in watchdog */ #define PWM_BASE_ADDR 0x53FE0000 #define RTIC_BASE_ADDR 0x53FEC000 #define IIM_BASE_ADDR 0x53FF0000 @@ -312,15 +313,6 @@ struct cspi_regs { u32 test; }; -/* Watchdog Timer (WDOG) registers */ -struct wdog_regs { - u16 wcr; /* Control */ - u16 wsr; /* Service */ - u16 wrsr; /* Reset Status */ - u16 wicr; /* Interrupt Control */ - u16 wmcr; /* Misc Control */ -}; - struct esdc_regs { u32 esdctl0; u32 esdcfg0; diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index c53465f..caac574 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -78,6 +78,7 @@ #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define CONFIG_IMX_WATCHDOG /* cpu_reset implemented in watchdog */ #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) @@ -216,16 +217,6 @@ */ #define WBED 1 -/* - * WEIM WCR - */ -#define BCM 1 -#define GBCD(x) (((x) & 0x3) << 1) -#define INTEN (1 << 4) -#define INTPOL (1 << 5) -#define WDOG_EN (1 << 8) -#define WDOG_LIMIT(x) (((x) & 0x3) << 9) - #define CS0_128 0 #define CS0_64M_CS1_64M 1 #define CS0_64M_CS1_32M_CS2_32M 2 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index dacb9ea..0f59567 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -115,6 +115,7 @@ #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) +#define CONFIG_IMX_WATCHDOG /* cpu_reset implemented in watchdog */ #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index c41f11d..d45b25c 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -36,13 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - mxc_hw_watchdog_reset(); -} -#endif - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -182,7 +175,7 @@ int board_late_init(void) pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); #ifdef CONFIG_HW_WATCHDOG - mxc_hw_watchdog_enable(); + hw_watchdog_init(); #endif return 0; diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 9f8bc53..54ac961 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -35,13 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - mxc_hw_watchdog_reset(); -} -#endif - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -92,7 +85,7 @@ int board_late_init(void) pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); #ifdef CONFIG_HW_WATCHDOG - mxc_hw_watchdog_enable(); + hw_watchdog_init(); #endif return 0; } diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c index 02e75ed..137c7e9 100644 --- a/board/hale/tt01/tt01.c +++ b/board/hale/tt01/tt01.c @@ -178,7 +178,7 @@ int board_init(void) int board_late_init(void) { #ifdef CONFIG_HW_WATCHDOG - mxc_hw_watchdog_enable(); + hw_watchdog_init(); #endif return 0; diff --git a/doc/README.watchdog b/doc/README.watchdog new file mode 100644 index 0000000..e4e9bd1 --- /dev/null +++ b/doc/README.watchdog @@ -0,0 +1,33 @@ +Watchdog driver general info + +CONFIG_HW_WATCHDOG + This enables hw_watchdog_reset to be called during various loops, + including waiting for a character on a serial port. But it + does not also call hw_watchdog_init. Boards which want this + enabled must call this function in their board file. This split + is useful because some rom's enable the watchdog when downloading + new code, so it must be serviced, but the board would rather it + was off. And, it cannot always be turned off once on. + +CONFIG_WATCHDOG_TIMEOUT_MSECS + Can be used to change the timeout for i.mx31/35/5x/6x. + If not given, will default to maximum timeout. This would + be 128000 msec for i.mx31/35/5x/6x. + +CONFIG_AT91SAM9_WATCHDOG + Available for AT91SAM9 to service the watchdog. + +CONFIG_FTWDT010_WATCHDOG + Available for FTWDT010 to service the watchdog. + +CONFIG_FTWDT010_HW_TIMEOUT + Can be used to change the timeout for FTWDT010. + +CONFIG_IMX_WATCHDOG + Compiles imx_watchdog.c. This is automatically set for i.mx31/35/5x/6x + boards because the file implements reset_cpu. + +CONFIG_IMX_HW_WATCHDOG + Available for i.mx31/35/5x/6x to service the watchdog. This is not + automatically set because some boards (vision2) still need to define + their own hw_watchdog_reset routine. diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5579bf2..71e3c88 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o +COBJS-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c new file mode 100644 index 0000000..3e5ea6d --- /dev/null +++ b/drivers/watchdog/imx_watchdog.c @@ -0,0 +1,66 @@ +/* + * watchdog.c - driver for i.mx on-chip watchdog + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/io.h> +#include <watchdog.h> +#include <asm/arch/imx-regs.h> + +struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +#define WCR_WDZST 0x01 +#define WCR_WDBG 0x02 +#define WCR_WDE 0x04 /* WDOG enable */ +#define WCR_WDT 0x08 +#define WCR_WDW 0x80 +#define SET_WCR_WT(x) (x << 8) + +#ifdef CONFIG_IMX_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + writew(0x5555, &wdog->wsr); + writew(0xaaaa, &wdog->wsr); +} + +void hw_watchdog_init(void) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + u16 timeout; + + /* + * The timer watchdog can be set between + * 0.5 and 128 Seconds. If not defined + * in configuration file, sets 128 Seconds + */ +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 +#endif + timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | + WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); + hw_watchdog_reset(); +} +#endif + +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + writew(WCR_WDE, &wdog->wcr); + writew(0x5555, &wdog->wsr); + writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 7634de7..6c287a7 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -63,6 +63,7 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_HW_WATCHDOG #define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI diff --git a/include/configs/qong.h b/include/configs/qong.h index e824e17..cdde1cb 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -54,6 +54,7 @@ #define CONFIG_MXC_GPIO #define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_HW_WATCHDOG #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 diff --git a/include/watchdog.h b/include/watchdog.h index b959914..328a30b 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -35,6 +35,7 @@ * Hardware watchdog */ #ifdef CONFIG_HW_WATCHDOG + void hw_watchdog_init(void); #if defined(__ASSEMBLY__) #define WATCHDOG_RESET bl hw_watchdog_reset #else -- 1.7.9.5

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[U-Boot] Pull request for u-boot-marvell.git
by Prafulla Wadaskar 10 Jan '13

10 Jan '13

Dear Albert Please kindly pull The following changes since commit ca849aa4b86b282f837c58a0b129460ebfad2239: David MÃ¼ller (ELSOFT AG) (1): ARM: activate DISPLAY_CPUINFO for VCMA9 + SMDK2410 board are available in the git repository at: u-boot-marvell.git master branch. Albert ARIBAUD (5): edminiv2: add hush parser, cmdline editing and long help Rename ehci-kirkwood as ehci-marvell Remove kirkwood-specifics from marvell EHCI driver orion5x: add USB host ehci-marvell support edminiv2: add USB host support Holger Brunck (2): arm/km: speed up i2c access for keymile boards arm/km: checkpatch cleanup Ian Campbell (1): kirkwood_spi: correct access to irq_mask register Michael Walle (1): arm, arm-kirkwood: disable l2c before linux boot Prafulla Wadaskar (1): bugfix: all Marvell specific build fails due to undefined reference to `get_ticks' Stefan (1): kirkwood: add support for D-Link DNS-325 MAINTAINERS | 4 + arch/arm/cpu/arm926ejs/armada100/timer.c | 18 ++ arch/arm/cpu/arm926ejs/cache.c | 9 + arch/arm/cpu/arm926ejs/cpu.c | 2 + arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 + arch/arm/cpu/arm926ejs/kirkwood/cache.c | 34 ++++ arch/arm/cpu/arm926ejs/kirkwood/timer.c | 18 ++ arch/arm/cpu/arm926ejs/orion5x/timer.c | 18 ++ arch/arm/cpu/arm926ejs/pantheon/timer.c | 18 ++ arch/arm/include/asm/arch-kirkwood/config.h | 2 +- arch/arm/include/asm/arch-kirkwood/kirkwood.h | 12 ++ arch/arm/include/asm/arch-orion5x/orion5x.h | 12 ++ board/d-link/dns325/Makefile | 49 +++++ board/d-link/dns325/dns325.c | 148 ++++++++++++++ board/d-link/dns325/dns325.h | 48 +++++ board/d-link/dns325/kwbimage.cfg | 208 ++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 23 +-- boards.cfg | 1 + drivers/spi/kirkwood_spi.c | 2 +- drivers/usb/host/Makefile | 2 +- .../usb/host/{ehci-kirkwood.c => ehci-marvell.c} | 36 ++-- include/configs/dns325.h | 188 ++++++++++++++++++ include/configs/edminiv2.h | 24 +++ include/configs/km/km_arm.h | 2 +- 24 files changed, 849 insertions(+), 30 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c create mode 100644 board/d-link/dns325/Makefile create mode 100644 board/d-link/dns325/dns325.c create mode 100644 board/d-link/dns325/dns325.h create mode 100644 board/d-link/dns325/kwbimage.cfg rename drivers/usb/host/{ehci-kirkwood.c => ehci-marvell.c} (73%) create mode 100644 include/configs/dns325.h Regards.. Prafulla . . .

4 47

[U-Boot] Secure update of uboot devices?
by Andreas Bäck 08 Jan '13

08 Jan '13

With the new threats like Stuxnet and Duqu one need to improve on how new updates to software is distrubuted to devcies so one can be sure that it's not a hacked or modified software that runs in the device. We use uboot + usb stick to update the software in our devices. Have anyone been trying out to add e.g cryptated,certificates or rsa keys to uboot?

5 6

[U-Boot] [PATCH 00/13] mxc nand: Add support for i.MX5
by Benoît Thébaudeau 08 Jan '13

08 Jan '13

Hi all, This series aims at adding support for i.MX5 to the mxc nand mtd and spl drivers. It also fixes several issues and cleans up the code a little bit. Best regards, Benoît

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