August 2012 - U-Boot

[U-Boot] [PATCH v3 3/4] mmc: s5p_sdhci: add the set_mmc_clk for cmu control
by Jaehoon Chung 31 Aug '12

31 Aug '12

Samsung SoC use the cmu control to set clock. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/mmc/s5p_sdhci.c | 3 +++ drivers/mmc/sdhci.c | 3 +++ include/configs/trats.h | 1 + include/sdhci.h | 2 ++ 4 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 9378e36..b978236 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -21,6 +21,7 @@ #include <malloc.h> #include <sdhci.h> #include <asm/arch/mmc.h> +#include <asm/arch/clk.h> static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -87,6 +88,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->set_control_reg = &s5p_sdhci_set_control_reg; + host->set_clock = set_mmc_clk; + host->index = index; host->host_caps = MMC_MODE_HC; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1709643..ac39e48 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -279,6 +279,9 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } div >>= 1; + if (host->set_clock) + host->set_clock(host->index, div); + clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; diff --git a/include/configs/trats.h b/include/configs/trats.h index d2dfc9f..799658f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -76,6 +76,7 @@ #define CONFIG_MMC #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI +#define CONFIG_MMC_SDMA /* PWM */ #define CONFIG_PWM diff --git a/include/sdhci.h b/include/sdhci.h index 9d37183..4351a62 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -248,8 +248,10 @@ struct sdhci_host { unsigned int clock; struct mmc *mmc; const struct sdhci_ops *ops; + int index; void (*set_control_reg)(struct sdhci_host *host); + void (*set_clock)(int dev_index, unsigned int div); uint voltages; }; -- 1.7.4.1

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[U-Boot] [PATCH v3 2/4] mmc: s5p_sdhci: fixed wrong function argument
by Jaehoon Chung 31 Aug '12

31 Aug '12

Useless code is removed, and get buswidth value. buswidth value will be used to choice the 4bit or 8bit. (Now used 4bit mode in sdhci.c by default) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungin.park(a)samsung.com> --- arch/arm/include/asm/arch-exynos/mmc.h | 4 ++-- arch/arm/include/asm/arch-s5pc1xx/mmc.h | 4 ++-- drivers/mmc/s5p_sdhci.c | 5 ++--- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 0f701c9..afdfcf0 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index 0f701c9..afdfcf0 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 6a04bd7..9378e36 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -69,7 +69,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) +int s5p_sdhci_init(u32 regbase, int index, int bus_width) { struct sdhci_host *host = NULL; host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); @@ -80,7 +80,6 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->name = S5P_NAME; host->ioaddr = (void *)regbase; - host->quirks = quirks; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR; @@ -91,6 +90,6 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->host_caps = MMC_MODE_HC; - add_sdhci(host, max_clk, min_clk); + add_sdhci(host, 52000000, 400000); return 0; } -- 1.7.4.1

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[U-Boot] [PATCH v3 1/4] mmc: s5p_sdhci: set the SDHCI_QUIRK_BROKEN_R1B
by Jaehoon Chung 31 Aug '12

31 Aug '12

Samsung SoC is broken busy waiting for R1b type. And clk delay control value is modified the previosuly value. (that value used at the s5p_mmc.c) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/mmc/s5p_sdhci.c | 10 ++++------ 1 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 1d4481b..6a04bd7 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -54,7 +54,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) * 00 = Delay3 (inverter delay) * 10 = Delay4 (inverter delay + 2ns) */ - val = SDHCI_CTRL3_FCSEL3 | SDHCI_CTRL3_FCSEL1; + val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1; sdhci_writel(host, val, SDHCI_CONTROL3); /* @@ -82,12 +82,10 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->ioaddr = (void *)regbase; host->quirks = quirks; - host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE; + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - if (quirks & SDHCI_QUIRK_REG32_RW) - host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; - else - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->set_control_reg = &s5p_sdhci_set_control_reg; -- 1.7.4.1

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[U-Boot] [PATCH v3 0/4] mmc: sdhci: fixed some problems for Exynos
by Jaehoon Chung 31 Aug '12

31 Aug '12

To use SDHCI for Samsung-SoC, Some problem is fixed.(read/write problem) See the below mmcinfo message: 1. eMMC card: Device: SAMSUNG SDHCI Manufacturer ID: 15 OEM: 100 Name: VYL00 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.0 High Capacity: Yes Capacity: 14.7 GiB Bus Width: 4-bit 2. SD-card Device: SAMSUNG SDHCI Manufacturer ID: 3 OEM: 5344 Name: SU04G Tran Speed: 25000000 Rd Block Len: 512 SD version 2.0 High Capacity: Yes Capacity: 3.7 GiB Bus Width: 4-bit Changelog v3: - increased the timeout and udelay's value instead of adding udelay. Changelog v2: - Add the patch "mmc: sdhci: add the udelay for completed post-request" Jaehoon Chung (4): mmc: s5p_sdhci: set the SDHCI_QUIRK_BROKEN_R1B mmc: s5p_sdhci: fixed wrong function argument mmc: s5p_sdhci: add the set_mmc_clk for cmu control mmc: sdhci: increase the timeout and udelay value arch/arm/include/asm/arch-exynos/mmc.h | 4 ++-- arch/arm/include/asm/arch-s5pc1xx/mmc.h | 4 ++-- drivers/mmc/s5p_sdhci.c | 18 +++++++++--------- drivers/mmc/sdhci.c | 7 +++++-- include/configs/trats.h | 1 + include/sdhci.h | 2 ++ 6 files changed, 21 insertions(+), 15 deletions(-) -- 1.7.4.1

1 0

[U-Boot] [PATCH v2 2/4] mmc: s5p_mmc: fixed wrong function argument
by Jaehoon Chung 31 Aug '12

31 Aug '12

Useless code is removed, and get buswidth value. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/include/asm/arch-exynos/mmc.h | 4 ++-- arch/arm/include/asm/arch-s5pc1xx/mmc.h | 4 ++-- drivers/mmc/s5p_sdhci.c | 9 ++++----- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 0f701c9..afdfcf0 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index 0f701c9..afdfcf0 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -64,11 +64,11 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); +int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline unsigned int s5p_mmc_init(int index, int bus_width) { unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return s5p_sdhci_init(base, 52000000, 400000, index); + return s5p_sdhci_init(base, index, bus_width); } #endif diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 12b28dd..d7e92a4 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -69,7 +69,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) sdhci_writel(host, ctrl, SDHCI_CONTROL2); } -int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) +int s5p_sdhci_init(u32 regbase, int index, int bus_width) { struct sdhci_host *host = NULL; host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); @@ -80,12 +80,11 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->name = S5P_NAME; host->ioaddr = (void *)regbase; - host->quirks = quirks; - host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - if (quirks & SDHCI_QUIRK_REG32_RW) + if (host->quirks & SDHCI_QUIRK_REG32_RW) host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; else host->version = sdhci_readw(host, SDHCI_HOST_VERSION); @@ -94,6 +93,6 @@ int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->host_caps = MMC_MODE_HC; - add_sdhci(host, max_clk, min_clk); + add_sdhci(host, 52000000, 400000); return 0; } -- 1.7.4.1

2 2

[U-Boot] [PATCH 0/2] PXA25x: USB ethernet driver
by Łukasz Dałek 31 Aug '12

31 Aug '12

I've moved cpu revision detection to arch/arm/cpu/pxa as you suggest. Cleaned ethernet driver. Soon I would also send patches for drivers/usb/gadget/ether.c to work correctly with this pxa driver. Łukasz Dałek (2): pxa: Add some stuff to examine cpu model and rev pxa25x: Add USB ethernet gadget arch/arm/cpu/pxa/cpuinfo.c | 11 +- arch/arm/include/asm/arch-pxa/pxa.h | 13 + drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/pxa25x_udc.c | 2059 +++++++++++++++++++++++++++++++++++ drivers/usb/gadget/pxa25x_udc.h | 168 +++ 5 files changed, 2250 insertions(+), 2 deletions(-) create mode 100644 drivers/usb/gadget/pxa25x_udc.c create mode 100644 drivers/usb/gadget/pxa25x_udc.h -- 1.7.8.6

3 10

[U-Boot] [PATCH] usb: remove unnecessary packed attributes
by Lucas Stach 30 Aug '12

30 Aug '12

We don't actually need to pack those structs, as they are not used to do actual hardware access. This avoids some unaligned accesses and therefore makes the EHCI stack work on ARMv7 without compiler workarounds. Signed-off-by: Lucas Stach <dev(a)lynxeye.de> --- drivers/usb/host/ehci-hcd.c | 2 +- include/usb.h | 2 +- 2 Dateien geändert, 2 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 18b4bc6..2f4fa5e 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -45,7 +45,7 @@ static struct descriptor { struct usb_linux_config_descriptor config; struct usb_linux_interface_descriptor interface; struct usb_endpoint_descriptor endpoint; -} __attribute__ ((packed)) descriptor = { +} descriptor = { { 0x8, /* bDescLength */ 0x29, /* bDescriptorType: hub descriptor */ diff --git a/include/usb.h b/include/usb.h index ba3d169..63730ee 100644 --- a/include/usb.h +++ b/include/usb.h @@ -369,7 +369,7 @@ struct usb_hub_descriptor { unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8]; /* DeviceRemovable and PortPwrCtrlMask want to be variable-length bitmaps that hold max 255 entries. (bit0 is ignored) */ -} __attribute__ ((packed)); +}; struct usb_hub_device { -- 1.7.11.4

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[U-Boot] [PATCH v2 4/4] mmc: sdhci: add the udelay for completed post-request
by Jaehoon Chung 30 Aug '12

30 Aug '12

To ensure that complete the request, add udelay(100). Also increased the timeout value to 10000. (Because timeout value is short, there is the case that didn't transfer data) Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sdhci.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index ac39e48..f71a14b 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -83,7 +83,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, { unsigned int stat, rdy, mask, timeout, block = 0; - timeout = 10000; + timeout = 100000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; do { @@ -239,6 +239,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !is_aligned && (data->flags == MMC_DATA_READ)) memcpy(data->dest, aligned_buffer, trans_bytes); + udelay(100); return 0; } -- 1.7.4.1

2 1

[U-Boot] [PATCH v2 3/4] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
by Jaehoon Chung 30 Aug '12

30 Aug '12

Support DesignWare MMC Controller for Samsung Specific. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> Signed-off-by: Rajeshawari Shinde <rajeshwari.s(a)samsung.com> --- arch/arm/include/asm/arch-exynos/dwmmc.h | 36 ++++++++++++++++++ drivers/mmc/exynos_dw_mmc.c | 58 ++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h create mode 100644 drivers/mmc/exynos_dw_mmc.c diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h new file mode 100644 index 0000000..8acdf9b --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DWMCI_CLKSEL 0x09C +#define DWMCI_SHIFT_0 0x0 +#define DWMCI_SHIFT_1 0x1 +#define DWMCI_SHIFT_2 0x2 +#define DWMCI_SHIFT_3 0x3 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +int exynos_dwmci_init(u32 regbase, int bus_width, int index); + +static inline unsigned int exynos_dwmmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return exynos_dwmci_init(base, bus_width, index); +} diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c new file mode 100644 index 0000000..286a7df --- /dev/null +++ b/drivers/mmc/exynos_dw_mmc.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <dwmmc.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/clk.h> + +static char *EXYNOS_NAME = "EXYNOS DWMMC"; + +static void exynos_dwmci_clksel(struct dwmci_host *host) +{ + u32 val; + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + + dwmci_writel(host, DWMCI_CLKSEL, val); +} + +int exynos_dwmci_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = (struct dwmci_host *)malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + host->name = EXYNOS_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = exynos_dwmci_clksel; + host->dev_index = index; + host->mmc_clk = get_mmc_clk; + + add_dwmci(host, 52000000, 400000, index); + + return 0; +} +

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[U-Boot] [PATCH 2/4] EXYNOS: clock: add the get_mmc_clk function
by Jaehoon Chung 30 Aug '12

30 Aug '12

To get more exactly sclk value, used the get_mmc_clk. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 78 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 79 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2f7048b..90fa45c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -360,6 +360,44 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos4: return mmc clock frequency */ +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + if (dev_index == 0) { + ratio = readl(&clk->div_fsys0); + pre_ratio = readl(&clk->div_fsys0); + } else if (dev_index == 4) { + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + } else + return 0; + + ratio = ratio & 0xf; + pre_ratio = (pre_ratio >> (dev_index + 8)) & 0xff; + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -387,6 +425,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: return mmc clock frequency */ +static unsigned long exynos5_get_mmc_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index << 2)) & 0xf; + pre_ratio = readl(&clk->div_fsys1); + pre_ratio = (pre_ratio >> ((dev_index<< 4) + 8)) & 0xff; + + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos5: set the mmc clock */ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { @@ -446,6 +516,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) + return exynos5_get_mmc_clk(dev_index); + else + return exynos4_get_mmc_clk(dev_index); +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index ff0f641..9e9d390 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -31,6 +31,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); +unsigned long get_mmc_clk(int dev_index); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);

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