May 2012 - U-Boot

[U-Boot] [PATCH] USB: ehci-mx6: Fix broken IO access
by Wolfgang Grandegger 06 May '12

06 May '12

To get USB working again on the i.MX6, this patch fixes a bug introduced with commit 522b2a0 "Add proper IO accessors for mx6 usb registers.". At that occasion, I also added the missing __iomem directive. Cc: Marek Vasut <marex(a)denx.de> CC: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Wolfgang Grandegger <wg(a)denx.de> --- drivers/usb/host/ehci-mx6.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 5dec673..42c77fe 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -73,7 +73,8 @@ static void usbh1_internal_phy_clock_gate(int on) static void usbh1_power_config(void) { - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; /* * Some phy and power's special controls for host1 * 1. The external charger detector needs to be disabled @@ -87,7 +88,7 @@ static void usbh1_power_config(void) &anatop->usb2_chrg_detect); __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, - &anatop->usb2_pll_480_ctrl); + &anatop->usb2_pll_480_ctrl_clr); __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | ANADIG_USB2_PLL_480_CTRL_POWER | -- 1.7.7.6

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[U-Boot] [PATCH 1/3] mx5: Add clock config interface
by Fabio Estevam 06 May '12

06 May '12

mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui(a)linaro.org> Signed-off-by: Eric Miao <eric.miao(a)linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Rebased against Stefano's u-boot-imx plus the v2 version of http://marc.info/?l=u-boot&m=133572323109396&w=2 - Fixed console output - Use -EINVAL instead of -1 arch/arm/cpu/armv7/mx5/clock.c | 448 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx5/clock.h | 5 +- arch/arm/include/asm/arch-mx5/crm_regs.h | 6 + 3 files changed, 454 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 903e207..30d86b4 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -49,6 +49,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { #endif }; +#define AHB_CLK_ROOT 133333333 +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +#define MX5_CBCMR 0x00015154 +#define MX5_CBCDR 0x02888945 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[] = { + {CONFIG_SYS_MX5_HCLK, 24 * 16}, +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) +#define PLL_FREQ_MIN(ref_clk) \ + ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define NFC_CLK_MAX 34000000 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; void set_usboh3_clk(void) @@ -291,7 +327,7 @@ static u32 get_uart_clk(void) /* * This function returns the low power audio clock. */ -u32 get_lp_apm(void) +static u32 get_lp_apm(void) { u32 ret_val = 0; u32 ccsr = __raw_readl(&mxc_ccm->ccsr); @@ -307,7 +343,7 @@ u32 get_lp_apm(void) /* * get cspi clock rate. */ -u32 imx_get_cspiclk(void) +static u32 imx_get_cspiclk(void) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); @@ -344,8 +380,77 @@ u32 imx_get_cspiclk(void) return ret_val; } +static u32 get_axi_a_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_axi_b_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_emi_slow_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; + + if (emi_clk_sel) + return get_ahb_clk() / (pdf + 1); + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_ddr_clk(void) +{ + u32 ret_val = 0; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; +#ifdef CONFIG_MX51 + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { + u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \ + MXC_CCM_CBCDR_DDR_PODF_OFFSET; + + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + ret_val /= ddr_clk_podf + 1; + + return ret_val; + } +#endif + switch (ddr_clk_sel) { + case 0: + ret_val = get_axi_a_clk(); + break; + case 1: + ret_val = get_axi_b_clk(); + break; + case 2: + ret_val = get_emi_slow_clk(); + break; + case 3: + ret_val = get_ahb_clk(); + break; + default: + break; + } + + return ret_val; +} + /* - * The API of get mxc clockes. + * The API of get mxc clocks. */ unsigned int mxc_get_clock(enum mxc_clock clk) { @@ -367,10 +472,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) CONFIG_SYS_MX5_HCLK); case MXC_SATA_CLK: return get_ahb_clk(); + case MXC_DDR_CLK: + return get_ddr_clk(); default: break; } - return -1; + return -EINVAL; } u32 imx_get_uartclk(void) @@ -384,6 +491,338 @@ u32 imx_get_fecclk(void) return mxc_get_clock(MXC_IPG_CLK); } +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/* + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -EINVAL; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -EINVAL; + else if (mfi < 5) + continue; + break; + } + /* + * Now got pd and mfi already + * + * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; + debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", + ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +#define calc_div(tgt_clk, src_clk, limit) ({ \ + u32 v = 0; \ + if (((src_clk) % (tgt_clk)) <= 100) \ + v = (src_clk) / (tgt_clk); \ + else \ + v = ((src_clk) / (tgt_clk)) + 1;\ + if (v > limit) \ + v = limit; \ + (v - 1); \ + }) + +#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ + { \ + __raw_writel(0x1232, &pll->ctrl); \ + __raw_writel(0x2, &pll->config); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->op); \ + __raw_writel(fn, &(pll->mfn)); \ + __raw_writel((fd) - 1, &pll->mfd); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->hfs_op); \ + __raw_writel(fn, &pll->hfs_mfn); \ + __raw_writel((fd) - 1, &pll->hfs_mfd); \ + __raw_writel(0x1232, &pll->ctrl); \ + while (!__raw_readl(&pll->ctrl) & 0x1) \ + ;\ + } + +static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) +{ + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + struct mxc_pll_reg *pll = mxc_plls[index]; + + switch (index) { + case PLL1_CLOCK: + /* Switch ARM to PLL2 clock */ + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); + break; + case PLL2_CLOCK: + /* Switch to pll2 bypass clock */ + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); + break; + case PLL3_CLOCK: + /* Switch to pll3 bypass clock */ + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); + break; + case PLL4_CLOCK: + /* Switch to pll4 bypass clock */ + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); + break; + default: + return -EINVAL; + } + + return 0; +} + +/* Config CPU clock */ +static int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", ret); + return ret; + } + + return config_pll_clk(PLL1_CLOCK, &pll_param); +} + +static int config_nfc_clk(u32 nfc_clk) +{ + u32 reg; + u32 parent_rate = get_emi_slow_clk(); + u32 div = parent_rate / nfc_clk; + + if (nfc_clk <= 0) + return -EINVAL; + if (div == 0) + div++; + if (parent_rate / div > NFC_CLK_MAX) + div++; + reg = __raw_readl(&mxc_ccm->cbcdr); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + return 0; +} + +/* Config main_bus_clock for periphs */ +static int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__raw_readl(&mxc_ccm->cbcmr) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLOCK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLOCK, &pll_param); + break; + default: + return -EINVAL; + } + } + + return 0; +} + +static int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + + if (emi_clk > MAX_DDR_CLK) { + printf("Warning:DDR clock should not exceed %d MHz\n", + MAX_DDR_CLK / SZ_DEC_1M); + emi_clk = MAX_DDR_CLK; + } + + clk_src = get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -EINVAL; + } + + if ((clk_src % emi_clk) < 10000000) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + __raw_writel(cbcdr, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + __raw_writel(0x0, &mxc_ccm->ccdr); + + return 0; +} + +/* + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + */ +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) +{ + freq *= SZ_DEC_1M; + + switch (clk) { + case MXC_ARM_CLK: + if (config_core_clk(ref, freq)) + return -EINVAL; + break; + case MXC_PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -EINVAL; + break; + case MXC_DDR_CLK: + if (config_ddr_clk(freq)) + return -EINVAL; + break; + case MXC_NFC_CLK: + if (config_nfc_clk(freq)) + return -EINVAL; + break; + default: + printf("Warning:Unsupported or invalid clock type\n"); + } + + return 0; +} + #ifdef CONFIG_MX53 /* * The clock for the external interface can be set to use internal clock @@ -430,6 +869,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); return 0; } diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index e822809..35ee815 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -33,6 +33,9 @@ enum mxc_clock { MXC_CSPI_CLK, MXC_FEC_CLK, MXC_SATA_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, }; unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); @@ -40,7 +43,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); - +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); void set_usb_phy2_clk(void); void enable_usb_phy2_clk(unsigned char enable); void set_usboh3_clk(void); diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index bdeafbc..4e0fc1b 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -76,6 +76,9 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif u32 cmeor; }; @@ -84,6 +87,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 /* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 -- 1.7.1

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[U-Boot] USB on mx53loco
by Fabio Estevam 06 May '12

06 May '12

Hi Wolfgang, Have you tested USB host functionality on a mx53loco with a Freescale MC34708 PMIC ? I can succesfully detect a USB pen drive on a mx53loco board with a Dialog PMIC, but not on the FSL PMIC version. I am going to debug this, but just wondering if you have already seen this issue. Thanks, Fabio Estevam

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[U-Boot] mpc85xx: Memory diagnostics run with cache enabled?
by Rajat Jain 05 May '12

05 May '12

Hello List, I'm taking a look at the memory diagnostics, specially for PowerPC mpc85xx family CPUs. It seems to me that currently all the memory diagnostics on mpc85xx are run with cache enabled, and memory mapped using cache-enabled TLB entries. Isn't it true that in such a case all the memory reads / writes would actually land up in cache (unless they are "spaced" out), and the memory diagnostics won't really be reliable? Are the memory diagnostics written with keeping in mind that the cache may be enabled? The diagnostic code (post/drivers/memory.c) does give architecture code (arch/powerpc/cpu/mpc85xx/cpu.c) a chance to prepare for running memory diagnostics, but it does not look like the CPU code is really disabling the cache. What am I missing? Thanks, Rajat

1 0

[U-Boot] [PATCH v5 04/10] input: Add support for keyboard matrix decoding from an fdt
by Simon Glass 04 May '12

04 May '12

From: Bernie Thompson <bhthompson(a)chromium.org> Matrix keyboards require a key map to be set up, and must also deal with key ghosting. Create a keyboard matrix management implementation which can be leveraged by various keyboard drivers. This includes code to read the keymap from the FDT and perform debouncing. Signed-off-by: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - Move matrix keyboard handling into a separate module Changes in v5: - Only bring in matrix keyboard when CONFIG_OF_CONTROL is defined drivers/input/Makefile | 1 + drivers/input/key_matrix.c | 208 ++++++++++++++++++++++++++++++++++++++++++++ include/key_matrix.h | 99 +++++++++++++++++++++ 3 files changed, 308 insertions(+), 0 deletions(-) create mode 100644 drivers/input/key_matrix.c create mode 100644 include/key_matrix.h diff --git a/drivers/input/Makefile b/drivers/input/Makefile index d06acb9..b26055e 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -31,6 +31,7 @@ COBJS-y += keyboard.o pc_keyb.o COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o endif COBJS-y += input.o +COBJS-$(CONFIG_OF_CONTROL) += key_matrix.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c new file mode 100644 index 0000000..84b898f --- /dev/null +++ b/drivers/input/key_matrix.c @@ -0,0 +1,208 @@ +/* + * Manage Keyboard Matrices + * + * Copyright (c) 2012 The Chromium OS Authors. + * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <fdtdec.h> +#include <key_matrix.h> +#include <malloc.h> +#include <linux/input.h> + +/** + * Determine if the current keypress configuration can cause key ghosting + * + * We figure this out by seeing if we have two or more keys in the same + * column, as well as two or more keys in the same row. + * + * @param config Keyboard matrix config + * @param keys List of keys to check + * @param valid Number of valid keypresses to check + * @return 0 if no ghosting is possible, 1 if it is + */ +static int has_ghosting(struct key_matrix *config, struct key_matrix_key *keys, + int valid) +{ + int key_in_same_col = 0, key_in_same_row = 0; + int i, j; + + for (i = 0; i < valid; i++) { + /* + * Find 2 keys such that one key is in the same row + * and the other is in the same column as the i-th key. + */ + for (j = i + 1; j < valid; j++) { + if (keys[j].col == keys[i].col) + key_in_same_col = 1; + if (keys[j].row == keys[i].row) + key_in_same_row = 1; + } + } + + if (key_in_same_col && key_in_same_row) + return 1; + else + return 0; +} + +int key_matrix_decode(struct key_matrix *config, struct key_matrix_key keys[], + int num_keys, int keycode[], int max_keycodes) +{ + const u8 *keymap; + int valid, upto; + int pos; + + debug("%s: num_keys = %d\n", __func__, num_keys); + keymap = config->plain_keycode; + for (valid = upto = 0; upto < num_keys; upto++) { + struct key_matrix_key *key = &keys[upto]; + + debug(" valid=%d, row=%d, col=%d\n", key->valid, key->row, + key->col); + if (!key->valid) + continue; + pos = key->row * config->num_cols + key->col; + if (config->fn_keycode && pos == config->fn_pos) + keymap = config->fn_keycode; + + /* Convert the (row, col) values into a keycode */ + if (valid < max_keycodes) + keycode[valid++] = keymap[pos]; + debug(" keycode=%d\n", keymap[pos]); + } + + /* For a ghost key config, ignore the keypresses for this iteration. */ + if (valid >= 3 && has_ghosting(config, keys, valid)) { + valid = 0; + debug(" ghosting detected!\n"); + } + debug(" %d valid keycodes found\n", valid); + + return valid; +} + +/** + * Create a new keycode map from some provided data + * + * This decodes a keycode map in the format used by the fdt, which is one + * word per entry, with the row, col and keycode encoded in that word. + * + * We create a (row x col) size byte array with each entry containing the + * keycode for that (row, col). We also search for map_keycode and return + * its position if found (this is used for finding the Fn key). + * + * @param config Key matrix dimensions structure + * @param data Keycode data + * @param len Number of entries in keycode table + * @param map_keycode Key code to find in the map + * @param pos Returns position of map_keycode, if found, else -1 + * @return map Pointer to allocated map + */ +static uchar *create_keymap(struct key_matrix *config, u32 *data, int len, + int map_keycode, int *pos) +{ + uchar *map; + + if (pos) + *pos = -1; + map = (uchar *)calloc(1, config->key_count); + if (!map) { + debug("%s: failed to malloc %d bytes\n", __func__, + config->key_count); + return NULL; + } + + for (; len >= sizeof(u32); data++, len -= 4) { + u32 tmp = fdt32_to_cpu(*data); + int key_code, row, col; + int entry; + + row = (tmp >> 24) & 0xff; + col = (tmp >> 16) & 0xff; + key_code = tmp & 0xffff; + entry = row * config->num_cols + col; + map[entry] = key_code; + if (pos && map_keycode == key_code) + *pos = entry; + } + + return map; +} + +int key_matrix_decode_fdt(struct key_matrix *config, const void *blob, + int node) +{ + const struct fdt_property *prop; + int offset; + + /* Check each property name for ones that we understand */ + for (offset = fdt_first_property_offset(blob, node); + offset > 0; + offset = fdt_next_property_offset(blob, offset)) { + const char *name; + int len; + + prop = fdt_get_property_by_offset(blob, offset, NULL); + name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + len = strlen(name); + + /* Name needs to match "1,<type>keymap" */ + debug("%s: property '%s'\n", __func__, name); + if (strncmp(name, "1,", 2) || len < 8 || + strcmp(name + len - 6, "keymap")) + continue; + + len -= 8; + if (len == 0) { + config->plain_keycode = create_keymap(config, + (u32 *)prop->data, fdt32_to_cpu(prop->len), + KEY_FN, &config->fn_pos); + } else if (0 == strncmp(name + 2, "fn-", len)) { + config->fn_keycode = create_keymap(config, + (u32 *)prop->data, fdt32_to_cpu(prop->len), + -1, NULL); + } else { + debug("%s: unrecognised property '%s'\n", __func__, + name); + } + } + debug("%s: Decoded key maps %p, %p from fdt\n", __func__, + config->plain_keycode, config->fn_keycode); + + if (!config->plain_keycode) { + debug("%s: cannot find keycode-plain map\n", __func__); + return -1; + } + + return 0; +} + +int key_matrix_init(struct key_matrix *config, int rows, int cols) +{ + memset(config, '\0', sizeof(*config)); + config->num_rows = rows; + config->num_cols = cols; + config->key_count = rows * cols; + assert(config->key_count > 0); + + return 0; +} diff --git a/include/key_matrix.h b/include/key_matrix.h new file mode 100644 index 0000000..f413314 --- /dev/null +++ b/include/key_matrix.h @@ -0,0 +1,99 @@ +/* + * Keyboard matrix helper functions + * + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KEY_MATRIX_H +#define _KEY_MATRIX_H + +#include <common.h> + +/* Information about a matrix keyboard */ +struct key_matrix { + /* Dimensions of the keyboard matrix, in rows and columns */ + int num_rows; + int num_cols; + int key_count; /* number of keys in the matrix (= rows * cols) */ + + /* + * Information about keycode mappings. The plain_keycode array must + * exist but fn may be NULL in which case it is not decoded. + */ + const u8 *plain_keycode; /* key code for each row / column */ + const u8 *fn_keycode; /* ...when Fn held down */ + int fn_pos; /* position of Fn key in key (or -1) */ +}; + +/* Information about a particular key (row, column pair) in the matrix */ +struct key_matrix_key { + uint8_t row; /* row number (0 = first) */ + uint8_t col; /* column number (0 = first) */ + uint8_t valid; /* 1 if valid, 0 to ignore this */ +}; + +/** + * Decode a set of pressed keys into key codes + * + * Given a list of keys that are pressed, this converts this list into + * a list of key codes. Each of the keys has a valid flag, which can be + * used to mark a particular key as invalid (so that it is ignored). + * + * The plain keymap is used, unless the Fn key is detected along the way, + * at which point we switch to the Fn key map. + * + * If key ghosting is detected, we simply ignore the keys and return 0. + * + * @param config Keyboard matrix config + * @param keys List of keys to process (each is row, col) + * @param num_keys Number of keys to process + * @param keycode Returns a list of key codes, decoded from input + * @param max_keycodes Size of key codes array (suggest 8) + * + */ +int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys, + int num_keys, int keycode[], int max_keycodes); + +/** + * Read the keyboard configuration out of the fdt. + * + * Decode properties of named "linux,<type>keymap" where <type> is either + * empty, or "fn-". Then set up the plain key map (and the FN keymap if + * present). + * + * @param config Keyboard matrix config + * @param blob FDT blob + * @param node Node containing compatible data + * @return 0 if ok, -1 on error + */ +int key_matrix_decode_fdt(struct key_matrix *config, const void *blob, + int node); + +/** + * Set up a new key matrix. + * + * @param config Keyboard matrix config + * @param rows Number of rows in key matrix + * @param cols Number of columns in key matrix + * @return 0 if ok, -1 on error + */ +int key_matrix_init(struct key_matrix *config, int rows, int cols); + +#endif -- 1.7.7.3

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[U-Boot] [PATCH V2] checkpatch: add check for whitespace before semicolon at end-of-line
by Eric Nelson 04 May '12

04 May '12

Requires --strict option during invocation: ~/linux$ scripts/checkpatch --strict foo.patch This tests for a bad habits of mine like this: return 0 ; Note that it does allow a special case of a bare semicolon for empty loops: while (foo()) ; --- V2 adds the special case and requirement for --strict based on recommendations of Joe Perches. scripts/checkpatch.pl | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index a3b9782..e711122 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -3227,6 +3227,12 @@ sub process { "Statements terminations use 1 semicolon\n" . $herecurr); } +# check for whitespace before semicolon - not allowed at end-of-line + if ($line =~ /\S+\s+;$/) { + CHK("SPACING", + "Whitespace before semicolon\n" . $herecurr); + } + # check for gcc specific __FUNCTION__ if ($line =~ /__FUNCTION__/) { WARN("USE_FUNC", -- 1.7.9

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[U-Boot] pull request for u-boot-tegra/master
by Tom Warren 04 May '12

04 May '12

Albert, Please pull u-boot-tegra/master into arm master. Thanks! The following changes since commit 026251a5e825d61d3bcdf6dffcc27d15afd574f4: Donghwa Lee (1): EXYNOS: Change bits per pixel value proper for u-boot. are available in the git repository at: git://git.denx.de/u-boot-tegra master Anton Staff (3): fdt: Add fdtdec functions to read byte array tegra: fdt: Add keyboard controller definition tegra: fdt: Add keyboard definitions for Seaboard Bernie Thompson (1): input: Add support for keyboard matrix decoding from an fdt Jimmy Zhang (3): tegra: Add EMC support for optimal memory timings tegra: Add PMU to manage power supplies tegra: Add EMC settings for Seaboard Rakesh Iyer (1): tegra: Add tegra keyboard driver Simon Glass (19): fdt: Add function to locate an array in the device tree fdt: Add function to return next compatible subnode Add abs() macro to return absolute value i2c: Add TPS6586X driver tegra: Move ap20.h header into arch location tegra: Add functions to access low-level Osc/PLL details tegra: Add tegra_get_chip_type() to detect SKU tegra: Add header file for APB_MISC register tegra: Set up PMU for Nvidia boards tegra: Set up warmboot code on Nvidia boards fdt: tegra: Add EMC node to device tree tegra: i2c: Add function to find DVC bus tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: Enable LP0 on Seaboard input: Add linux/input.h for key code support input: Add generic keyboard input handler tegra: Add keyboard support to funcmux tegra: Switch on console mux and use environment for console tegra: Enable keyboard for Seaboard Wei Ni (1): tegra: Turn off power detect in board init Yen Lin (5): Add AES crypto library tegra: Add crypto library for warmboot code tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add warmboot implementation tegra: Setup PMC scratch info from ap20 setup arch/arm/cpu/armv7/tegra2/Makefile | 4 + arch/arm/cpu/armv7/tegra2/ap20.c | 44 ++- arch/arm/cpu/armv7/tegra2/board.c | 4 +- arch/arm/cpu/armv7/tegra2/clock.c | 32 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 ++++++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 ++ arch/arm/cpu/armv7/tegra2/emc.c | 286 ++++++++++ arch/arm/cpu/armv7/tegra2/funcmux.c | 16 + arch/arm/cpu/armv7/tegra2/pmu.c | 70 +++ arch/arm/cpu/armv7/tegra2/warmboot.c | 386 +++++++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 ++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 +++ arch/arm/dts/tegra20.dtsi | 11 + .../tegra2 => include/asm/arch-tegra2}/ap20.h | 7 + arch/arm/include/asm/arch-tegra2/apb_misc.h | 36 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra2/clock.h | 22 + arch/arm/include/asm/arch-tegra2/emc.h | 113 ++++ arch/arm/include/asm/arch-tegra2/flow.h | 36 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 ++ arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 25 + arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 7 + arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++++ board/nvidia/common/Makefile | 1 + board/nvidia/common/board.c | 42 ++- board/nvidia/common/emc.c | 53 ++ board/nvidia/common/emc.h | 29 + board/nvidia/dts/tegra2-seaboard.dts | 64 +++ drivers/i2c/tegra_i2c.c | 14 + drivers/input/Makefile | 3 + drivers/input/input.c | 429 ++++++++++++++ drivers/input/key_matrix.c | 208 +++++++ drivers/input/tegra-kbc.c | 375 ++++++++++++ drivers/power/Makefile | 1 + drivers/power/tps6586x.c | 280 +++++++++ include/aes.h | 70 +++ include/common.h | 13 + include/configs/seaboard.h | 16 + include/configs/tegra2-common.h | 26 +- include/fdtdec.h | 71 +++ include/input.h | 145 +++++ include/key_matrix.h | 99 ++++ include/linux/input.h | 155 +++++ include/tegra-kbc.h | 33 ++ include/tps6586x.h | 68 +++ lib/Makefile | 1 + lib/aes.c | 598 ++++++++++++++++++++ lib/fdtdec.c | 53 ++ 51 files changed, 4981 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.c create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.h create mode 100644 arch/arm/cpu/armv7/tegra2/emc.c create mode 100644 arch/arm/cpu/armv7/tegra2/pmu.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.h rename arch/arm/{cpu/armv7/tegra2 => include/asm/arch-tegra2}/ap20.h (96%) create mode 100644 arch/arm/include/asm/arch-tegra2/apb_misc.h create mode 100644 arch/arm/include/asm/arch-tegra2/emc.h create mode 100644 arch/arm/include/asm/arch-tegra2/flow.h create mode 100644 arch/arm/include/asm/arch-tegra2/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra2/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra2/sdram_param.h create mode 100644 arch/arm/include/asm/arch-tegra2/warmboot.h create mode 100644 board/nvidia/common/emc.c create mode 100644 board/nvidia/common/emc.h create mode 100644 drivers/input/input.c create mode 100644 drivers/input/key_matrix.c create mode 100644 drivers/input/tegra-kbc.c create mode 100644 drivers/power/tps6586x.c create mode 100644 include/aes.h create mode 100644 include/input.h create mode 100644 include/key_matrix.h create mode 100644 include/linux/input.h create mode 100644 include/tegra-kbc.h create mode 100644 include/tps6586x.h create mode 100644 lib/aes.c

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Re: [U-Boot] [PATCH] OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
by R, Sricharan 04 May '12

04 May '12

Jon, [snip] > --- a/include/configs/omap4_common.h > +++ b/include/configs/omap4_common.h > @@ -151,6 +151,7 @@ > #define CONFIG_EXTRA_ENV_SETTINGS \ > "loadaddr=0x82000000\0" \ > "console=ttyO2,115200n8\0" \ > + "fdt_high=0xffffffff\0" \ Tested this on mainline and worked fine on 4430SDP. Tested the same on u-boot-arm, but did not work there. Not sure what i am missing. Thanks, Sricharan

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[U-Boot] [PATCH] OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
by Jon Hunter 04 May '12

04 May '12

From: Jon Hunter <jon-hunter(a)ti.com> For OMAP4 boards, such as the panda-es, that have 1GB of memory the linux kernel fails to locate the device tree blob on boot. The reason being is that u-boot is copying the DT blob to the upper part of RAM when booting the kernel and the kernel is unable to access the blob. By setting the fdt_high variable to either 0xffffffff (to prevent the copy) or 0xac000000 (704MB boundary of memory for OMAP4) the kernel is able to locate the DT blob and boot. Based upon following patch by Dirk Behme set the fdt_high variable to allow booting with device tree on OMAP4 boards. "7e9603e i.mx6q: configs: Add fdt_high and initrd_high variables" Cc: Sricharan R <r.sricharan(a)ti.com> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Tom Rini <trini(a)ti.com> Signed-off-by: Jon Hunter <jon-hunter(a)ti.com> --- include/configs/omap4_common.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index a989721..d31cbb5 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -151,6 +151,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdt_high=0xffffffff\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ -- 1.7.5.4

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[U-Boot] [PATCH 0/6] further updates for Keymile ARM boards
by Holger Brunck 04 May '12

04 May '12

This patch seris is based on a already transmitted but currently not committed patch serie: http://lists.denx.de/pipermail/u-boot/2012-March/121009.html It adds some further support for our managed switch on kmnusa and kmcoge5un. And some other feature are added or fixed (dip switch detection for kmcoge5un, testpin detection for kmcoge5un). This patch serie modifies only code for Keymile boards and does no changes in common u-boot code. Thomas Herzmann (2): arm/km: add implementation for read_dip_switch arm/km: fix testpin detection for kmcoge5un Valentin Longchamp (4): arm/km: add support for external switch configuration arm/km: enable external switch configuration for kmnusa arm/km: skip FPGA config when already configured arm/km: support the 2 PCIe fpga resets board/keymile/common/common.h | 7 -- board/keymile/km_arm/fpga_config.c | 52 +++++++++- board/keymile/km_arm/km_arm.c | 31 +++++-- board/keymile/km_arm/managed_switch.c | 169 +++++++++++++++++++++++++++++++-- board/keymile/km_arm/managed_switch.h | 99 +++++++++++++++++++ include/configs/km_kirkwood.h | 3 - 6 files changed, 330 insertions(+), 31 deletions(-) create mode 100644 board/keymile/km_arm/managed_switch.h

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