May 2012 - U-Boot

[U-Boot] garbage in early serial output on at91sam9g20 after u-boot v2011.12
by Alexander Dahl 08 May '12

08 May '12

Hei hei, I was updating u-boot for our target hardware in the past few days. We have a board here very similar in design to the Atmel AT91SAM9G20-EK. Migrating our patches step by step from v2010.09 to v2011.09 replacing code based on at91 legacy code took a while but was succesful. Output on the serial console (debug console of the SoC) was and should be like this (some output of at91bootstrap before u-boot): Start AT91Bootstrap... HW_INIT AT91Bootstrap successful... NAND-Flash uChipID: 0xADDA loaded image into RAM U-Boot 2011.06-00027-g21b18a4 (May 08 2012 - 15:03:20) CPU: AT91SAM9G20 Crystal frequency: 18.432 MHz CPU clock : 396.288 MHz Master clock : 132.096 MHz DRAM: 32 MiB NAND: 256 MiB In: serial Out: serial Err: serial Net: macb0 Hit keys 'is' to stop autoboot (3 seconds). I know, still v2011.06 but worked. Now with v2011.12 and v2012.04 output of the »greeting line« and CPU info produces garbage, see: Start AT91Bootstrap... HW_INéÅÍÉ¹ÁåÙ5!é5)I5éÍÉ5¥essful5)ÿWARNING: Caches not enabled NAND: 256 MiB!é5)5 0xADDA In: serial¹ÁÑ¡5RAM Out: serial5!é5))5) Err: serial Net: macb0 Hit keys 'is' to stop autoboot (3 seconds). The console works in the end, but in between there's just garbage. I tried moving the call to at91_seriald_hw_init() from board_init() to board_early_init_f) but this didn't change the behaviour. I also tried to find out what was changed in u-boot source since 2011.09 but this is a lot and just looking over commit messages in git I didn't get a clue. Has someone had similar problems and maybe a solution? Or is anyone interested in debugging this and could help me with a start? Greets Alex -- »With the first link, the chain is forged. The first speech censured, the first thought forbidden, the first freedom denied, chains us all irrevocably.« (Jean-Luc Picard, quoting Judge Aaron Satie) *** GnuPG-FP: 02C8 A590 7FE5 CA5F 3601 D1D5 8FBA 7744 CC87 10D0 ***

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[U-Boot] Subject: [PATCH] libfdt: Add fdt functionality for more intuitive fdt handling
by Peter Feuerer 08 May '12

08 May '12

libfdt: Add fdt functionality for more intuitive fdt handling New functions: fdt_read - retrieve the value of a property by full path fdt_write - create or change a property with full path and create subnodes if needed fdt_create_path - create subnode path with parents Signed-off-by: Peter Feuerer <peter.feuerer(a)sysgo.com> CC: David Gibson <david(a)gibson.dropbear.id.au> CC: Gerald Van Baren <gvb(a)unssw.com> --- include/libfdt.h | 93 ++++++++++++++++++++++++++++++++++++++++ lib/libfdt/fdt_ro.c | 30 +++++++++++++ lib/libfdt/fdt_rw.c | 97 ++++++++++++++++++++++++++++++++++++++++++ lib/libfdt/libfdt_internal.h | 4 ++ 4 files changed, 224 insertions(+), 0 deletions(-) diff --git a/include/libfdt.h b/include/libfdt.h index de82ed5..822ab18 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -548,6 +548,37 @@ static inline void *fdt_getprop_w(void *fdt, int nodeoffset, } /** + * fdt_read - retrieve the value of a property by full path + * @fdt: pointer to the device tree blob + * @path: string containing the absolute path of the property + * @name: name of the property + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_read(const void *fdt, const char *path, + const char *name, int *lenp); + +/** * fdt_get_phandle - retrieve the phandle of a given node * @fdt: pointer to the device tree blob * @nodeoffset: structure block offset of the node @@ -1066,6 +1097,38 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name); */ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); +/** + * fdt_write - create or change a property with full path and create + * all subnodes to the property if needed + * @fdt: pointer to the device tree blob + * @path: string containing the absolute path of the property + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_write() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. Additionally it creates all parent nodes if + * not yet existing. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_write(void *fdt, const char *path, const char *name, + const void *val, int len); /** * fdt_setprop_cell - set a property to a single cell value @@ -1204,6 +1267,36 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, int fdt_add_subnode(void *fdt, int parentoffset, const char *name); /** + * fdt_create_path - create subnode path with parents + * @fdt: pointer to the device tree blob + * @path: absolute path of subnodes to create + * + * fdt_create_path() creates absolute subnode path with all needed + * parents, if they don't exist. + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_create_path(struct fdt_header *fdt, const char *path); + +/** * fdt_del_node - delete a node (subtree) * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node to nop diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 1933010..9a08200 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -324,6 +324,36 @@ const void *fdt_getprop(const void *fdt, int nodeoffset, return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp); } +const void *fdt_read(const void *fdt, const char *path, + const char *name, int *lenp) +{ + int nodeoffset; + int len; + const void *nodep ; + + if (fdt_check_header(fdt) != 0) { + if (lenp) + *lenp = -FDT_ERR_BADSTRUCTURE; + return NULL; + } + + nodeoffset = fdt_path_offset(fdt, path); + + if (nodeoffset < 0) { + if (lenp) + *lenp = -FDT_ERR_BADPATH; + return NULL; + } else { + nodep = fdt_getprop(fdt, nodeoffset, name, &len); + if (len <= 0) + return NULL; + if (lenp) + *lenp = len; + } + return nodep; +} + + uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) { const uint32_t *php; diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index 5c27a67..ccebafb 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -293,6 +293,21 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, return 0; } +int fdt_write(void *fdt, const char *path, const char *name, + const void *val, int len) +{ + int nodeoffset; + + FDT_CHECK_HEADER(fdt); + + nodeoffset = fdt_create_path(fdt, path); + + if (nodeoffset < 0) + return nodeoffset; + + return fdt_setprop(fdt, nodeoffset, name, val, len); +} + int fdt_delprop(void *fdt, int nodeoffset, const char *name) { struct fdt_property *prop; @@ -354,6 +369,88 @@ int fdt_add_subnode(void *fdt, int parentoffset, const char *name) return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name)); } +int fdt_create_path_internal(struct fdt_header *fdt, char *path) +{ + int offset = 0; + char *p = NULL; + char *last_slash = NULL; + char *path2 = path; + int ret = 0; + + /* search for last slash */ + for (p = path; *p != 0; ++p) + if (*p == '/') + last_slash = p; + + /* if path ends with "/" then, error */ + if (*(last_slash + 1) == 0) + return -FDT_ERR_BADPATH; + + /* + * if last_slash is root, use "/" instead of string + * otherwise terminate string at slash + */ + if (last_slash == path) + path2 = "/"; + else + *last_slash = 0; + + /* + * test if the parent path is valid, if not valid, + * recursively add paths + */ + offset = fdt_path_offset(fdt, path2); + if (offset == -FDT_ERR_NOTFOUND) + offset = fdt_create_path_internal(fdt, path2); + + if (offset < 0) + return offset; + + /* path valid, create subnode */ + ret = fdt_add_subnode(fdt, offset, last_slash + 1); + + /* undo termination */ + if (last_slash && last_slash != path) + *last_slash = '/'; + + return ret; +} + +int fdt_create_path(struct fdt_header *fdt, const char *path) +{ + int offset = 0; + int ret = 0; + int size = 0; +#ifndef FDT_USE_MALLOC + char path_mem[FDT_MAX_PATHLEN] = {0}; + size = FDT_MAX_PATHLEN; +#else + char *path_mem; + size = strlen(path); + path_mem = calloc(size, 1); + if (!path_mem) + return -FDT_ERR_NOSPACE; +#endif + + /* if full path already exists, return the offset */ + offset = fdt_path_offset(fdt, path); + if (offset >= 0) { + ret = offset; + goto end; + } + + /* copy path to local path variable, so that we can modify it */ + strncpy(path_mem, path, size - 1); + + ret = fdt_create_path_internal(fdt, path_mem); +end: +#ifdef FDT_USE_MALLOC + free(path_mem); +#endif + return ret; + +} + int fdt_del_node(void *fdt, int nodeoffset) { int endoffset; diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index 381133b..786a052 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -55,6 +55,10 @@ #define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) +#ifndef FDT_USE_MALLOC +#define FDT_MAX_PATHLEN 2048 +#endif + #define FDT_CHECK_HEADER(fdt) \ { \ int err; \ -- 1.7.3

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[U-Boot] [PATCH 0/6 V2] EXYNOS5: USB: Enable USB 2.0 support
by Rajeshwari Shinde 08 May '12

08 May '12

This patchset series adds support to enable USB 2.0 on smdk5250. It corrects sysreg register, usb host, usb otg base address, adds power management registers,functions to enable and disable power to the USB host controller are added. This patchset is based on: USB: EXYNOS: Add ehci support.patch Rajeshwari Shinde (6): EXYNOS5: Fix system register structure EXYNOS: Add structure for PMU registers EXYNOS5 : USB: Set USB 2.0 HOST Link mode Exynos5: Add power Enable/Disable for USB-EHCI EXYNOS5: USB: Fix incorrect USB base addresses config: EXYNOS5: USB: Enable USB 2.0 on smdk5250 arch/arm/cpu/armv7/exynos/power.c | 37 ++ arch/arm/cpu/armv7/exynos/system.c | 22 + arch/arm/include/asm/arch-exynos/cpu.h | 4 +- arch/arm/include/asm/arch-exynos/power.h | 626 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/system.h | 4 + drivers/usb/host/ehci-exynos.c | 7 + include/configs/smdk5250.h | 6 + 7 files changed, 704 insertions(+), 2 deletions(-) -- 1.7.4.4

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[U-Boot] [PATCH] MTD: SPEAr SMI: Add write support for length < 4 bytes
by Stefan Roese 08 May '12

08 May '12

Needed for redundant environment for example. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- drivers/mtd/st_smi.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c index 3f689e7..f950e11 100644 --- a/drivers/mtd/st_smi.c +++ b/drivers/mtd/st_smi.c @@ -362,7 +362,7 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) * smi_write - Write to SMI flash * @src_addr: source buffer * @dst_addr: destination buffer - * @length: length to write in words + * @length: length to write in bytes * @bank: bank base address * * Write to SMI flash @@ -370,7 +370,10 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, unsigned int length, ulong bank_addr) { + u8 *src_addr8 = (u8 *)src_addr; + u8 *dst_addr8 = (u8 *)dst_addr; int banknum; + int i; switch (bank_addr) { case SMIBANK0_BASE: @@ -399,7 +402,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; /* Perform the write command */ - while (length--) { + for (i = 0; i < length; i += 4) { if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) @@ -409,7 +412,18 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; } - *dst_addr++ = *src_addr++; + if (length < 4) { + int k; + + /* + * Handle special case, where length < 4 (redundant env) + */ + for (k = 0; k < length; k++) + *dst_addr8++ = *src_addr8++; + } else { + /* Normal 32bit write */ + *dst_addr++ = *src_addr++; + } if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) return -EIO; @@ -435,7 +449,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) { return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - (length + 3) / 4, info->start[0]); + length, info->start[0]); } /* -- 1.7.10.1

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[U-Boot] [PATCH] i2c: designware_i2c.c: Add support for the "i2c probe" command
by Stefan Roese 08 May '12

08 May '12

i2c_probe() is changed to reinit the i2c bus upon read failure. This is naturally the case upon i2c bus probing. Also, some printf messages upon read failure are removed. As they would interfere with the "i2c probe" command. Additionally, i2c_set_bus_speed() now returns 0, so that the "i2c speed" command can be used. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- drivers/i2c/designware_i2c.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 6d118ac..bf64a2a 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -90,7 +90,7 @@ static void set_speed(int i2c_spd) * * Set the i2c speed. */ -void i2c_set_bus_speed(int speed) +int i2c_set_bus_speed(int speed) { if (speed >= I2C_MAX_SPEED) set_speed(IC_SPEED_MODE_MAX); @@ -98,6 +98,8 @@ void i2c_set_bus_speed(int speed) set_speed(IC_SPEED_MODE_FAST); else set_speed(IC_SPEED_MODE_STANDARD); + + return 0; } /* @@ -215,10 +217,8 @@ static int check_params(uint addr, int alen, uchar *buffer, int len) static int i2c_xfer_init(uchar chip, uint addr) { - if (i2c_wait_for_bb()) { - printf("Timed out waiting for bus\n"); + if (i2c_wait_for_bb()) return 1; - } i2c_setaddress(chip); writel(addr, &i2c_regs_p->ic_cmd_data); @@ -282,7 +282,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) start_time_rx = get_timer(0); } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { - printf("Timed out. i2c read Failed\n"); return 1; } } @@ -334,9 +333,14 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { u32 tmp; + int ret; /* * Try to read the first location of the chip. */ - return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + if (ret) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return ret; } -- 1.7.10.1

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[U-Boot] [PATCH] rtc/m41t62: Add support for M41T82 with HT (Halt Update)
by Stefan Roese 08 May '12

08 May '12

Add support for the M41T82 RTC to the m41t62 driver. The only difference that needs to be handled by this driver, is to clear the HT (Halt Update) bit upon reset. This bit is not used on the M41T62, so its save to clear this bit always. The M41T82 support will be used by the X600 (SPEAr600) board support. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/rtc/m41t62.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 62c2446..8721e74 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -63,6 +63,8 @@ #define M41T62_FEATURE_HT (1 << 0) #define M41T62_FEATURE_BL (1 << 1) +#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ + int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; @@ -132,9 +134,15 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { + u8 val; + /* - * Nothing to do + * M41T82: Make sure HT (Halt Update) bit is cleared. + * This bit is 0 in M41T62 so its save to clear it always. */ + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + val &= ~M41T80_ALHOUR_HT; + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif -- 1.7.10.1

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[U-Boot] [PATCH 0/7] ARM: SPL: SPEAr: Add SPEAr600 X600 board with SPL support
by Stefan Roese 08 May '12

08 May '12

This patch series introduces SPL support for SPEAr600. One more platform not needing XLoader any more. The integrated new X600 board port is the first user of this SPL support. Thanks, Stefan Simon Glass (1): arm: Don't use printf() in SPL builds Stefan Roese (6): SPL: common/Makefile: Add image.c to SPL build SPL: lib/Makefile: Add crc32.c to SPL build SPL: ARM: spear: Remove some objects from SPL build Makefile: Add u-boot.spr build target (SPEAr) SPL: ARM: spear: Add SPL support for SPEAr600 platform ARM: Add X600 board support (SPEAr600 based) MAINTAINERS | 2 + Makefile | 17 ++ arch/arm/cpu/arm926ejs/spear/Makefile | 24 +- arch/arm/cpu/arm926ejs/spear/spear600.c | 236 ++++++++++++++ arch/arm/cpu/arm926ejs/spear/spl.c | 282 +++++++++++++++++ arch/arm/cpu/arm926ejs/spear/spl_boot.c | 197 ++++++++++++ .../spear/spr600_mt47h128m8_3_266_cl5_async.c | 130 ++++++++ .../spear/spr600_mt47h32m16_333_cl5_psync.c | 135 ++++++++ .../spear/spr600_mt47h32m16_37e_166_cl4_sync.c | 130 ++++++++ .../spear/spr600_mt47h64m16_3_333_cl5_psync.c | 144 +++++++++ arch/arm/cpu/arm926ejs/spear/start.S | 122 ++++++++ arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 87 ++++++ arch/arm/include/asm/arch-spear/hardware.h | 55 ++-- arch/arm/include/asm/arch-spear/spr_defs.h | 30 ++ arch/arm/include/asm/arch-spear/spr_misc.h | 136 ++++++++- arch/arm/include/asm/arch-spear/spr_ssp.h | 45 +++ arch/arm/include/asm/arch-spear/spr_syscntl.h | 14 + arch/arm/lib/eabi_compat.c | 3 +- board/spear/common/Makefile | 2 + board/spear/spear600/Makefile | 2 + board/spear/x600/Makefile | 47 +++ board/spear/x600/fpga.c | 280 +++++++++++++++++ board/spear/x600/fpga.h | 23 ++ board/spear/x600/x600.c | 124 ++++++++ boards.cfg | 1 + common/Makefile | 2 +- config.mk | 4 + include/configs/x600.h | 323 ++++++++++++++++++++ lib/Makefile | 2 +- 29 files changed, 2569 insertions(+), 30 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/spear/spear600.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl_boot.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/start.S create mode 100644 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-spear/spr_ssp.h create mode 100644 board/spear/x600/Makefile create mode 100644 board/spear/x600/fpga.c create mode 100644 board/spear/x600/fpga.h create mode 100644 board/spear/x600/x600.c create mode 100644 include/configs/x600.h

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[U-Boot] [PATCH 7/7] ARM: Add X600 board support (SPEAr600 based)
by Stefan Roese 08 May '12

08 May '12

This patch adds support for the X600 SPEAr600 based board. Its also the first SPEAr600 board that uses the newly introduced SPEAr600 SPL support. Xloader is not necessary any more. By using the new "u-boot.spr" make target, one image will generated containing both, U-Boot SPL (with mkimage header as needed by the SPEAr BootROM, and the main U-Boot with mkimage header. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- MAINTAINERS | 2 + board/spear/x600/Makefile | 47 +++++++ board/spear/x600/fpga.c | 280 +++++++++++++++++++++++++++++++++++++++ board/spear/x600/fpga.h | 23 ++++ board/spear/x600/x600.c | 124 +++++++++++++++++ boards.cfg | 1 + include/configs/x600.h | 323 +++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 800 insertions(+) create mode 100644 board/spear/x600/Makefile create mode 100644 board/spear/x600/fpga.c create mode 100644 board/spear/x600/fpga.h create mode 100644 board/spear/x600/x600.c create mode 100644 include/configs/x600.h diff --git a/MAINTAINERS b/MAINTAINERS index e2441d8..296a1b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -814,6 +814,8 @@ John Rigby <jcrigby(a)gmail.com> Stefan Roese <sr(a)denx.de> + x600 ARM926EJS (spear600 Soc) + pdnb3 xscale/ixp scpu xscale/ixp diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile new file mode 100644 index 0000000..8c4e7e2 --- /dev/null +++ b/board/spear/x600/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := fpga.o $(BOARD).o +endif +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c new file mode 100644 index 0000000..85eb31b --- /dev/null +++ b/board/spear/x600/fpga.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spartan3.h> +#include <command.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_ssp.h> + +/* + * FPGA program pin configuration on X600: + * + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use + * 16bit serial writes via this SSP port to write the data bits into the + * FPGA. + */ +#define CONFIG_SYS_FPGA_PROG 2 +#define CONFIG_SYS_FPGA_DONE 3 + +/* + * Set the active-low FPGA reset signal. + */ +static void fpga_reset(int assert) +{ + /* + * On x600 we have no means to toggle the FPGA reset signal + */ + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert); +} + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +static int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); + + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert); + + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +static int fpga_init_fn(int cookie) +{ + static int state; + + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state); + + /* + * On x600, the FPGA INIT signal is not connected to the SoC. + * We can't read the INIT status. Let's return the "correct" + * INIT signal state generated via a local state-machine. + */ + if (++state == 1) { + return 1; + } else { + state = 0; + return 0; + } +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +static int fpga_done_fn(int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + + /* + * Wait for Tx-FIFO to become empty before looking for DONE + */ + while (!(readl(&ssp->sspsr) & SSPSR_TFE)) + ; + + if (gpio_get_value(CONFIG_SYS_FPGA_DONE)) + return 1; + else + return 0; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +static int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); + fpga_reset(TRUE); + + return 0; +} + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +static int fpga_post_config_fn(int cookie) +{ + int rc = 0; + + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); + + fpga_reset(TRUE); + udelay(100); + fpga_reset(FALSE); + udelay(100); + + return rc; +} + +static int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + /* + * No dedicated clock signal on x600 (data & clock generated) + * in SSP interface. So we don't have to do anything here. + */ + return assert_clk; +} + +static int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + static int count; + static u16 data; + + /* + * First collect 16 bits of data + */ + data = data << 1; + if (assert_write) + data |= 1; + + /* + * If 16 bits are not available, return for more bits + */ + count++; + if (count != 16) + return assert_write; + + count = 0; + + /* + * Wait for Tx-FIFO to become ready + */ + while (!(readl(&ssp->sspsr) & SSPSR_TNF)) + ; + + /* Send 16 bits to FPGA via SSP bus */ + writel(data, &ssp->sspdr); + + return assert_write; +} + +static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; + +static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) +}; + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +static void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + +static int expi_setup(int freq) +{ + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + int pll2_m, pll2_n, pll2_p, expi_x, expi_y; + + pll2_m = (freq * 2) / 1000; + pll2_n = 15; + pll2_p = 1; + expi_x = 1; + expi_y = 2; + + /* + * Disable reset, Low compression, Disable retiming, Enable Expi, + * Enable soft reset, DMA, PLL2, Internal + */ + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST | + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 | + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24), + &misc->expi_clk_cfg); + + /* + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters, + * Enable PLL2, Disable reset + */ + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq); + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE | + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl); + + /* + * Disable soft reset + */ + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST); + + return 0; +} + +/* + * Initialize the fpga + */ +int x600_init_fpga(void) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Enable SSP2 clock */ + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB, + &misc->periph1_clken); + + /* Set EXPI clock to 45 MHz */ + expi_setup(45000); + + /* Configure GPIO directions */ + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0); + gpio_direction_input(CONFIG_SYS_FPGA_DONE); + + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); + writel(SSPCR1_SSE, &ssp->sspcr1); + + /* + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download + * speed. + * + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1)) + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz. + */ + writel(2, &ssp->sspcpsr); + + fpga_init(); + fpga_serialslave_init(); + + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__); + fpga_add(fpga_xilinx, &fpga[0]); + + return 0; +} diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h new file mode 100644 index 0000000..2b18557 --- /dev/null +++ b/board/spear/x600/fpga.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +int x600_init_fpga(void); diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c new file mode 100644 index 0000000..96ec0ad --- /dev/null +++ b/board/spear/x600/x600.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <netdev.h> +#include <phy.h> +#include <rtc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <linux/mtd/fsmc_nand.h> +#include "fpga.h" + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + /* + * X600 is equipped with an M41T82 RTC. This RTC has the + * HT bit (Halt Update), which needs to be cleared upon + * power-up. Otherwise the RTC is halted. + */ + rtc_reset(); + + return spear_board_init(MACH_TYPE_SPEAR600); +} + +int board_late_init(void) +{ + /* + * Monitor and env protection on by default + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* Init FPGA subsystem */ + x600_init_fpga(); + + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init(void) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + fsmc_nand_init(nand); +} + +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + /* Extended PHY control 1, select GMII */ + mii_write(dev, phy_addr, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + dw_reset_phy(dev); + + /* Enable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + mii_write(dev, phy_addr, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + mii_write(dev, phy_addr, 16, 0xe0ea); + + /* Disable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0000); + + /* Enable clock output pin */ + mii_write(dev, phy_addr, 18, 0x0049); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + PHY_INTERFACE_MODE_GMII) >= 0) + ret++; + + return ret; +} diff --git a/boards.cfg b/boards.cfg index ffdc281..119d84b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -190,6 +190,7 @@ spear600 arm arm926ejs spear600 spear spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand +x600 arm arm926ejs - spear spear x600 versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB diff --git a/include/configs/x600.h b/include/configs/x600.h new file mode 100644 index 0000000..2093a0c --- /dev/null +++ b/include/configs/x600.h @@ -0,0 +1,323 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, <vipin.kumar(a)st.com> + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 /* SPEAr600 SoC */ +#define CONFIG_X600 /* on X600 board */ + +#include <asm/arch/hardware.h> + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK 8300000 + +#define CONFIG_SYS_TEXT_BASE 0x00800040 +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +/* Reserve 8KiB for SPL */ +#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x60000 + +#define CONFIG_ENV_IS_IN_FLASH + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NOR FLASH config options */ +#define CONFIG_ST_SMI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* NAND FLASH config options */ +#define CONFIG_NAND_FSMC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE +#define CONFIG_MTD_ECC_SOFT +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* UBI/UBI config options */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE + +/* Ethernet config options */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_SPEAR_GPIO + +/* I2C config options */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_I2C_CHIPADDRESS 0x50 + +#define CONFIG_RTC_M41T62 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* FPGA config options */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 + +/* + * Command support defines + */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_LZO + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +#define CONFIG_BOOTDELAY 3 + +/* + * U-Boot Environment placing definitions. + */ +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "X600> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_64BIT_VSPRINTF + +#define CONFIG_HOSTNAME x600 +#define CONFIG_UBI_PART ubi0 +#define CONFIG_UBIFS_VOLUME rootfs + +#define xstr(s) str(s) +#define str(s) #s + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:-(ubi0)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr=1000000\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ + "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ + " ${filesize};" \ + "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "upd=run load update\0" \ + "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ + "part=" xstr(CONFIG_UBI_PART) "\0" \ + "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ + " ${filesize}\0" \ + "upd_ubifs=run load_ubifs update_ubifs\0" \ + "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ + "ubi create ${vol} 4000000\0" \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-4.2/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "ubifsargs=set bootargs ubi.mtd=ubi0 root=ubi0:rootfs " \ + "rootfstype=ubifs\0" \ + "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_fs=/boot/uImage \0" \ + "kernel_addr=1000000\0" \ + "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_addr=1800000\0" \ + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ + "${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "net_nfs=run load_dtb load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ + " addcon addmisc addmtd;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "ubifs_mount=ubi part ubi0;ubifsmount rootfs\0" \ + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ + "ubifsload ${dtb_addr} ${dtb_fs};\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ + "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ + "bootcmd=run nand_ubifs\0" \ + "\0" + +/* Stack sizes */ +#define CONFIG_STACKSIZE (512 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * SPL related defines + */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0xd2800b00 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ +#define CONFIG_SPL_NO_PRINTF + +/* + * Please select/define only one of the following + * Each definition corresponds to a supported DDR chip. + * DDR configuration is based on the following selection + */ +#define CONFIG_DDR_MT47H64M16 1 +#define CONFIG_DDR_MT47H32M16 0 +#define CONFIG_DDR_MT47H128M8 0 + +/* + * Synchronous/Asynchronous operation of DDR + * + * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation + * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation + * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation + */ +#define CONFIG_DDR_2HCLK 1 +#define CONFIG_DDR_HCLK 0 +#define CONFIG_DDR_PLL2 0 + +/* + * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported + * or not. Modify/Add to only these macros to define new boot types + */ +#define USB_BOOT_SUPPORTED 0 +#define PCIE_BOOT_SUPPORTED 0 +#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 0 +#define TFTP_BOOT_SUPPORTED 0 +#define UART_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 +#define MMC_BOOT_SUPPORTED 0 + +#endif /* __CONFIG_H */ -- 1.7.10.1

1 0

[U-Boot] [PATCH 6/7] SPL: ARM: spear: Add SPL support for SPEAr600 platform
by Stefan Roese 08 May '12

08 May '12

This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- arch/arm/cpu/arm926ejs/spear/Makefile | 24 +- arch/arm/cpu/arm926ejs/spear/spear600.c | 236 ++++++++++++++++ arch/arm/cpu/arm926ejs/spear/spl.c | 282 ++++++++++++++++++++ arch/arm/cpu/arm926ejs/spear/spl_boot.c | 197 ++++++++++++++ .../spear/spr600_mt47h128m8_3_266_cl5_async.c | 130 +++++++++ .../spear/spr600_mt47h32m16_333_cl5_psync.c | 135 ++++++++++ .../spear/spr600_mt47h32m16_37e_166_cl4_sync.c | 130 +++++++++ .../spear/spr600_mt47h64m16_3_333_cl5_psync.c | 144 ++++++++++ arch/arm/cpu/arm926ejs/spear/start.S | 122 +++++++++ arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 87 ++++++ arch/arm/include/asm/arch-spear/hardware.h | 55 ++-- arch/arm/include/asm/arch-spear/spr_defs.h | 30 +++ arch/arm/include/asm/arch-spear/spr_misc.h | 136 +++++++++- arch/arm/include/asm/arch-spear/spr_ssp.h | 45 ++++ arch/arm/include/asm/arch-spear/spr_syscntl.h | 14 + 15 files changed, 1740 insertions(+), 27 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/spear/spear600.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spl_boot.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c create mode 100644 arch/arm/cpu/arm926ejs/spear/start.S create mode 100644 arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-spear/spr_ssp.h diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 46923a4..d06f03d 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -25,17 +25,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := cpu.o \ +COBJS-y := cpu.o \ reset.o \ timer.o -SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o spl_boot.o +COBJS-$(CONFIG_SPEAR600) += spear600.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o +COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +endif -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c new file mode 100644 index 0000000..ff52131 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2000-2009 + * Viresh Kumar, ST Microelectronics, viresh.kumar(a)st.com + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_defs.h> + +#define FALSE 0 +#define TRUE (!FALSE) + +static void sel_1v8(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000003; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000010; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) + ; +} + +static void sel_2v5(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000003; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000010; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) + ; +} + +/* + * plat_ddr_init: + */ +void plat_ddr_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddrpad; + u32 core3v3, ddr1v8, ddr2v5; + + /* DDR pad register configurations */ + ddrpad = readl(&misc_p->ddr_pad); + ddrpad &= ~DDR_PAD_CNF_MSK; + +#if (CONFIG_DDR_HCLK) + ddrpad |= 0xEAAB; +#elif (CONFIG_DDR_2HCLK) + ddrpad |= 0xEAAD; +#elif (CONFIG_DDR_PLL2) + ddrpad |= 0xEAAD; +#endif + writel(ddrpad, &misc_p->ddr_pad); + + /* Compensation register configurations */ + core3v3 = readl(&misc_p->core_3v3_compensation); + core3v3 &= 0x8080ffe0; + core3v3 |= 0x78000002; + writel(core3v3, &misc_p->core_3v3_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000004; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000004; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { + /* Software memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) + sel_1v8(); + else + sel_2v5(); + } else { + /* Hardware memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) + sel_1v8(); + else + sel_2v5(); + } +} + +/* + * soc_init: + */ +void soc_init(void) +{ + /* Nothing to be done for SPEAr600 */ +} + +/* + * xxx_boot_selected: + * + * return TRUE if the particular booting option is selected + * return FALSE otherwise + */ +static u32 read_bootstrap(void) +{ + return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) + & CONFIG_SPEAR_BOOTSTRAPMASK; +} + +int snor_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (SNOR_BOOT_SUPPORTED) { + /* Check whether SNOR boot is selected */ + if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == + CONFIG_SPEAR_ONLYSNORBOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int nand_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (NAND_BOOT_SUPPORTED) { + /* Check whether NAND boot is selected */ + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int pnor_boot_selected(void) +{ + /* Parallel NOR boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int usb_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (USB_BOOT_SUPPORTED) { + /* Check whether USB boot is selected */ + if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) + return TRUE; + } + + return FALSE; +} + +int tftp_boot_selected(void) +{ + /* TFTP boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int uart_boot_selected(void) +{ + /* UART boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int spi_boot_selected(void) +{ + /* SPI boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int i2c_boot_selected(void) +{ + /* I2C boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int mmc_boot_selected(void) +{ + return FALSE; +} + +void plat_late_init(void) +{ + spear_late_init(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c new file mode 100644 index 0000000..48e6efb --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_syscntl.h> + +inline void hang(void) +{ + serial_puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +static void ddr_clock_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 clkenb, ddrpll; + + clkenb = readl(&misc_p->periph1_clken); + clkenb &= ~PERIPH_MPMCMSK; + clkenb |= PERIPH_MPMC_WE; + + /* Intentionally done twice */ + writel(clkenb, &misc_p->periph1_clken); + writel(clkenb, &misc_p->periph1_clken); + + ddrpll = readl(&misc_p->pll_ctr_reg); + ddrpll &= ~MEM_CLK_SEL_MSK; +#if (CONFIG_DDR_HCLK) + ddrpll |= MEM_CLK_HCLK; +#elif (CONFIG_DDR_2HCLK) + ddrpll |= MEM_CLK_2HCLK; +#elif (CONFIG_DDR_PLL2) + ddrpll |= MEM_CLK_PLL2; +#else +#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)" +#endif + writel(ddrpll, &misc_p->pll_ctr_reg); + + writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, + &misc_p->periph1_clken); +} + +static void mpmc_init_values(void) +{ + u32 i; + u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + u32 *mpmc_val_p = &mpmc_conf_vals[0]; + + for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++) + writel(*mpmc_val_p, mpmc_reg_p); + + mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + + /* + * MPMC controller start + * MPMC waiting for DLLLOCKREG high + */ + writel(0x01000100, &mpmc_reg_p[7]); + + while (!(readl(&mpmc_reg_p[3]) & 0x10000)) + ; +} + +static void mpmc_init(void) +{ + /* Clock related settings for DDR */ + ddr_clock_init(); + + /* + * DDR pad register bits are different for different SoCs + * Compensation values are also handled separately + */ + plat_ddr_init(); + + /* Initialize mpmc register values */ + mpmc_init_values(); +} + +static void pll_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Initialize PLLs */ + writel(FREQ_332, &misc_p->pll1_frq); + writel(0x1C0A, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + writel(0x1C06, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + + writel(FREQ_332, &misc_p->pll2_frq); + writel(0x1C0A, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + writel(0x1C06, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + + /* wait for pll locks */ + while (!(readl(&misc_p->pll1_cntl) & 0x1)) + ; + while (!(readl(&misc_p->pll2_cntl) & 0x1)) + ; +} + +static void mac_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC), + &misc_p->periph1_clken); + + writel(SYNTH23, &misc_p->gmac_synth_clk); + + switch (get_socrev()) { + case SOC_SPEAR600_AA: + case SOC_SPEAR600_AB: + case SOC_SPEAR600_BA: + case SOC_SPEAR600_BB: + case SOC_SPEAR600_BC: + case SOC_SPEAR600_BD: + writel(0x0, &misc_p->gmac_ctr_reg); + break; + + case SOC_SPEAR300: + case SOC_SPEAR310: + case SOC_SPEAR320: + writel(0x4, &misc_p->gmac_ctr_reg); + break; + } + + writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC, + &misc_p->periph1_clken); + + writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC, + &misc_p->periph1_rst); + writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC), + &misc_p->periph1_rst); +} + +static void sys_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct syscntl_regs *syscntl_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + /* Set system state to SLOW */ + writel(SLOW, &syscntl_p->scctrl); + writel(PLL_TIM << 3, &syscntl_p->scpllctrl); + + /* Initialize PLLs */ + pll_init(); + + /* + * Ethernet configuration + * To be done only if the tftp boot is not selected already + * Boot code ensures the correct configuration in tftp booting + */ + if (!tftp_boot_selected()) + mac_init(); + + writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg); + writel(0x555, &misc_p->amba_clk_cfg); + + writel(NORMAL, &syscntl_p->scctrl); + + /* Wait for system to switch to normal mode */ + while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK) + != NORMAL) + ; +} + +/* + * get_socrev + * + * Get SoC Revision. + * @return SOC_SPEARXXX + */ +int get_socrev(void) +{ +#if defined(CONFIG_SPEAR600) + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 soc_id = readl(&misc_p->soc_core_id); + u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF; + u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF; + + if ((pri_socid == 'B') && (sec_socid == 'B')) + return SOC_SPEAR600_BB; + else if ((pri_socid == 'B') && (sec_socid == 'C')) + return SOC_SPEAR600_BC; + else if ((pri_socid == 'B') && (sec_socid == 'D')) + return SOC_SPEAR600_BD; + else if (soc_id == 0) + return SOC_SPEAR600_BA; + else + return SOC_SPEAR_NA; +#elif defined(CONFIG_SPEAR300) + return SOC_SPEAR300; +#elif defined(CONFIG_SPEAR310) + return SOC_SPEAR310; +#elif defined(CONFIG_SPEAR320) + return SOC_SPEAR320; +#endif +} + +void lowlevel_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + const char *u_boot_rev = U_BOOT_VERSION; + + /* Initialize PLLs */ + sys_init(); + + /* Initialize UART */ + serial_init(); + + /* Print U-Boot SPL version string */ + serial_puts("\nU-Boot SPL "); + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + serial_puts(u_boot_rev); + serial_puts(" ("); + serial_puts(U_BOOT_DATE); + serial_puts(" - "); + serial_puts(U_BOOT_TIME); + serial_puts(")\n"); + +#if defined(CONFIG_OS_BOOT) + writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, + &misc_p->periph1_clken); +#endif + + /* Enable IPs (release reset) */ + writel(PERIPH_RST_ALL, &misc_p->periph1_rst); + + /* Initialize MPMC */ + serial_puts("Configure DDR\n"); + mpmc_init(); + + /* SoC specific initialization */ + soc_init(); +} + +void spear_late_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(0x80000007, &misc_p->arb_icm_ml1); + writel(0x80000007, &misc_p->arb_icm_ml2); + writel(0x80000007, &misc_p->arb_icm_ml3); + writel(0x80000007, &misc_p->arb_icm_ml4); + writel(0x80000007, &misc_p->arb_icm_ml5); + writel(0x80000007, &misc_p->arb_icm_ml6); + writel(0x80000007, &misc_p->arb_icm_ml7); + writel(0x80000007, &misc_p->arb_icm_ml8); + writel(0x80000007, &misc_p->arb_icm_ml9); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c new file mode 100644 index 0000000..f2f9a49 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <image.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/arch/spr_defs.h> +#include <linux/mtd/st_smi.h> + +static const char kernel_name[] = "Linux"; +static const char loader_name[] = "U-Boot"; + +int image_check_header(image_header_t *hdr, const char *name) +{ + if (image_check_magic(hdr) && + (!strncmp(image_get_name(hdr), name, strlen(name))) && + image_check_hcrc(hdr)) { + return 1; + } + return 0; +} + +int image_check_data(image_header_t *hdr) +{ + if (image_check_dcrc(hdr)) + return 1; + + return 0; +} + +/* + * SNOR (Serial NOR flash) related functions + */ +void snor_init(void) +{ + struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; + + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +static int snor_image_load(u8 *load_addr, void (**image_p)(void), + const char *image_name) +{ + image_header_t *header; + + /* + * Since calculating the crc in the SNOR flash does not + * work, we copy the image to the destination address + * minus the header size. And point the header to this + * new destination. This will not work for address 0 + * of course. + */ + header = (image_header_t *)load_addr; + memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), + (const ulong *)load_addr, + image_get_data_size(header) + sizeof(image_header_t)); + header = (image_header_t *)(image_get_load(header) - + sizeof(image_header_t)); + + if (image_check_header(header, image_name)) { + if (image_check_data(header)) { + /* Jump to boot image */ + *image_p = (void *)image_get_load(header); + return 1; + } + } + + return 0; +} + +static void boot_image(void (*image)(void)) +{ + void (*funcp)(void) __noreturn = (void *)image; + + (*funcp)(); +} + +/* + * spl_boot: + * + * All supported booting types of all supported SoCs are listed here. + * Generic readback APIs are provided for each supported booting type + * eg. nand_read_skip_bad + */ +u32 spl_boot(void) +{ + void (*image)(void); + +#ifdef CONFIG_SPEAR_USBTTY + plat_late_init(); + return 1; +#endif + + /* + * All the supported booting devices are listed here. Each of + * the booting type supported by the platform would define the + * macro xxx_BOOT_SUPPORTED to TRUE. + */ + + if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { + /* SNOR-SMI initialization */ + snor_init(); + + serial_puts("Booting via SNOR\n"); + /* Serial NOR booting */ + if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, + &image, loader_name)) { + /* Platform related late initialasations */ + plat_late_init(); + + /* Jump to boot image */ + serial_puts("Jumping to U-Boot\n"); + boot_image(image); + return 1; + } + } + + if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { + /* NAND booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { + /* PNOR booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { + /* MMC booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { + /* SPI booting */ + /* Not supported for any platform as of now */ + return 0; + } + + if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { + /* I2C booting */ + /* Not supported for any platform as of now */ + return 0; + } + + /* + * All booting types without memory are listed as below + * Control has to be returned to BootROM in case of all + * the following booting scenarios + */ + + if (USB_BOOT_SUPPORTED && usb_boot_selected()) { + plat_late_init(); + return 1; + } + + if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { + plat_late_init(); + return 1; + } + + if (UART_BOOT_SUPPORTED && uart_boot_selected()) { + plat_late_init(); + return 1; + } + + /* Ideally, the control should not reach here. */ + hang(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c new file mode 100644 index 0000000..5edc115 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02030202, + 0x03000204, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00040800, + 0x00000000, + 0x00000f02, + 0x00001b1b, + 0x7f000000, + 0x005f0000, + 0x1c040b6a, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x000007ff, + 0x00000000, + 0x47ec00c8, + 0x00c8001f, + 0x00000000, + 0x0000cd98, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00270000, + 0x00250027, + 0x00300000, + 0x008900b7, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c new file mode 100644 index 0000000..616b861 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, + 0x72000000, + 0x00550000, + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c new file mode 100644 index 0000000..b89f77d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x03030301, + 0x03030303, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02020202, + 0x03000203, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00030600, + 0x00000000, + 0x00000a02, + 0x00001c1c, + 0x7f000000, + 0x005f0000, + 0x12030743, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x0000050e, + 0x00000000, + 0x2d8900c8, + 0x00c80014, + 0x00000000, + 0x00008236, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00400000, + 0x003a0040, + 0x00680000, + 0x00d80120, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c new file mode 100644 index 0000000..0c39cd1 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar(a)st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, +#ifdef CONFIG_X600 + 0x02030206, +#else + 0x02010106, +#endif + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, +#ifdef CONFIG_X600 + 0x7f000000, + 0x005c0000, +#else + 0x72000000, + 0x00550000, +#endif + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S new file mode 100644 index 0000000..a103c0f --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -0,0 +1,122 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: +_software_interrupt: +_prefetch_abort: +_data_abort: +_not_used: +_irq: +_fiq: + .word infinite_loop + +infinite_loop: + b infinite_loop + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * Below are the critical initializations already taken place in BootROM. + * So, these are not taken care in Xloader + * 1. Relocation to RAM + * 2. Initializing stacks + * + ************************************************************************* + */ + +/* + * the actual reset code + */ + +reset: +/* + * Xloader has to return back to BootROM in a few cases. + * eg. Ethernet boot, UART boot, USB boot + * Saving registers for returning back + */ + stmdb sp!, {r0-r12,r14} + bl cpu_init_crit +/* + * Clearing bss area is not done in Xloader. + * BSS area lies in the DDR location which is not yet initialized + * bss is assumed to be uninitialized. + */ + bl spl_boot + ldmia sp!, {r0-r12,pc} + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * enable instruction cache + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + stmdb sp!, {lr} + bl lowlevel_init /* go setup pll,mux,memory */ + ldmia sp!, {pc} diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds new file mode 100644 index 0000000..afd3381 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut(a)gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm926ejs/spear/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 0012dd7..8150911 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -24,37 +24,54 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) -#define CONFIG_SPEAR_TIMERBASE (0xFC800000) -#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_USBD_BASE 0xE1100000 +#define CONFIG_SYS_PLUG_BASE 0xE1200000 +#define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_SMI_BASE 0xFC000000 +#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 +#define CONFIG_SPEAR_TIMERBASE 0xFC800000 +#define CONFIG_SPEAR_MISCBASE 0xFCA80000 #define CONFIG_SPEAR_ETHBASE 0xE0800000 +#define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SSP1_BASE 0xD0100000 +#define CONFIG_SSP2_BASE 0xD0180000 +#define CONFIG_SSP3_BASE 0xD8180000 +#define CONFIG_GPIO_BASE 0xD8100000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SYS_FSMC_BASE (0xD1800000) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_FSMC_BASE 0xD1800000 +#define CONFIG_FSMC_NAND_BASE 0xD2000000 + +#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 +#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 +#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB +#define CONFIG_SPEAR_ONLYSNORBOOT 0xA +#define CONFIG_SPEAR_NORNANDBOOT 0xB +#define CONFIG_SPEAR_NORNAND8BOOT 0x8 +#define CONFIG_SPEAR_NORNAND16BOOT 0x9 +#define CONFIG_SPEAR_USBBOOT 0x8 + +#define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x94000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x44000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE #define CONFIG_SYS_NAND_CLE (1 << 17) #define CONFIG_SYS_NAND_ALE (1 << 16) -#define CONFIG_SPEAR_EMIBASE (0x4F000000) -#define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SPEAR_EMIBASE 0x4F000000 +#define CONFIG_SPEAR_RASBASE 0xB4000000 #define CONFIG_SYS_MACB0_BASE 0xB0000000 #define CONFIG_SYS_MACB1_BASE 0xB0800000 @@ -62,11 +79,11 @@ #define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SYS_FSMC_BASE (0x4C000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x4C000000 -#define CONFIG_SPEAR_EMIBASE (0x40000000) -#define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SPEAR_EMIBASE 0x40000000 +#define CONFIG_SPEAR_RASBASE 0xB3000000 #define CONFIG_SYS_MACB0_BASE 0xAA000000 diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index 0ddce62..71d64a1 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -28,6 +28,30 @@ extern int spear_board_init(ulong); extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz; +void plat_ddr_init(void); +void soc_init(void); +void spear_late_init(void); +void plat_late_init(void); + +int snor_boot_selected(void); +int nand_boot_selected(void); +int pnor_boot_selected(void); +int usb_boot_selected(void); +int uart_boot_selected(void); +int tftp_boot_selected(void); +int i2c_boot_selected(void); +int spi_boot_selected(void); +int mmc_boot_selected(void); + +extern u32 mpmc_conf_vals[]; + +struct chip_data { + int cpufreq; + int dramfreq; + int dramtype; + uchar version[32]; +}; + /* HW mac id in i2c memory definitions */ #define MAGIC_OFF 0x0 #define MAGIC_LEN 0x2 @@ -36,4 +60,10 @@ extern unsigned int setfreq_sz; #define MAC_OFF 0x2 #define MAC_LEN 0x6 +#define PNOR_WIDTH_8 0 +#define PNOR_WIDTH_16 1 +#define PNOR_WIDTH_32 2 +#define PNOR_WIDTH_NUM 3 +#define PNOR_WIDTH_SEARCH 0xff + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index b8fcf49..5f67a5f 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -46,7 +46,7 @@ struct misc_regs { u32 prsc2_clk_cfg; /* 0x48 */ u32 prsc3_clk_cfg; /* 0x4C */ u32 amem_cfg_ctrl; /* 0x50 */ - u32 port_cfg_ctrl; /* 0x54 */ + u32 expi_clk_cfg; /* 0x54 */ u32 reserved_1; /* 0x58 */ u32 clcd_synth_clk; /* 0x5C */ u32 irda_synth_clk; /* 0x60 */ @@ -101,6 +101,37 @@ struct misc_regs { u32 ras_gpp2_out; /* 0x800C */ }; +/* SYNTH_CLK value*/ +#define SYNTH23 0x00020003 + +/* PLLx_FRQ value */ +#if defined(CONFIG_SPEAR3XX) +#define FREQ_332 0xA600010C +#define FREQ_266 0x8500010C +#elif defined(CONFIG_SPEAR600) +#define FREQ_332 0xA600010F +#define FREQ_266 0x8500010F +#endif + +/* PLL_CTR_REG */ +#define MEM_CLK_SEL_MSK 0x70000000 +#define MEM_CLK_HCLK 0x00000000 +#define MEM_CLK_2HCLK 0x10000000 +#define MEM_CLK_PLL2 0x30000000 + +#define EXPI_CLK_CFG_LOW_COMPR 0x2000 +#define EXPI_CLK_CFG_CLK_EN 0x0400 +#define EXPI_CLK_CFG_RST 0x0200 +#define EXPI_CLK_SYNT_EN 0x0010 +#define EXPI_CLK_CFG_SEL_PLL2 0x0004 +#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 + +#define PLL2_CNTL_6UA 0x1c00 +#define PLL2_CNTL_SAMPLE 0x0008 +#define PLL2_CNTL_ENABLE 0x0004 +#define PLL2_CNTL_RESETN 0x0002 +#define PLL2_CNTL_LOCK 0x0001 + /* AUTO_CFG_REG value */ #define MISC_SOCCFGMSK 0x0000003F #define MISC_SOCCFG30 0x0000000C @@ -131,9 +162,112 @@ struct misc_regs { #define MISC_ETHENB 0x00800000 #define MISC_SMIENB 0x00200000 #define MISC_GPT3ENB 0x00010000 +#define MISC_GPIO4ENB 0x00002000 #define MISC_GPT2ENB 0x00000800 #define MISC_FSMCENB 0x00000200 #define MISC_I2CENB 0x00000080 +#define MISC_SSP2ENB 0x00000070 #define MISC_UART0ENB 0x00000008 +/* PERIPH_CLK_CFG */ +#define XTALTIMEEN 0x00000001 +#define PLLTIMEEN 0x00000002 +#define CLCDCLK_SYNTH 0x00000000 +#define CLCDCLK_48MHZ 0x00000004 +#define CLCDCLK_EXT 0x00000008 +#define UARTCLK_MASK (0x1 << 4) +#define UARTCLK_48MHZ 0x00000000 +#define UARTCLK_SYNTH 0x00000010 +#define IRDACLK_48MHZ 0x00000000 +#define IRDACLK_SYNTH 0x00000020 +#define IRDACLK_EXT 0x00000040 +#define RTC_DISABLE 0x00000080 +#define GPT1CLK_48MHZ 0x00000000 +#define GPT1CLK_SYNTH 0x00000100 +#define GPT2CLK_48MHZ 0x00000000 +#define GPT2CLK_SYNTH 0x00000200 +#define GPT3CLK_48MHZ 0x00000000 +#define GPT3CLK_SYNTH 0x00000400 +#define GPT4CLK_48MHZ 0x00000000 +#define GPT4CLK_SYNTH 0x00000800 +#define GPT5CLK_48MHZ 0x00000000 +#define GPT5CLK_SYNTH 0x00001000 +#define GPT1_FREEZE 0x00002000 +#define GPT2_FREEZE 0x00004000 +#define GPT3_FREEZE 0x00008000 +#define GPT4_FREEZE 0x00010000 +#define GPT5_FREEZE 0x00020000 + +/* PERIPH1_CLKEN bits */ +#define PERIPH_ARM1_WE 0x00000001 +#define PERIPH_ARM1 0x00000002 +#define PERIPH_ARM2 0x00000004 +#define PERIPH_UART1 0x00000008 +#define PERIPH_UART2 0x00000010 +#define PERIPH_SSP1 0x00000020 +#define PERIPH_SSP2 0x00000040 +#define PERIPH_I2C 0x00000080 +#define PERIPH_JPEG 0x00000100 +#define PERIPH_FSMC 0x00000200 +#define PERIPH_FIRDA 0x00000400 +#define PERIPH_GPT4 0x00000800 +#define PERIPH_GPT5 0x00001000 +#define PERIPH_GPIO4 0x00002000 +#define PERIPH_SSP3 0x00004000 +#define PERIPH_ADC 0x00008000 +#define PERIPH_GPT3 0x00010000 +#define PERIPH_RTC 0x00020000 +#define PERIPH_GPIO3 0x00040000 +#define PERIPH_DMA 0x00080000 +#define PERIPH_ROM 0x00100000 +#define PERIPH_SMI 0x00200000 +#define PERIPH_CLCD 0x00400000 +#define PERIPH_GMAC 0x00800000 +#define PERIPH_USBD 0x01000000 +#define PERIPH_USBH1 0x02000000 +#define PERIPH_USBH2 0x04000000 +#define PERIPH_MPMC 0x08000000 +#define PERIPH_RAMW 0x10000000 +#define PERIPH_MPMC_EN 0x20000000 +#define PERIPH_MPMC_WE 0x40000000 +#define PERIPH_MPMCMSK 0x60000000 + +#define PERIPH_CLK_ALL 0x0FFFFFF8 +#define PERIPH_RST_ALL 0x00000004 + +/* DDR_PAD values */ +#define DDR_PAD_CNF_MSK 0x0000ffff +#define DDR_PAD_SW_CONF 0x00060000 +#define DDR_PAD_SSTL_SEL 0x00000001 +#define DDR_PAD_DRAM_TYPE 0x00008000 + +/* DDR_COMP values */ +#define DDR_COMP_ACCURATE 0x00000010 + +/* SoC revision stuff */ +#define SOC_PRI_SHFT 16 +#define SOC_SEC_SHFT 8 + +/* Revision definitions */ +#define SOC_SPEAR_NA 0 + +/* + * The definitons have started from + * 101 for SPEAr6xx + * 201 for SPEAr3xx + * 301 for SPEAr13xx + */ +#define SOC_SPEAR600_AA 101 +#define SOC_SPEAR600_AB 102 +#define SOC_SPEAR600_BA 103 +#define SOC_SPEAR600_BB 104 +#define SOC_SPEAR600_BC 105 +#define SOC_SPEAR600_BD 106 + +#define SOC_SPEAR300 201 +#define SOC_SPEAR310 202 +#define SOC_SPEAR320 203 + +extern int get_socrev(void); + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h new file mode 100644 index 0000000..4f144ee --- /dev/null +++ b/arch/arm/include/asm/arch-spear/spr_ssp.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_SSP_H +#define _SPR_SSP_H + +struct ssp_regs { + u32 sspcr0; + u32 sspcr1; + u32 sspdr; + u32 sspsr; + u32 sspcpsr; + u32 sspimsc; + u32 sspicr; + u32 sspdmacr; +}; + +#define SSPCR0_FRF_MOT_SPI 0x0000 +#define SSPCR0_DSS_16BITS 0x000f + +#define SSPCR1_SSE 0x0002 + +#define SSPSR_TNF 0x2 +#define SSPSR_TFE 0x1 + +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h index 3c92f09..2393d89 100644 --- a/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __SYSCTRL_H +#define __SYSCTRL_H + struct syscntl_regs { u32 scctrl; u32 scsysstat; @@ -36,3 +39,14 @@ struct syscntl_regs { const u32 scperclken; const u32 scperstat; }; + +#define MODE_SHIFT 0x00000003 + +#define NORMAL 0x00000004 +#define SLOW 0x00000002 +#define DOZE 0x00000001 +#define SLEEP 0x00000000 + +#define PLL_TIM 0x01FFFFFF + +#endif -- 1.7.10.1

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[U-Boot] [PATCH 5/7] Makefile: Add u-boot.spr build target (SPEAr)
by Stefan Roese 08 May '12

08 May '12

On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. Both images are created using mkimage (crc etc), so that the ROM bootloader can check its integrity. Padding needs to be done to the SPL image (with mkimage header) and not the binary. Otherwise the resulting image which is loaded/copied by the ROM bootloader to SRAM doesn't fit. The resulting image containing both U-Boot images is called u-boot.spr. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- Makefile | 17 +++++++++++++++++ config.mk | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/Makefile b/Makefile index 023ea23..b177032 100644 --- a/Makefile +++ b/Makefile @@ -453,6 +453,22 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ -o $(obj)u-boot.sb +# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. +# Both images are created using mkimage (crc etc), so that the ROM +# bootloader can check its integrity. Padding needs to be done to the +# SPL image (with mkimage header) and not the binary. Otherwise the resulting image +# which is loaded/copied by the ROM bootloader to SRAM doesn't fit. +# The resulting image containing both U-Boot images is called u-boot.spr +$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ + -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ + of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null + dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \ + conv=notrunc 2>/dev/null + cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ + ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ @@ -765,6 +781,7 @@ clobber: tidy @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb + @rm -f $(obj)u-boot.spr @rm -f $(obj)tools/inca-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c diff --git a/config.mk b/config.mk index fa33e62..29e2380 100644 --- a/config.mk +++ b/config.mk @@ -201,6 +201,10 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) endif +ifneq ($(CONFIG_SPL_PAD_TO),) +CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) +endif + ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif -- 1.7.10.1

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