May 2012 - U-Boot

[U-Boot] [PATCH] misc:pmic:trats: Correct procedure of enabling/disabling USB regulators
by Lukasz Majewski 03 May '12

03 May '12

In the MAX8997, LDO regulators needs to preserve previously set voltage values. Signed-off-by: Lukasz Majewski <l.majewski(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> --- board/samsung/trats/trats.c | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-) diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 10cf5b3..a20268d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -218,6 +218,7 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; + u32 val = 0; struct pmic *p = get_pmic(); if (pmic_probe(p)) @@ -226,11 +227,17 @@ static int s5pc210_phy_control(int on) if (on) { ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_ON); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); } else { - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_OFF); } -- 1.7.2.3

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[U-Boot] [PATCH] checkpatch: warn of whitespace before semicolon at end of line.
by Eric Nelson 03 May '12

03 May '12

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- tools/checkpatch.pl | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl index 2048a44..0caffcb 100755 --- a/tools/checkpatch.pl +++ b/tools/checkpatch.pl @@ -3139,6 +3139,12 @@ sub process { "Statements terminations use 1 semicolon\n" . $herecurr); } +# check for multiple semicolons + if ($line =~ /\s+;$/) { + WARN("SPACEBEFORE_SEMICOLON", + "Blank before semicolon\n" . $herecurr); + } + # check for gcc specific __FUNCTION__ if ($line =~ /__FUNCTION__/) { WARN("USE_FUNC", -- 1.7.9

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[U-Boot] [PATCH] tegra2: trivially enable 13 mhz crystal frequency
by Lucas Stach 03 May '12

03 May '12

This is needed for upcoming Toradex Colibri T20 upstream support. Signed-off-by: Lucas Stach <dev(a)lynxeye.de> --- arch/arm/cpu/armv7/tegra2/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 39376ab..8084631 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -1027,7 +1027,10 @@ void clock_early_init(void) clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); break; - case CLOCK_OSC_FREQ_13_0: + case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8); + clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); + break; case CLOCK_OSC_FREQ_19_2: default: /* -- 1.7.10

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[U-Boot] U-boot Required
by Amber and Sarosh 03 May '12

03 May '12

Hi Can somebody mail us the u-boot files for these PR1 Appliances? ; Appliance with 2xMT48LC32M8A2P-75 i.e. 64MB SDRAM Appliance with 2xhy57v56820bt-h The one available on the switchfin site i.e. u-boot-pr1-ub2.30 is only for Appliance with 2xMT48LC64M8A2P-75 i.e. 128 MB SDRAM and is not working with other devices mentioned above. Waiting for your response. Regards Amber and Sarosh

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[U-Boot] [PATCH 1/5] msm7x30: Add support for low speed uart on msm7x30
by mohamed.haneef＠lntinfotech.com 03 May '12

03 May '12

From: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> * Support for low speed uart Signed-off-by: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> --- drivers/serial/Makefile | 1 + drivers/serial/serial_msm_uart.c | 206 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 207 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_msm_uart.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 616b857..2801edc 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -55,6 +55,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o +COBJS-$(CONFIG_MSM_UART) += serial_msm_uart.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_msm_uart.c b/drivers/serial/serial_msm_uart.c new file mode 100644 index 0000000..8cafa7a --- /dev/null +++ b/drivers/serial/serial_msm_uart.c @@ -0,0 +1,206 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/iomap.h> +#include <asm/io.h> +#include <asm/types.h> + +#define UART_MR1 0x0000 + +#define UART_MR1_AUTO_RFR_LEVEL0(n) (((n) & 0x3f) << 8) +#define UART_MR1_RX_RDY_CTL (1 << 7) +#define UART_MR1_CTS_CTL (1 << 6) +#define UART_MR1_AUTO_RFR_LEVEL1(n) ((n) & 0x3f) + +#define UART_MR2 0x0004 +#define UART_MR2_ERROR_MODE (1 << 6) +#define UART_MR2_BITS_PER_CHAR_5 (0 << 4) +#define UART_MR2_BITS_PER_CHAR_6 (1 << 4) +#define UART_MR2_BITS_PER_CHAR_7 (2 << 4) +#define UART_MR2_BITS_PER_CHAR_8 (3 << 4) +#define UART_MR2_STOP_BIT_LEN_0563 (0 << 2) +#define UART_MR2_STOP_BIT_LEN_1000 (1 << 2) +#define UART_MR2_STOP_BIT_LEN_1563 (2 << 2) +#define UART_MR2_STOP_BIT_LEN_2000 (3 << 2) +#define UART_MR2_PARITY_MODE_NONE (0) +#define UART_MR2_PARITY_MODE_ODD (1) +#define UART_MR2_PARITY_MODE_EVEN (2) +#define UART_MR2_PARITY_MODE_SPACE (3) + +#define UART_CSR 0x0008 +#define UART_CSR_115200 0xFF +#define UART_CSR_57600 0xEE +#define UART_CSR_38400 0xDD +#define UART_CSR_19200 0xBB + +#define UART_TF 0x000C + +#define UART_CR 0x0010 +#define UART_CR_CMD_NULL (0 << 4) +#define UART_CR_CMD_RESET_RX (1 << 4) +#define UART_CR_CMD_RESET_TX (2 << 4) +#define UART_CR_CMD_RESET_ERR (3 << 4) +#define UART_CR_CMD_RESET_BCI (4 << 4) +#define UART_CR_CMD_START_BREAK (5 << 4) +#define UART_CR_CMD_STOP_BREAK (6 << 4) +#define UART_CR_CMD_RESET_CTS_N (7 << 4) +#define UART_CR_CMD_PACKET_MODE (9 << 4) +#define UART_CR_CMD_MODE_RESET (12 << 4) +#define UART_CR_CMD_SET_RFR_N (13 << 4) +#define UART_CR_CMD_RESET_RFR_ND (14 << 4) +#define UART_CR_TX_DISABLE (1 << 3) +#define UART_CR_TX_ENABLE (1 << 3) +#define UART_CR_RX_DISABLE (1 << 3) +#define UART_CR_RX_ENABLE (1 << 3) + +#define UART_IMR 0x0014 +#define UART_IMR_RXLEV (1 << 4) +#define UART_IMR_TXLEV (1 << 0) + +#define UART_IPR 0x0018 +#define UART_TFWR 0x001C +#define UART_RFWR 0x0020 +#define UART_HCR 0x0024 + +#define UART_MREG 0x0028 +#define UART_NREG 0x002C +#define UART_DREG 0x0030 +#define UART_MNDREG 0x0034 +#define UART_IRDA 0x0038 +#define UART_MISR_MODE 0x0040 +#define UART_MISR_RESET 0x0044 +#define UART_MISR_EXPORT 0x0048 +#define UART_MISR_VAL 0x004C +#define UART_TEST_CTRL 0x0050 + +#define UART_SR 0x0008 +#define UART_SR_HUNT_CHAR (1 << 7) +#define UART_SR_RX_BREAK (1 << 6) +#define UART_SR_PAR_FRAME_ERR (1 << 5) +#define UART_SR_OVERRUN (1 << 4) +#define UART_SR_TX_EMPTY (1 << 3) +#define UART_SR_TX_READY (1 << 2) +#define UART_SR_RX_FULL (1 << 1) +#define UART_SR_RX_READY (1 << 0) + +#define UART_RF 0x000C +#define UART_MISR 0x0010 +#define UART_ISR 0x0014 + + +#if PLATFORM_MSM7X30 +static unsigned uart_base = MSM_UART2_BASE; +#elif PLATFORM_MSM7X27A +static unsigned uart_base = MSM_UART1_BASE; +#else +static unsigned uart_base = MSM_UART3_BASE; +#endif + +#define uwr(v, a) writel(v, uart_base + (a)) +#define urd(a) readl(uart_base + (a)) + +void uart_init(void) +{ + uwr(0x0A, UART_CR); /* disable TX and RX */ + uwr(0x30, UART_CR); /* reset error status */ + uwr(0x10, UART_CR); /* reset receiver */ + uwr(0x20, UART_CR); /* reset transmitter */ +#if PLATFORM_QSD8K || PLATFORM_MSM7X30 || PLATFORM_MSM7X27A + /* TCXO */ + uwr(0x06, UART_MREG); + uwr(0xF1, UART_NREG); + uwr(0x0F, UART_DREG); + uwr(0x1A, UART_MNDREG); +#else + /* TCXO/4 */ + uwr(0xC0, UART_MREG); + uwr(0xAF, UART_NREG); + uwr(0x80, UART_DREG); + uwr(0x19, UART_MNDREG); +#endif + uwr(0x10, UART_CR); /* reset RX */ + uwr(0x20, UART_CR); /* reset TX */ + uwr(0x30, UART_CR); /* reset error status */ + uwr(0x40, UART_CR); /* reset RX break */ + uwr(0x70, UART_CR); /* rest? */ + uwr(0xD0, UART_CR); /* reset */ + uwr(0x7BF, UART_IPR); /* stale timeout = 630 * bitrate */ + uwr(0, UART_IMR); + uwr(115, UART_RFWR); /* RX watermark = 58 * 2 - 1 */ + uwr(10, UART_TFWR); /* TX watermark */ + uwr(0, UART_RFWR); + uwr(UART_CSR_115200, UART_CSR); + uwr(0, UART_IRDA); + uwr(0x1E, UART_HCR); + uwr(16, UART_MR1); + uwr(0x34, UART_MR2); /* 8N1 */ + uwr(0x05, UART_CR); /* enable TX & RX */ + +} + +static int _uart_putc(int port, char c) +{ + while (!(urd(UART_SR) & UART_SR_TX_READY)) + ; + uwr(c, UART_TF); + return 0; +} + +int serial_init(void) +{ + uart_init(); + return 0; +} + +void serial_putc(char c) +{ + if (c == '\n') + _uart_putc(0, '\r'); + _uart_putc(0, c); +} + +void serial_putc_raw(const char c) +{ + _uart_putc(0, c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} + +int serial_getc() +{ + while (!(urd(UART_SR) & UART_SR_RX_READY)) + ; + return urd(UART_RF); +} + +int serial_tstc() +{ + return urd(UART_SR) & UART_SR_RX_READY; +} + +void serial_setbrg() +{ +} + -- 1.7.1 The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"

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[U-Boot] "make menuconfig" does not work
by hong zhang 03 May '12

03 May '12

List, "make menuconfig" does not work for u-boot under panadaboard. Old mailing list said because of no Kconfig in u-boot tree. Any plan to add Kconfig or any other way to configure u-boot? Thanks for any help! ---henry

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[U-Boot] [PATCH] M28: Enable FDT support
by Marek Vasut 03 May '12

03 May '12

Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Detlev Zundel <dzu(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> --- include/configs/m28evk.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 7e1661e..b419516 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -43,6 +43,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT +#define CONFIG_OF_LIBFDT + /* * SPL */ -- 1.7.10

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[U-Boot] [PATCH] powerpc/p1010rdb: add readme document for p1010rdb
by Shengzhou Liu 02 May '12

02 May '12

Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- doc/README.p1010rdb | 138 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 138 insertions(+), 0 deletions(-) create mode 100644 doc/README.p1010rdb diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb new file mode 100644 index 0000000..78b1dee --- /dev/null +++ b/doc/README.p1010rdb @@ -0,0 +1,138 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + — 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + — 32 Mbyte NOR flash single-chip memory + — 32 Mbyte NAND flash memory + — 256 Kbit M24256 I2C EEPROM + — 16 Mbyte SPI memory + — I2C Board EEPROM 128x8 bit memory + — SD/MMC connector to interface with the SD memory card +Interfaces: + — PCIe: + – Lane0: x1 mini-PCIe slot + – Lane1: x1 PCIe standard slot + — SATA: + – 1 internal SATA connector to 2.5” 160G SATA2 HDD + – 1 eSATA connector to rear panel + — 10/100/1000 BaseT Ethernet ports: + – eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + – eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + – eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + — USB 2.0 port: + – x1 USB2.0 port: via an ULPI PHY to micro-AB connector + – x1 USB2.0 poort via an internal PHY to micro-AB connector + — FlexCAN ports: + – x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + — DUART interface: + – DUART interface: supports two UARTs up to 115200 bps for + console display + – RJ45 connectors are used for these 2 UART ports. + — TDM + – 2 FXS ports connected via an external SLIC to the TDM + interface. SLIC is controllled via SPI. + – 1 FXO port connected via a relay to FXS for switchover to + POTS +Board connectors: + — Mini-ITX power supply connector + — JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + — support critical POR setting changed via switch on board +PCB + — 6-layer routing (4-layer signals, 2-layer power and ground) + + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + +Please refer to P1010-RDB User Guide for details. + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn u-boot to NOR flash +======================================= +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff80000 +$filesize + => erase eff80000 +$filesize + => cp.b $loadaddr eff80000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + + +Build and burn u-boot to NAND flash +======================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + + +Build and burn u-boot to SPI flash +======================================= +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + -- 1.7.0.4

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[U-Boot] [RESEND PATCH 0/5] usb:udc:composite: Samsung's UDC cleanup and composite gadget implementation
by Lukasz Majewski 02 May '12

02 May '12

This patch serie has been created as a combination of several patches previously sent to u-boot mailing list: - Duplicated USB code has been removed. - Samsung's UDC driver has been cleaned up -> DEBUG_ macros have been replaced with debug_cond() calls. - Version v4. of composite gadget implementation for u-boot. Those patches have been rebased on top of u-boot-usb/master. Lukasz Majewski (5): usb:udc: Remove duplicated USB definitions from include/linux/usb/ch9.h file usb:udc:samsung:cleanup Replace DEBUG_* macros with debug_cond() calls usb:gadget:composite USB composite gadget support usb:gadget:composite: Support for composite at gadget.h usb:udc:samsung Add functions for storing private gadget data in UDC driver drivers/usb/gadget/composite.c | 1082 +++++++++++++++++++++++++++++ drivers/usb/gadget/config.c | 1 + drivers/usb/gadget/epautoconf.c | 1 + drivers/usb/gadget/ether.c | 1 + drivers/usb/gadget/s3c_udc_otg.c | 53 +- drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 287 +++++--- drivers/usb/gadget/usbstring.c | 1 + include/linux/usb/ch9.h | 67 -- include/linux/usb/composite.h | 350 ++++++++++ include/linux/usb/gadget.h | 6 + include/usb/lin_gadget_compat.h | 24 +- include/usb/s3c_udc.h | 49 +-- 12 files changed, 1668 insertions(+), 254 deletions(-) create mode 100644 drivers/usb/gadget/composite.c create mode 100644 include/linux/usb/composite.h -- 1.7.2.3

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Re: [U-Boot] [PATCH] USB: S5P: Add ehci support
by Marek Vasut 02 May '12

02 May '12

Dear RAJESHWARI S SHINDE, > Hi Marek, > > Thank you for the comments, would modify the code and send V2. Thank you for your patches and your work, they are what's important here :-) > Regards, > Rajeshwari Shinde. > > ------- Original Message ------- > Sender : Marek Vasut<marex(a)denx.de> > Date : May 02, 2012 06:17 (GMT+09:00) > Title : Re: [U-Boot] [PATCH] USB: S5P: Add ehci support > > Dear Rajeshwari Shinde, > > > This patch adds ehci driver support for s5p. > > It'd be awesome if you CCed me ;-) > Also, it might be worth CCing Lukasz? > > > Signed-off-by: Vivek Gautam > > Signed-off-by: Rajeshwari Shinde > > --- > > > > arch/arm/include/asm/arch-exynos/ehci-s5p.h | 66 ++++++++++++++++ > > drivers/usb/host/Makefile | 1 + > > drivers/usb/host/ehci-s5p.c | 113 > > > > +++++++++++++++++++++++++++ 3 files changed, 180 insertions(+), 0 > > deletions(-) > > > > create mode 100755 arch/arm/include/asm/arch-exynos/ehci-s5p.h > > create mode 100644 drivers/usb/host/ehci-s5p.c > > > > diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h > > b/arch/arm/include/asm/arch-exynos/ehci-s5p.h new file mode 100755 > > index 0000000..68feb85 > > --- /dev/null > > +++ b/arch/arm/include/asm/arch-exynos/ehci-s5p.h > > @@ -0,0 +1,66 @@ > > +/* > > + * SAMSUNG S5P USB HOST EHCI Controller > > + * > > + * Copyright (C) 2012 Samsung Electronics Co.Ltd > > + * Vivek Gautam > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > > + * MA 02110-1301 USA > > + */ > > + > > +#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ > > +#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ > > + > > +#define CLK_24MHZ 5 > > + > > +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) > > +#define HOST_CTRL0_COMMONON_N (1 << 9) > > +#define HOST_CTRL0_SIDDQ (1 << 6) > > +#define HOST_CTRL0_FORCESLEEP (1 << 5) > > +#define HOST_CTRL0_FORCESUSPEND (1 << 4) > > +#define HOST_CTRL0_WORDINTERFACE (1 << 3) > > +#define HOST_CTRL0_UTMISWRST (1 << 2) > > +#define HOST_CTRL0_LINKSWRST (1 << 1) > > +#define HOST_CTRL0_PHYSWRST (1 << 0) > > + > > +#define HOST_CTRL0_FSEL_MASK (7 << 16) > > + > > +#define EHCICTRL_ENAINCRXALIGN (1 << 29) > > +#define EHCICTRL_ENAINCR4 (1 << 28) > > +#define EHCICTRL_ENAINCR8 (1 << 27) > > +#define EHCICTRL_ENAINCR16 (1 << 26) > > + > > +/* Register map for PHY control */ > > +struct s5p_usb_phy { > > + unsigned int usbphyctrl0; > > + unsigned int usbphytune0; > > + unsigned int reserved1[2]; > > + unsigned int hsicphyctrl1; > > + unsigned int hsicphytune1; > > + unsigned int reserved2[2]; > > + unsigned int hsicphyctrl2; > > + unsigned int hsicphytune2; > > + unsigned int reserved3[2]; > > + unsigned int ehcictrl; > > + unsigned int ohcictrl; > > + unsigned int usbotgsys; > > + unsigned int reserved4; > > + unsigned int usbotgtune; > > +}; > > + > > +/* Switch on the VBUS power. */ > > +int board_usb_vbus_init(void); > > + > > +#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ > > diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile > > index 0d4657e..59c3e57 100644 > > --- a/drivers/usb/host/Makefile > > +++ b/drivers/usb/host/Makefile > > @@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o > > > > COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o > > COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o > > COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o > > > > +COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o > > > > COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o > > COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o > > > > diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c > > new file mode 100644 > > index 0000000..ac9f061 > > --- /dev/null > > +++ b/drivers/usb/host/ehci-s5p.c > > @@ -0,0 +1,113 @@ > > +/* > > + * SAMSUNG S5P USB HOST EHCI Controller > > + * > > + * Copyright (C) 2012 Samsung Electronics Co.Ltd > > + * Vivek Gautam > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation; either version 2 of > > + * the License, or (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program; if not, write to the Free Software > > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > > + * MA 02110-1301 USA > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include "ehci.h" > > +#include "ehci-core.h" > > + > > +/* Setup the EHCI host controller. */ > > +static void setup_usb_phy(struct s5p_usb_phy *usb) > > +{ > > + unsigned int hostphy_ctrl0; > > + > > + /* Setting up host and device simultaneously */ > > + hostphy_ctrl0 = readl(&usb->usbphyctrl0); > > + hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | > > + HOST_CTRL0_COMMONON_N | > > + /* HOST Phy setting */ > > + HOST_CTRL0_PHYSWRST | > > + HOST_CTRL0_PHYSWRSTALL | > > + HOST_CTRL0_SIDDQ | > > + HOST_CTRL0_FORCESUSPEND | > > + HOST_CTRL0_FORCESLEEP); > > + hostphy_ctrl0 |= (/* Setting up the ref freq */ > > + CLK_24MHZ << 16 | > > Parens around (CLK << 16). > -- Corrected > > > + /* HOST Phy setting */ > > + HOST_CTRL0_LINKSWRST | > > + HOST_CTRL0_UTMISWRST); > > + writel(hostphy_ctrl0, &usb->usbphyctrl0); > > Use clrsetbits_le32() please. > -- Corrected > > > + udelay(10); > > + clrbits_le32(&usb->usbphyctrl0, > > + HOST_CTRL0_LINKSWRST | > > + HOST_CTRL0_UTMISWRST); > > + udelay(20); > > + > > + /* EHCI Ctrl setting */ > > + setbits_le32(&usb->ehcictrl, > > + EHCICTRL_ENAINCRXALIGN | > > + EHCICTRL_ENAINCR4 | > > + EHCICTRL_ENAINCR8 | > > + EHCICTRL_ENAINCR16); > > +} > > + > > +/* Reset the EHCI host controller. */ > > +static void reset_usb_phy(struct s5p_usb_phy *usb) > > +{ > > + /* HOST_PHY reset */ > > + setbits_le32(&usb->usbphyctrl0, > > + HOST_CTRL0_PHYSWRST | > > + HOST_CTRL0_PHYSWRSTALL | > > + HOST_CTRL0_SIDDQ | > > + HOST_CTRL0_FORCESUSPEND | > > + HOST_CTRL0_FORCESLEEP); > > +} > > + > > +/* > > + * EHCI-initialization > > + * Create the appropriate control structures to manage > > + * a new EHCI host controller. > > + */ > > +int ehci_hcd_init(void) > > +{ > > + struct s5p_usb_phy *usb; > > + > > + usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); > > + setup_usb_phy(usb); > > + > > + hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE); > > + hcor = (struct ehci_hcor *)((uint32_t) hccr > > + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); > > + > > + printf("\n usb cmd addr = %x", &hcor->or_usbcmd); > > Either debug() or remove the above ;-) > -- Removed > > > + debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n", > > + (uint32_t)hccr, (uint32_t)hcor, > > + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); > > + > > + return 0; > > +} > > + > > +/* > > + * Destroy the appropriate control structures corresponding > > + * the EHCI host controller. > > + */ > > +int ehci_hcd_stop() > > +{ > > + struct s5p_usb_phy *usb; > > + > > + usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); > > + reset_usb_phy(usb); > > Well ... if reseting the PHY is enough to stop the controller, I won't > object ;-) > ---- Verified the user manual and this seems to be enough to reset the host > controller. > > This patch gives a good impression, I see V2 and then mainline acceptance > :) > > > + > > + return 0; > > +}

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