January 2012 - U-Boot

[U-Boot] [PATCH 1/8 v2] powerpc/srio: Rewrite the struct ccsr_rio
by Liu Gang 17 Jan '12

17 Jan '12

Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- Changes in v2: - Change the subject and commit message. - Remove the offsets in the comments. - Rewrite the struct for the support of two ports and two message units registers. arch/powerpc/include/asm/immap_85xx.h | 383 +++++++++++++++++++-------------- 1 files changed, 223 insertions(+), 160 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8..a65fc1c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1353,171 +1353,234 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ +#define SRIO_PORT_MAX_NUM 2 /* SRIO port max number */ +#define SRIO_OB_WIN_NUM 9 /* SRIO outbound window number */ +#define SRIO_IB_WIN_NUM 5 /* SRIO inbound window number */ +#define SRIO_MSG_UNIT_NUM 2 /* SRIO message unit number */ + +/* Architectural regsiters */ +struct rio_arch { + u32 didcar; /* Device Identity CAR */ + u32 dicar; /* Device Information CAR */ + u32 aidcar; /* Assembly Identity CAR */ + u32 aicar; /* Assembly Information CAR */ + u32 pefcar; /* Processing Element Features CAR */ + u8 res0[4]; + u32 socar; /* Source Operations CAR */ + u32 docar; /* Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* Mailbox CSR */ + u32 pwdcsr; /* Port-Write and Doorbell CSR */ u8 res2[4]; u32 pellccsr; /* Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* Local Configuration Space BACSR */ + u32 bdidcsr; /* Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; + u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ + u32 ctcsr; /* Component Tag CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial Port registers */ +struct rio_lp_serial_port { + u32 plmreqcsr; /* Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* Port Link Maintenance Response CS */ + u32 plascsr; /* Port Local Ackid Status CSR */ + u8 res0[12]; + u32 pescsr; /* Port Error and Status CSR */ + u32 pccsr; /* Port Control CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial registers */ +struct rio_lp_serial { + u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ + u8 res0[28]; + u32 pltoccsr; /* Port Link Time-out CCSR */ + u32 prtoccsr; /* Port Response Time-out CCSR */ + u8 res1[20]; + u32 pgccsr; /* Port General CSR */ + struct rio_lp_serial_port port[SRIO_PORT_MAX_NUM]; +}; + +/* Logical error reporting registers */ +struct rio_logical_err { + u32 erbh; /* Error Reporting Block Header Register */ + u8 res0[4]; + u32 ltledcsr; /* Logical/Transport layer error DCSR */ + u32 ltleecsr; /* Logical/Transport layer error ECSR */ + u8 res1[4]; + u32 ltlaccsr; /* Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* Logical/Transport layer control CCSR */ +}; + +/* Physical error reporting port registers */ +struct rio_phys_err_port { + u32 edcsr; /* Port error detect CSR */ + u32 erecsr; /* Port error rate enable CSR */ + u32 ecacsr; /* Port error capture attributes CSR */ + u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ + u32 peccsr[3]; /* Port error capture CSR */ + u8 res0[12]; + u32 ercsr; /* Port error rate CSR */ + u32 ertcsr; /* Port error rate threshold CSR */ + u8 res1[16]; +}; + +/* Physical error reporting registers */ +struct rio_phys_err { + struct rio_phys_err_port port[SRIO_PORT_MAX_NUM]; +}; + +/* Implementation Space: General Port-Common */ +struct rio_impl_common { + u8 res0[4]; + u32 llcr; /* Logical Layer Configuration Register */ + u8 res1[8]; + u32 epwisr; /* Error / Port-Write Interrupt SR */ + u8 res2[12]; + u32 lretcr; /* Logical Retry Error Threshold CR */ + u8 res3[92]; + u32 pretcr; /* Physical Retry Erorr Threshold CR */ + u8 res4[124]; +}; + +/* Implementation Space: Port Specific */ +struct rio_impl_port_spec { + u32 adidcsr; /* Port Alt. Device ID CSR */ + u8 res0[28]; + u32 ptaacr; /* Port Pass-Through/Accept-All CR */ + u32 lopttlcr; + u8 res1[8]; + u32 iecsr; /* Port Implementation Error CSR */ + u8 res2[12]; + u32 pcr; /* Port Phsyical Configuration Register */ + u8 res3[20]; + u32 slcsr; /* Port Serial Link CSR */ + u8 res4[4]; + u32 sleicr; /* Port Serial Link Error Injection */ + u32 a0txcr; /* Port Arbitration 0 Tx CR */ + u32 a1txcr; /* Port Arbitration 1 Tx CR */ + u32 a2txcr; /* Port Arbitration 2 Tx CR */ + u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ + u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ +}; + +/* Implementation Space: register */ +struct rio_implement { + struct rio_impl_common com; + struct rio_impl_port_spec port[SRIO_PORT_MAX_NUM]; +}; + +/* Revision Control Register */ +struct rio_rev_ctrl { + u32 ipbrr[2]; /* IP Block Revision Register */ +}; + +struct rio_atmu_row { + u32 rowtar; /* RapidIO Outbound Window TAR */ + u32 rowtear; /* RapidIO Outbound Window TEAR */ + u32 rowbar; + u8 res0[4]; + u32 rowar; /* RapidIO Outbound Attributes Register */ + u32 rowsr[3]; /* Port RapidIO outbound window segment register */ +}; + +struct rio_atmu_riw { + u32 riwtar; /* RapidIO Inbound Window Translation AR */ + u8 res0[4]; + u32 riwbar; /* RapidIO Inbound Window Base AR */ + u8 res1[4]; + u32 riwar; /* RapidIO Inbound Attributes Register */ + u8 res2[12]; +}; + +/* ATMU window registers */ +struct rio_atmu_win { + struct rio_atmu_row outbw[SRIO_OB_WIN_NUM]; + u8 res0[64]; + struct rio_atmu_riw inbw[SRIO_IB_WIN_NUM]; +}; + +struct rio_atmu { + struct rio_atmu_win port[SRIO_PORT_MAX_NUM]; +}; + +struct rio_msg { + u32 omr; /* Outbound Mode Register */ + u32 osr; /* Outbound Status Register */ + u32 eodqdpar; /* Extended Outbound DQ DPAR */ + u32 odqdpar; /* Outbound Descriptor Queue DPAR */ + u32 eosar; /* Extended Outbound Unit Source AR */ + u32 osar; /* Outbound Unit Source AR */ + u32 odpr; /* Outbound Destination Port Register */ + u32 odatr; /* Outbound Destination Attributes Register */ + u32 odcr; /* Outbound Doubleword Count Register */ + u32 eodqepar; /* Extended Outbound DQ EPAR */ + u32 odqepar; /* Outbound Descriptor Queue EPAR */ + u32 oretr; /* Outbound Retry Error Threshold Register */ + u32 omgr; /* Outbound Multicast Group Register */ + u32 omlr; /* Outbound Multicast List Register */ + u8 res0[40]; + u32 imr; /* Outbound Mode Register */ + u32 isr; /* Inbound Status Register */ + u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* Inbound Frame Queue EPAR */ + u32 imirir; /* Inbound Maximum Interrutp RIR */ + u8 res1[4]; + u32 eihqepar; /* Extended inbound message header queue EPAR */ + u32 ihqepar; /* Inbound message header queue EPAR */ + u8 res2[120]; +}; + +struct rio_dbell { + u32 odmr; /* Outbound Doorbell Mode Register */ + u32 odsr; /* Outbound Doorbell Status Register */ + u8 res0[16]; + u32 oddpr; /* Outbound Doorbell Destination Port */ + u32 oddatr; /* Outbound Doorbell Destination AR */ + u8 res1[12]; + u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ + u8 res2[48]; + u32 idmr; /* Inbound Doorbell Mode Register */ + u32 idsr; /* Inbound Doorbell Status Register */ + u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* Inbound Doorbell Queue EPAR */ + u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ +}; + +struct rio_pw { + u32 pwmr; /* Port-Write Mode Register */ + u32 pwsr; /* Port-Write Status Register */ + u32 epwqbar; /* Extended Port-Write Queue BAR */ + u32 pwqbar; /* Port-Write Queue Base Address Register */ +}; + +/* RapidIO Registers */ +struct ccsr_rio { + struct rio_arch arch; + u8 res0[144]; + struct rio_lp_serial lp_serial; + u8 res1[1152]; + struct rio_logical_err logical_err; + u8 res2[32]; + struct rio_phys_err phys_err; + u8 res3[63808]; + struct rio_implement impl; + u8 res4[2552]; + struct rio_rev_ctrl rev; + struct rio_atmu atmu; + u8 res5[8192]; + struct rio_msg msg[SRIO_MSG_UNIT_NUM]; + u8 res6[512]; + struct rio_dbell dbell; + u8 res7[100]; + struct rio_pw pw; +}; /* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { -- 1.7.3.1

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[U-Boot] [PATCH 3/3] ARM: AM33XX: Add i2c support
by Patil, Rachna 17 Jan '12

17 Jan '12

Add i2c driver board hookup for AM335X EVM. Signed-off-by: Chandan Nath <chandan.nath(a)ti.com> Signed-off-by: Patil, Rachna <rachna(a)ti.com> --- arch/arm/cpu/armv7/am33xx/clock.c | 5 ++ arch/arm/include/asm/arch-am33xx/common_def.h | 1 + arch/arm/include/asm/arch-am33xx/cpu.h | 3 +- arch/arm/include/asm/arch-am33xx/i2c.h | 81 +++++++++++++++++++++++++ board/ti/am335x/evm.c | 6 ++ board/ti/am335x/mux.c | 14 ++++ include/configs/am335x_evm.h | 9 +++ 7 files changed, 118 insertions(+), 1 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/i2c.h diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 98cfd93..bbb9c13 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -113,6 +113,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) ; + + /* i2c0 */ + writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); + while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/include/asm/arch-am33xx/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h index 767932d..aa3b554 100644 --- a/arch/arm/include/asm/arch-am33xx/common_def.h +++ b/arch/arm/include/asm/arch-am33xx/common_def.h @@ -18,5 +18,6 @@ extern void enable_uart0_pin_mux(void); extern void enable_mmc0_pin_mux(void); +extern void enable_i2c0_pin_mux(void); #endif/*__COMMON_DEF_H__ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 25558a2..cd002e6 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -95,7 +95,8 @@ struct cm_wkuppll { unsigned int divm2dpllper; /* offset 0xAC */ unsigned int resv11[1]; unsigned int wkup_uart0ctrl; /* offset 0xB4 */ - unsigned int resv12[8]; + unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ + unsigned int resv12[7]; unsigned int divm6dpllcore; /* offset 0xD8 */ }; diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h new file mode 100644 index 0000000..366e2bb --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _I2C_H_ +#define _I2C_H_ + +#define I2C_BASE1 0x44E0B000 +#define I2C_BASE2 0x4802A000 +#define I2C_BASE3 0x4819C000 +#define I2C_BUS_MAX 3 + +#define I2C_DEFAULT_BASE I2C_BASE1 + +struct i2c { + unsigned short revnb_lo; /* 0x00 */ + unsigned short res1; + unsigned short revnb_hi; /* 0x04 */ + unsigned short res2[13]; + unsigned short sysc; /* 0x20 */ + unsigned short res3; + unsigned short irqstatus_raw; /* 0x24 */ + unsigned short res4; + unsigned short stat; /* 0x28 */ + unsigned short res5; + unsigned short ie; /* 0x2C */ + unsigned short res6; + unsigned short irqenable_clr; /* 0x30 */ + unsigned short res7; + unsigned short iv; /* 0x34 */ + unsigned short res8[45]; + unsigned short syss; /* 0x90 */ + unsigned short res9; + unsigned short buf; /* 0x94 */ + unsigned short res10; + unsigned short cnt; /* 0x98 */ + unsigned short res11; + unsigned short data; /* 0x9C */ + unsigned short res13; + unsigned short res14; /* 0xA0 */ + unsigned short res15; + unsigned short con; /* 0xA4 */ + unsigned short res16; + unsigned short oa; /* 0xA8 */ + unsigned short res17; + unsigned short sa; /* 0xAC */ + unsigned short res18; + unsigned short psc; /* 0xB0 */ + unsigned short res19; + unsigned short scll; /* 0xB4 */ + unsigned short res20; + unsigned short sclh; /* 0xB8 */ + unsigned short res21; + unsigned short systest; /* 0xBC */ + unsigned short res22; + unsigned short bufstat; /* 0xC0 */ + unsigned short res23; +}; + +#define I2C_IP_CLK 48000000 +#define I2C_INTERNAL_SAMLPING_CLK 12000000 + +#endif /* _I2C_H_ */ diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c index 6a9f788..158c71f 100644 --- a/board/ti/am335x/evm.c +++ b/board/ti/am335x/evm.c @@ -42,6 +42,12 @@ int init_basic_setup(void) int board_init(void) { enable_uart0_pin_mux(); + +#ifdef CONFIG_I2C + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + init_basic_setup(); return 0; diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 4cb0cdf..ac90c35 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -272,6 +272,14 @@ static struct module_pin_mux mmc0_pin_mux[] = { }; #endif +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + /* * Configure the pin mux for the module */ @@ -297,3 +305,9 @@ void enable_mmc0_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); } #endif + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 2cea1f4..6683b3e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -103,6 +103,14 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP24XX_I2C + #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } @@ -131,6 +139,7 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT -- 1.7.1

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[U-Boot] [PATCH 1/3] ARM: I2C: I2C Multi byte address support
by Patil, Rachna 17 Jan '12

17 Jan '12

Existing OMAP I2C driver does not support address length greater than one. Hence this patch is to add support for 2 byte address read/write. Signed-off-by: Philip, Avinash <avinashphilip(a)ti.com> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar(a)ti.com> Signed-off-by: Patil, Rachna <rachna(a)ti.com> --- drivers/i2c/omap24xx_i2c.c | 477 ++++++++++++++++++++++++++++---------------- drivers/i2c/omap24xx_i2c.h | 2 + 2 files changed, 306 insertions(+), 173 deletions(-) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 4ae237a..88e26b2 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -29,10 +29,11 @@ DECLARE_GLOBAL_DATA_PTR; -#define I2C_TIMEOUT 1000 +#define I2C_TIMEOUT (1 << 31) +#define I2C_STAT_TIMEO 10 -static void wait_for_bb(void); -static u16 wait_for_pin(void); +static u32 wait_for_bb(void); +static u32 wait_for_status_mask(u16 mask); static void flush_fifo(void); static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; @@ -45,7 +46,6 @@ void i2c_init(int speed, int slaveadd) int psc, fsscll, fssclh; int hsscll = 0, hssclh = 0; u32 scll, sclh; - int timeout = I2C_TIMEOUT; /* Only handle standard, fast and high speeds */ if ((speed != OMAP_I2C_STANDARD) && @@ -107,24 +107,14 @@ void i2c_init(int speed, int slaveadd) sclh = (unsigned int)fssclh; } + if (gd->flags & GD_FLG_RELOC) + bus_initialized[current_bus] = 1; + if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); } - writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ - udelay(1000); - - writew(I2C_CON_EN, &i2c_base->con); - while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { - if (timeout <= 0) { - printf("ERROR: Timeout in soft-reset\n"); - return; - } - udelay(1000); - } - - writew(0, &i2c_base->con); writew(psc, &i2c_base->psc); writew(scll, &i2c_base->scll); writew(sclh, &i2c_base->sclh); @@ -140,81 +130,6 @@ void i2c_init(int speed, int slaveadd) flush_fifo(); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); - - if (gd->flags & GD_FLG_RELOC) - bus_initialized[current_bus] = 1; -} - -static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb(); - - /* one byte only */ - writew(1, &i2c_base->cnt); - /* set slave address */ - writew(devaddr, &i2c_base->sa); - /* no stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | - I2C_CON_TRX, &i2c_base->con); - - /* send register offset */ - while (1) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { - i2c_error = 1; - goto read_exit; - } - if (status & I2C_STAT_XRDY) { - /* Important: have to use byte access */ - writeb(regoffset, &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); - } - if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); - break; - } - } - - /* set slave address */ - writew(devaddr, &i2c_base->sa); - /* read one byte from slave */ - writew(1, &i2c_base->cnt); - /* need stop bit here */ - writew(I2C_CON_EN | I2C_CON_MST | - I2C_CON_STT | I2C_CON_STP, - &i2c_base->con); - - /* receive data */ - while (1) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { - i2c_error = 1; - goto read_exit; - } - if (status & I2C_STAT_RRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) - *value = readb(&i2c_base->data); -#else - *value = readw(&i2c_base->data); -#endif - writew(I2C_STAT_RRDY, &i2c_base->stat); - } - if (status & I2C_STAT_ARDY) { - writew(I2C_STAT_ARDY, &i2c_base->stat); - break; - } - } - -read_exit: - flush_fifo(); - writew(0xFFFF, &i2c_base->stat); - writew(0, &i2c_base->cnt); - return i2c_error; } static void flush_fifo(void) @@ -241,32 +156,43 @@ static void flush_fifo(void) int i2c_probe(uchar chip) { - u16 status; + u32 status; int res = 1; /* default = fail */ if (chip == readw(&i2c_base->oa)) return res; /* wait until bus not busy */ - wait_for_bb(); + status = wait_for_bb(); + /* exit on BUS busy */ + if (status & I2C_TIMEOUT) + return res; /* try to write one byte */ writew(1, &i2c_base->cnt); /* set slave address */ writew(chip, &i2c_base->sa); /* stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); - - status = wait_for_pin(); - - /* check for ACK (!NAK) */ - if (!(status & I2C_STAT_NACK)) - res = 0; - - /* abort transfer (force idle state) */ - writew(0, &i2c_base->con); - + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT + | I2C_CON_STP, &i2c_base->con); + /* enough delay for the NACK bit set */ + udelay(50000); + + if (!(readw(&i2c_base->stat) & I2C_STAT_NACK)) { + res = 0; /* success case */ + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + } else { + /* failure, clear sources*/ + writew(0xFFFF, &i2c_base->stat); + /* finish up xfer */ + writew(readw(&i2c_base->con) | I2C_CON_STP, &i2c_base->con); + udelay(20000); + status = wait_for_bb(); + /* exit on BUS busy */ + if (status & I2C_TIMEOUT) + return res; + } flush_fifo(); /* don't allow any more data in... we don't want it. */ writew(0, &i2c_base->cnt); @@ -276,143 +202,348 @@ int i2c_probe(uchar chip) int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - int i; - if (alen > 1) { - printf("I2C read: addr len %d not supported\n", alen); + int i2c_error = 0, i; + u32 status; + + if ((alen > 2) || (alen < 0)) { return 1; } - if (addr + len > 256) { - printf("I2C read: address out of range\n"); + if (alen < 2) { + if (addr + len > 256) { + return 1; + } + } else if (addr + len > 0xFFFF) { return 1; } - for (i = 0; i < len; i++) { - if (i2c_read_byte(chip, addr + i, &buffer[i])) { - printf("I2C read: I/O error\n"); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; + /* wait until bus not busy */ + status = wait_for_bb(); + + /* exit on BUS busy */ + if (status & I2C_TIMEOUT) + return 1; + + writew((alen & 0xFF), &i2c_base->cnt); + /* set slave address */ + writew(chip, &i2c_base->sa); + /* Clear the Tx & Rx FIFOs */ + writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | + I2C_TXFIFO_CLEAR), &i2c_base->buf); + /* no stop bit needed here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | + I2C_CON_STT, &i2c_base->con); + + /* wait for Transmit ready condition */ + status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) + i2c_error = 1; + + if (!i2c_error) { + if (status & I2C_STAT_XRDY) { + switch (alen) { + case 2: + /* Send address MSByte */ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + writew(((addr >> 8) & 0xFF), &i2c_base->data); + + /* Clearing XRDY event */ + writew((status & I2C_STAT_XRDY), + &i2c_base->stat); + /* wait for Transmit ready condition */ + status = wait_for_status_mask(I2C_STAT_XRDY | + I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | + I2C_TIMEOUT)) { + i2c_error = 1; + break; + } +#endif + case 1: +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* Send address LSByte */ + writew((addr & 0xFF), &i2c_base->data); +#else + /* Send address Short word */ + writew((addr & 0xFFFF), &i2c_base->data); +#endif + /* Clearing XRDY event */ + writew((status & I2C_STAT_XRDY), + &i2c_base->stat); + /*wait for Transmit ready condition */ + status = wait_for_status_mask(I2C_STAT_ARDY | + I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | + I2C_TIMEOUT)) { + i2c_error = 1; + break; + } + } + } else + i2c_error = 1; + } + + /* Wait for ARDY to set */ + status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK + | I2C_STAT_AL); + + if (!i2c_error) { + /* set slave address */ + writew(chip, &i2c_base->sa); + writew((len & 0xFF), &i2c_base->cnt); + /* Clear the Tx & Rx FIFOs */ + writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | + I2C_TXFIFO_CLEAR), &i2c_base->buf); + /* need stop bit here */ + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + &i2c_base->con); + + for (i = 0; i < len; i++) { + /* wait for Receive condition */ + status = wait_for_status_mask(I2C_STAT_RRDY | + I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) { + i2c_error = 1; + break; + } + + if (status & I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + buffer[i] = readb(&i2c_base->data); +#else + *((u16 *)&buffer[i]) = + readw(&i2c_base->data) & 0xFFFF; + i++; +#endif + writew((status & I2C_STAT_RRDY), + &i2c_base->stat); + udelay(1000); + } else { + i2c_error = 1; + } + } + } + /* Wait for ARDY to set */ + status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK + | I2C_STAT_AL); + + if (i2c_error) { + writew(0, &i2c_base->con); + return 1; + } + + if (!i2c_error) { + writew(I2C_CON_EN, &i2c_base->con); + + while (readw(&i2c_base->stat) + || (readw(&i2c_base->con) & I2C_CON_MST)) { + udelay(10000); + writew(0xFFFF, &i2c_base->stat); } } + writew(I2C_CON_EN, &i2c_base->con); + flush_fifo(); + writew(0xFFFF, &i2c_base->stat); + writew(0, &i2c_base->cnt); + return 0; } int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { - int i; - u16 status; - int i2c_error = 0; + int i, i2c_error = 0; + u32 status; + u16 writelen; - if (alen > 1) { - printf("I2C write: addr len %d not supported\n", alen); + if (alen > 2) { return 1; } - if (addr + len > 256) { - printf("I2C write: address 0x%x + 0x%x out of range\n", - addr, len); + if (alen < 2) { + if (addr + len > 256) { + return 1; + } + } else if (addr + len > 0xFFFF) { return 1; } /* wait until bus not busy */ - wait_for_bb(); + status = wait_for_bb(); + + /* exiting on BUS busy */ + if (status & I2C_TIMEOUT) + return 1; + + writelen = (len & 0xFFFF) + alen; + + /* two bytes */ + writew((writelen & 0xFFFF), &i2c_base->cnt); + /* Clear the Tx & Rx FIFOs */ + writew((readw(&i2c_base->buf) | I2C_RXFIFO_CLEAR | + I2C_TXFIFO_CLEAR), &i2c_base->buf); - /* start address phase - will write regoffset + len bytes data */ - /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ - writew(alen + len, &i2c_base->cnt); /* set slave address */ writew(chip, &i2c_base->sa); /* stop bit needed here */ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - /* Send address byte */ - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { + /* wait for Transmit ready condition */ + status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) i2c_error = 1; - printf("error waiting for i2c address ACK (status=0x%x)\n", - status); - goto write_exit; + + if (!i2c_error) { + if (status & I2C_STAT_XRDY) { + switch (alen) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + case 2: + /* send out MSB byte */ + writeb(((addr >> 8) & 0xFF), &i2c_base->data); +#else + writeb((addr & 0xFFFF), &i2c_base->data); + break; +#endif + /* Clearing XRDY event */ + writew((status & I2C_STAT_XRDY), + &i2c_base->stat); + /*waiting for Transmit ready * condition */ + status = wait_for_status_mask(I2C_STAT_XRDY | + I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) { + i2c_error = 1; + break; + } + case 1: +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* send out MSB byte */ + writeb((addr & 0xFF), &i2c_base->data); +#else + writew(((buffer[0] << 8) | (addr & 0xFF)), + &i2c_base->data); +#endif + } + + /* Clearing XRDY event */ + writew((status & I2C_STAT_XRDY), &i2c_base->stat); + } + + /* waiting for Transmit ready condition */ + status = wait_for_status_mask(I2C_STAT_XRDY | I2C_STAT_NACK); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) + i2c_error = 1; + + if (!i2c_error) { + for (i = ((alen > 1) ? 0 : 1); i < len; i++) { + if (status & I2C_STAT_XRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + writeb((buffer[i] & 0xFF), + &i2c_base->data); +#else + writew((((buffer[i] << 8) | + buffer[i + 1]) & 0xFFFF), + &i2c_base->data); + i++; +#endif + } else + i2c_error = 1; + /* Clearing XRDY event */ + writew((status & I2C_STAT_XRDY), + &i2c_base->stat); + /* waiting for XRDY condition */ + status = wait_for_status_mask( + I2C_STAT_XRDY | + I2C_STAT_ARDY | + I2C_STAT_NACK); + if (status & (I2C_STAT_NACK | + I2C_TIMEOUT)) { + i2c_error = 1; + break; + } + if (status & I2C_STAT_ARDY) + break; + } + } } - if (status & I2C_STAT_XRDY) { - writeb(addr & 0xFF, &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); - } else { + status = wait_for_status_mask(I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL); + + if (status & (I2C_STAT_NACK | I2C_TIMEOUT)) i2c_error = 1; - printf("i2c bus not ready for transmit (status=0x%x)\n", - status); - goto write_exit; + + if (i2c_error) { + writew(0, &i2c_base->con); + return 1; } - /* address phase is over, now write data */ - for (i = 0; i < len; i++) { - status = wait_for_pin(); - if (status == 0 || status & I2C_STAT_NACK) { - i2c_error = 1; - printf("i2c error waiting for data ACK (status=0x%x)\n", - status); - goto write_exit; - } + if (!i2c_error) { + int eout = 200; - if (status & I2C_STAT_XRDY) { - writeb(buffer[i], &i2c_base->data); - writew(I2C_STAT_XRDY, &i2c_base->stat); - } else { - i2c_error = 1; - printf("i2c bus not ready for Tx (i=%d)\n", i); - goto write_exit; + writew(I2C_CON_EN, &i2c_base->con); + while ((status = readw(&i2c_base->stat)) || + (readw(&i2c_base->con) & I2C_CON_MST)) { + udelay(1000); + /* have to read to clear intrrupt */ + writew(0xFFFF, &i2c_base->stat); + if (--eout == 0) + /* better leave with error than hang */ + break; } } -write_exit: flush_fifo(); writew(0xFFFF, &i2c_base->stat); - return i2c_error; + writew(0, &i2c_base->cnt); + return 0; } -static void wait_for_bb(void) +static u32 wait_for_bb(void) { - int timeout = I2C_TIMEOUT; - u16 stat; + int timeout = I2C_STAT_TIMEO; + u32 stat; - writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { writew(stat, &i2c_base->stat); - udelay(1000); + udelay(50000); } if (timeout <= 0) { printf("timed out in wait_for_bb: I2C_STAT=%x\n", readw(&i2c_base->stat)); + stat |= I2C_TIMEOUT; } writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ + return stat; } -static u16 wait_for_pin(void) +static u32 wait_for_status_mask(u16 mask) { - u16 status; - int timeout = I2C_TIMEOUT; + u32 status; + int timeout = I2C_STAT_TIMEO; do { udelay(1000); status = readw(&i2c_base->stat); - } while (!(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); + } while (!(status & mask) && timeout--); if (timeout <= 0) { printf("timed out in wait_for_pin: I2C_STAT=%x\n", readw(&i2c_base->stat)); writew(0xFFFF, &i2c_base->stat); - status = 0; + status |= I2C_TIMEOUT; } - return status; } diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h index 1f38c23..9a0b126 100644 --- a/drivers/i2c/omap24xx_i2c.h +++ b/drivers/i2c/omap24xx_i2c.h @@ -60,7 +60,9 @@ /* I2C Buffer Configuration Register (I2C_BUF): */ #define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_RXFIFO_CLEAR (1 << 14) /* RX FIFO Clear */ #define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ +#define I2C_TXFIFO_CLEAR (1 << 6) /* TX FIFO clear */ /* I2C Configuration Register (I2C_CON): */ -- 1.7.1

2 2

[U-Boot] Uboot for PowerPC MPC8313
by Ankur Singh 17 Jan '12

17 Jan '12

Hi, We are developing application at PowerPC MPC8313E. For testing of peripherals at power on of the device, we are using U-boot Version – 1.1.6). This is an old project and we are only upgrading few of the functionalities. The reason I have contacted you is, I’m trying to test UART3 (it’s a memory mapped IO, driven from a eLBC module via chip selection and all). Somehow I’m not able to test from the u-boot how to test this memory mapped IO. I’m looking to transmit and receive few character to HyperTerminal and conclude whether its working or not? My questions are 1. Is it possible to test this UART (memory mapped IO) in such a manner? 2. If yes, can u guide me how to test with some reference code or something? We have been struck here for a week and tried everything but I think somewhere I’m lacking proper guidance (1st time I’m developing something on Linux and powerPC) Thanks for any suggestion.. Regards, Ankur Singh Larsen & Toubro Limited www.larsentoubro.com This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system.

1 0

[U-Boot] [PATCH 1/2] nand: Introduce CONFIG_SYS_NAND_SELF_INIT
by Scott Wood 16 Jan '12

16 Jan '12

This allows a driver to run code between nand_scan_ident() and nand_scan_tail(), among other things. See the additions to doc/README.nand for details. To allow a gradual transition, Boards that don't set CONFIG_SYS_NAND_SELF_INIT will still be initialized the old way, but new drivers should not require this, and existing drivers should be converted when convenient. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- doc/README.nand | 62 ++++++++++++++++++++++++++++++ drivers/mtd/nand/nand.c | 96 +++++++++++++++++++++++++++++------------------ include/nand.h | 5 ++ 3 files changed, 126 insertions(+), 37 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 023740e..04a87c9 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -120,6 +120,68 @@ Configuration Options: CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. + CONFIG_SYS_NAND_SELF_INIT + Traditionally, glue code in drivers/mtd/nand/nand.c has driven + the initialization process -- it provides the mtd and nand + structs, calls a board init function for a specific device, + calls nand_scan(), and registers with mtd. + + This arrangement does not provide drivers with the flexibility to + run code between nand_scan_ident() and nand_scan_tail(), or other + deviations from the "normal" flow. + + If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c + will make one call to board_nand_init(), with no arguments. That + function is responsible for calling a driver init function for + each NAND device on the board, that performs all initialization + tasks except setting mtd->name, and registering with the rest of + U-Boot. Those last tasks are accomplished by calling nand_register() + on the new mtd device. + + Example of new init to be added to the end of an existing driver + init: + + /* + * devnum is the device number to be used in nand commands + * and in mtd->name. Must be less than + * CONFIG_SYS_NAND_MAX_DEVICE. + */ + mtd = &nand_info[devnum]; + + /* chip is struct nand_chip, and is now provided by the driver. */ + mtd->priv = &chip; + + /* + * Fill in appropriate values if this driver uses these fields, + * or uses the standard read_byte/write_buf/etc. functions from + * nand_base.c that use these fields. + */ + chip.IO_ADDR_R = ...; + chip.IO_ADDR_W = ...; + + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) + error out + + /* + * Insert here any code you wish to run after the chip has been + * identified, but before any other I/O is done. + */ + + if (nand_scan_tail(mtd)) + error out + + if (nand_register(devnum)) + error out + + In addition to providing more flexibility to the driver, it reduces + the difference between a U-Boot driver and its Linux counterpart. + nand_init() is now reduced to calling board_nand_init() once, and + printing a size summary. This should also make it easier to + transition to delayed NAND initialization. + + Please convert your driver even if you don't need the extra + flexibility, so that one day we can eliminate the old mechanism. + NOTE: ===== diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index d987f4c..4cf4c1c 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -23,6 +23,7 @@ #include <common.h> #include <nand.h> +#include <errno.h> #ifndef CONFIG_SYS_NAND_BASE_LIST #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } @@ -31,63 +32,84 @@ DECLARE_GLOBAL_DATA_PTR; int nand_curr_device = -1; + + nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; +#ifndef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +#endif + +static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8]; + +static unsigned long total_nand_size; /* in kiB */ + +/* Register an initialized NAND mtd device with the U-Boot NAND command. */ +int nand_register(int devnum) +{ + struct mtd_info *mtd; + + if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE) + return -EINVAL; + + mtd = &nand_info[devnum]; + + sprintf(dev_name[devnum], "nand%d", devnum); + mtd->name = dev_name[devnum]; + +#ifdef CONFIG_MTD_DEVICE + /* + * Add MTD device so that we can reference it later + * via the mtdcore infrastructure (e.g. ubi). + */ + add_mtd_device(mtd); +#endif + + total_nand_size += mtd->size / 1024; -static const char default_nand_name[] = "nand"; -static __attribute__((unused)) char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8]; + if (nand_curr_device == -1) + nand_curr_device = devnum; + + return 0; +} -static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, - ulong base_addr) +#ifndef CONFIG_SYS_NAND_SELF_INIT +static void nand_init_chip(int i) { + struct mtd_info *mtd = &nand_info[i]; + struct nand_chip *nand = &nand_chip[i]; + ulong base_addr = base_address[i]; int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; - static int __attribute__((unused)) i = 0; if (maxchips < 1) maxchips = 1; - mtd->priv = nand; + mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; - if (board_nand_init(nand) == 0) { - if (nand_scan(mtd, maxchips) == 0) { - if (!mtd->name) - mtd->name = (char *)default_nand_name; -#ifdef CONFIG_NEEDS_MANUAL_RELOC - else - mtd->name += gd->reloc_off; -#endif -#ifdef CONFIG_MTD_DEVICE - /* - * Add MTD device so that we can reference it later - * via the mtdcore infrastructure (e.g. ubi). - */ - sprintf(dev_name[i], "nand%d", i); - mtd->name = dev_name[i++]; - add_mtd_device(mtd); -#endif - } else - mtd->name = NULL; - } else { - mtd->name = NULL; - mtd->size = 0; - } + if (board_nand_init(nand)) + return; + if (nand_scan(mtd, maxchips)) + return; + + nand_register(i); } +#endif void nand_init(void) { +#ifdef CONFIG_SYS_NAND_SELF_INIT + board_nand_init(); +#else int i; - unsigned int size = 0; - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) { - nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); - size += nand_info[i].size / 1024; - if (nand_curr_device == -1) - nand_curr_device = i; - } - printf("%u MiB\n", size / 1024); + + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_init_chip(i); +#endif + + printf("%lu MiB\n", total_nand_size / 1024); #ifdef CONFIG_SYS_NAND_SELECT_DEVICE /* diff --git a/include/nand.h b/include/nand.h index d444ddc..5dd1710 100644 --- a/include/nand.h +++ b/include/nand.h @@ -30,7 +30,12 @@ extern void nand_init(void); #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> +#ifdef CONFIG_SYS_NAND_SELF_INIT +void board_nand_init(void); +int nand_register(int devnum); +#else extern int board_nand_init(struct nand_chip *nand); +#endif typedef struct mtd_info nand_info_t; -- 1.7.7.rc3.4.g8d714

2 7

[U-Boot] [RESEND PATCH v3 0/6] Introduce generic relocation feature
by Simon Glass 16 Jan '12

16 Jan '12

(I have updated this cover letter slightly and rebased to master. This series has trivial conflicts with the generic board series in the arch/xxx/config.mk additions and also in that they both add include/linux/sections.h. I original had this series first in my list, but the generic board series now also applies directly to master, so I will leave this one as is until I know what ordering is required). This is the second patch series aiming to unify the various board.c files in each architecture into a single one. This series implements a generic relocation feature, which is the bridge between board_init_f() and board_init_r(). It then moves ARM over to use this framework, as an example. On ARM the relocation code is duplicated for each CPU yet it is the same. We can bring this up to the arch level. But since (I believe) Elf relocation is basically the same process for all archs, there is no reason not to bring it up to the generic level. Each architecture which uses this framework needs to provide a function called arch_elf_relocate_entry() which processes a single relocation entry. This is a static inline function to reduce code size overhead. For ARM, a new arch/arm/lib/proc.S file is created, which holds generic ARM assembler code (things that cannot be written in C and are common functions used by all ARM CPUs). This helps reduce duplication. Interrupt handling code and perhaps even some startup code can move there later. It may be useful for other architectures with a lot of different CPUs to have a similar file. Code size on my ARMv7 system increases by 54 bytes with generic relocation. This overhead is mostly just literal pool access and setting up to call the relocated U-Boot at the end. On my system, execution time increases from 10.8ms to 15.6ms due to the less efficient C implementations of the copy and zero loops. If execution time is of concern, you can define CONFIG_USE_ARCH_MEMSET and CONFIG_USE_ARCH_MEMCPY to reduce it. For met this reduces relocation time to 5.4ms, i.e. twice as fast as the old system. One problem remains which causes tx25 to fail to build. It doesn't have string.c in its SPL code and the architecture-specific versions of memset()/memcpy() are too large. I propose to add a local change to reloc.c that uses inline code for boards that use the old legacy SPL framework. We can remove it later. This is not included in v4 but I am interested in comments on this approach. An alternative would be just to add simple memset()/memcpy() functions just for this board. Changes in v2: - Add README file for relocation - Add function comments - Import asm-generic/sections.h from Linux and add U-Boot extras - Invalidate I-cache when we jump to relocated code - Make relocation symbols global so we can use them outside start.S - Move reloc.c into common/ - Squash generic link symbols patch into generic relocation patch - Use CONFIG_SYS_SKIP_RELOC instead of CONFIG_SYS_LEGACY_BOARD - Use an inline relocation function to reduce code size - Use memset, memcpy instead of inline code Changes in v3: - Rebase to master - Remove the 'reloc' tag from each commit Simon Glass (6): Create reloc.h and include it where needed define CONFIG_SYS_SKIP_RELOC for all archs Add generic relocation feature arm: Add processor function library arm: Move over to generic relocation arm: Remove unused code in start.S README | 4 + arch/arm/cpu/arm1136/start.S | 133 ++------------ arch/arm/cpu/arm1176/start.S | 214 ++------------------- arch/arm/cpu/arm720t/start.S | 127 ++----------- arch/arm/cpu/arm920t/start.S | 135 ++------------ arch/arm/cpu/arm925t/start.S | 135 ++------------ arch/arm/cpu/arm926ejs/davinci/spl.c | 1 + arch/arm/cpu/arm926ejs/start.S | 144 ++------------- arch/arm/cpu/arm946es/start.S | 130 ++----------- arch/arm/cpu/arm_intcm/start.S | 135 ++------------ arch/arm/cpu/armv7/omap-common/spl.c | 1 + arch/arm/cpu/armv7/start.S | 140 ++------------ arch/arm/cpu/ixp/start.S | 127 ++----------- arch/arm/cpu/lh7a40x/start.S | 124 ++----------- arch/arm/cpu/pxa/start.S | 138 ++------------ arch/arm/cpu/s3c44b0/start.S | 127 ++----------- arch/arm/cpu/sa1100/start.S | 124 ++----------- arch/arm/include/asm/reloc.h | 56 ++++++ arch/arm/lib/Makefile | 2 + arch/arm/lib/board.c | 1 + arch/arm/lib/proc.S | 40 ++++ arch/avr32/config.mk | 3 + arch/avr32/lib/board.c | 1 + arch/blackfin/config.mk | 3 + arch/m68k/config.mk | 3 + arch/m68k/lib/board.c | 1 + arch/microblaze/config.mk | 3 + arch/mips/config.mk | 3 + arch/mips/lib/board.c | 1 + arch/nds32/config.mk | 3 + arch/nds32/lib/board.c | 1 + arch/nios2/config.mk | 3 + arch/powerpc/config.mk | 3 + arch/powerpc/lib/board.c | 1 + arch/sandbox/config.mk | 3 + arch/sh/config.mk | 3 + arch/sparc/config.mk | 3 + arch/x86/config.mk | 3 + arch/x86/lib/board.c | 1 + board/freescale/mpc8313erdb/mpc8313erdb.c | 1 + board/freescale/mpc8315erdb/mpc8315erdb.c | 1 + board/samsung/smdk6400/smdk6400_nand_spl.c | 1 + board/sheldon/simpc8313/simpc8313.c | 1 + common/Makefile | 4 + common/reloc.c | 121 ++++++++++++ doc/README.relocation | 87 +++++++++ include/asm-generic/sections.h | 92 +++++++++ include/common.h | 2 +- include/reloc.h | 54 +++++ nand_spl/board/freescale/mpc8536ds/nand_boot.c | 1 + nand_spl/board/freescale/mpc8569mds/nand_boot.c | 1 + nand_spl/board/freescale/mpc8572ds/nand_boot.c | 1 + nand_spl/board/freescale/mx31pdk/Makefile | 8 +- nand_spl/board/freescale/mx31pdk/u-boot.lds | 1 + nand_spl/board/freescale/p1010rdb/nand_boot.c | 1 + nand_spl/board/freescale/p1023rds/nand_boot.c | 1 + nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 1 + nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 1 + nand_spl/board/karo/tx25/Makefile | 8 +- nand_spl/board/karo/tx25/u-boot.lds | 1 + nand_spl/nand_boot_fsl_nfc.c | 1 + 61 files changed, 705 insertions(+), 1765 deletions(-) create mode 100644 arch/arm/include/asm/reloc.h create mode 100644 arch/arm/lib/proc.S create mode 100644 common/reloc.c create mode 100644 doc/README.relocation create mode 100644 include/asm-generic/sections.h create mode 100644 include/reloc.h -- 1.7.7.3

1 6

Re: [U-Boot] [GIT PULL] please pull u-boot-mpc85xx
by Tabi Timur-B04825 16 Jan '12

16 Jan '12

On Thu, Jan 12, 2012 at 5:49 PM, Tabi Timur-B04825 <b04825(a)freescale.com> wrote: > Are you going to make another pull request before the window closes? The reason I ask is that you're missing some of my patches. http://patchwork.ozlabs.org/project/uboot/list/?submitter=timur -- Timur Tabi Linux kernel developer at Freescale

2 1

[U-Boot] [PATCH 1/2] SPI: Add i.MX ECSPI driver
by Dirk Behme 16 Jan '12

16 Jan '12

From: Eric Nelson <eric.nelson(a)boundarydevices.com> Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> CC: Jason Liu <jason.hui(a)linaro.org> CC: Stefano Babic <sbabic(a)denx.de> --- drivers/spi/Makefile | 1 + drivers/spi/imx_ecspi.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++ include/imx_spi.h | 97 ++++++++++++++ 3 files changed, 432 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/imx_ecspi.c create mode 100644 include/imx_spi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c967d87..e27ef41 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +COBJS-$(CONFIG_IMX_ECSPI) += imx_ecspi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/imx_ecspi.c b/drivers/spi/imx_ecspi.c new file mode 100644 index 0000000..1468208 --- /dev/null +++ b/drivers/spi/imx_ecspi.c @@ -0,0 +1,334 @@ +/* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <spi.h> +#include <asm/errno.h> +#include <linux/types.h> +#include <asm/io.h> +#include <malloc.h> +#include <asm/arch/clock.h> +#include <imx_spi.h> + +static inline struct imx_spi_dev_t *to_imx_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct imx_spi_dev_t, slave); +} + +static s32 spi_reset(struct spi_slave *slave) +{ + u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); + u32 pre_div = 0, post_div = 0, reg_ctrl, reg_config; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *reg = &(dev->reg); + + if (dev->freq == 0) { + printf("Error: desired clock is 0\n"); + return 1; + } + + reg_ctrl = readl(dev->base + SPI_CON_REG); + reg_config = readl(dev->base + SPI_CFG_REG); + /* Reset spi */ + writel(0, dev->base + SPI_CON_REG); + writel((reg_ctrl | 0x1), dev->base + SPI_CON_REG); + + /* Control register setup */ + pre_div = (clk_src + dev->freq - 1) / dev->freq; + while (pre_div > 16) { + pre_div = (pre_div + 1) >> 1; + post_div++; + } + if (post_div > 0x0f) { + printf("Error: no divider can meet the freq: %d\n", dev->freq); + return -1; + } + if (pre_div) + pre_div--; + + debug("pre_div = %d, post_div=%d, clk_src=%d, spi_freq=%d\n", pre_div, + post_div, clk_src, (clk_src/(pre_div + 1)) >> post_div); + reg_ctrl &= ~((3 << 18) | (0xF << 12) | (0xF << 8)); + reg_ctrl |= (dev->ss << 18); + reg_ctrl |= (pre_div << 12); + reg_ctrl |= (post_div << 8); + reg_ctrl |= (1 << (dev->ss + 4)); /* always set to master mode */ + reg_ctrl |= 1; + + /* configuration register setup */ + reg_config &= ~(0x111111 << dev->ss); + reg_config |= (dev->in_sctl << (dev->ss + 20)); + reg_config |= (dev->in_dctl << (dev->ss + 16)); + reg_config |= (dev->ss_pol << (dev->ss + 12)); + reg_config |= (dev->ssctl << (dev->ss + 8)); + reg_config |= (dev->sclkpol << (dev->ss + 4)); + reg_config |= (dev->sclkpha << (dev->ss)); + + reg_config &= 0x0f << 12 ; + reg_config |= (dev->ss_pol)<<(12+dev->ss); + debug("ss%x, reg_config = 0x%x\n", dev->ss, reg_config); + writel(reg_config, dev->base + SPI_CFG_REG); + debug("ss%x, reg_ctrl = 0x%x\n", dev->ss, reg_ctrl); + writel(reg_ctrl & ~1, dev->base + SPI_CON_REG); + + /* save config register and control register */ + reg->cfg_reg = reg_config; + reg->ctrl_reg = reg_ctrl; + + /* clear interrupt reg */ + writel(0, dev->base + SPI_INT_REG); + writel(3 << 6, dev->base + SPI_STAT_REG); + return 0; +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct imx_spi_dev_t *imx_spi_slave = NULL; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + imx_spi_slave = (struct imx_spi_dev_t *) + calloc(sizeof(struct imx_spi_dev_t), 1); + if (!imx_spi_slave) + return NULL; + + imx_spi_slave->slave.bus = bus; + imx_spi_slave->slave.cs = cs; + + spi_get_cfg(imx_spi_slave); + + if (max_hz < imx_spi_slave->freq) + imx_spi_slave->freq = max_hz ; + spi_io_init(imx_spi_slave, 0); + + spi_reset(&(imx_spi_slave->slave)); + + return &(imx_spi_slave->slave); +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct imx_spi_dev_t *imx_spi_slave; + + if (slave) { + imx_spi_slave = to_imx_spi_slave(slave); + free(imx_spi_slave); + } +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +/* + * SPI xchg + */ + +int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) +{ + int nbytes = (bitlen + 7) / 8; + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + struct spi_reg_t *spi_reg = &(dev->reg); + u32 loop_cnt ; + if (!slave) + return -1; + + if (spi_reg->ctrl_reg == 0) { + printf("Error: spi(base=0x%x) has not been initialized yet\n", + dev->base); + return -1; + } + spi_reg->ctrl_reg = (spi_reg->ctrl_reg & ~0xFFF00000) | \ + ((bitlen - 1) << 20); + + writel(spi_reg->ctrl_reg, dev->base + SPI_CON_REG); + writel(spi_reg->cfg_reg, dev->base + SPI_CFG_REG); + + /* move data to the tx fifo */ + debug("dout=0x%p, bitlen=%x\n", dout, bitlen); + + /* + * The SPI controller works only with words, + * check if less than a word is sent. + * Access to the FIFO is only 32 bit + */ + if (bitlen % 32) { + u32 data = 0; + u32 cnt = (bitlen % 32) / 8; + if (dout) { + int i ; + for (i = 0; i < cnt; i++) + data = (data << 8) | (*dout++ & 0xFF); + } + debug("Sending SPI 0x%x\n", data); + + writel(data, dev->base + SPI_TX_DATA); + nbytes -= cnt; + } + + while (nbytes > 0) { + u32 data = 0; + if (dout) { + /* Buffer is not 32-bit aligned */ + if ((unsigned long)dout & 0x03) { + int i ; + data = 0; + for (i = 0; i < 4; i++) + data = (data << 8) | (*dout++ & 0xFF); + } else { + data = *(u32 *)dout; + data = cpu_to_be32(data); + } + dout += 4; + } + debug("Sending SPI 0x%x\n", data); + writel(data, dev->base + SPI_TX_DATA); + nbytes -= 4; + } + + writel(spi_reg->ctrl_reg | (1 << 2), dev->base + SPI_CON_REG); + + loop_cnt = SPI_RETRY_TIMES ; + /* poll on the TC bit (transfer complete) */ + while ((readl(dev->base + SPI_STAT_REG) & (1 << 7)) == 0) { + loop_cnt--; + if (loop_cnt <= 0) { + printf("%s: Error: re-tried %d times\n", + __func__, SPI_RETRY_TIMES); + bitlen = 0 ; + spi_cs_deactivate(slave); + return -1; + } + udelay(100); + } + + /* clear the TC bit */ + writel(3 << 6, dev->base + SPI_STAT_REG); + + nbytes = (bitlen + 7) / 8; + + if (bitlen % 32) { + u32 data = readl(dev->base + SPI_RX_DATA); + u32 cnt = (bitlen % 32) / 8; + data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8); + debug("SPI Rx unaligned: 0x%x\n", data); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + while (nbytes > 0) { + u32 tmp = readl(dev->base + SPI_RX_DATA); + u32 data = cpu_to_be32(tmp); + u32 cnt = min(nbytes, sizeof(data)); + debug("SPI Rx: 0x%x 0x%x\n", tmp, data); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + return 0; +} + +/* + * SPI transfer: + * + * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf + * for more informations. + */ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + int n_bytes = (bitlen + 7) / 8; + int n_bits; + int ret; + u32 blk_size; + u8 *p_outbuf = (u8 *)dout; + u8 *p_inbuf = (u8 *)din; + + if (!slave) + return -1; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (n_bytes > 0) { + if (n_bytes < MAX_SPI_BYTES) + blk_size = n_bytes; + else + blk_size = MAX_SPI_BYTES; + + n_bits = blk_size * 8; + + ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); + + if (ret) + return ret; + if (dout) + p_outbuf += blk_size; + if (din) + p_inbuf += blk_size; + n_bytes -= blk_size; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + + spi_io_init(dev, 1); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct imx_spi_dev_t *dev = to_imx_spi_slave(slave); + spi_io_init(dev, 0); + writel(0, dev->base + SPI_CON_REG); +} diff --git a/include/imx_spi.h b/include/imx_spi.h new file mode 100644 index 0000000..32544d9 --- /dev/null +++ b/include/imx_spi.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMX_SPI_H__ +#define __IMX_SPI_H__ + +#include <spi.h> + +#undef IMX_SPI_DEBUG + +#define IMX_SPI_ACTIVE_HIGH 1 +#define IMX_SPI_ACTIVE_LOW 0 +#define SPI_RETRY_TIMES 100 + +#if defined(IMX_CSPI_VER_0_7) + #define SPI_RX_DATA 0x0 + #define SPI_TX_DATA 0x4 + #define SPI_CON_REG 0x8 + #define SPI_INT_REG 0xC + #define SPI_DMA_REG 0x10 + #define SPI_STAT_REG 0x14 + #define SPI_PERIOD_REG 0x18 + + #define SPI_CTRL_EN (1 << 0) + #define SPI_CTRL_MODE (1 << 1) + #define SPI_CTRL_REG_XCH_BIT (1 << 2) + #define SPI_CTRL_SSPOL (1 << 7) + #define SPI_CTRL_SSPOL_OFF (7) + #define SPI_CTRL_SSCTL (1 << 6) + #define SPI_CTRL_SSCTL_OFF (6) + #define SPI_CTRL_SCLK_POL (1 << 4) + #define SPI_CTRL_SCLK_POL_OFF (4) + #define SPI_CTRL_SCLK_PHA (1 << 5) + #define SPI_CTRL_SCLK_PHA_OFF (5) + #define SPI_CTRL_SS_OFF (12) + #define SPI_CTRL_SS_MASK (3 << 12) + #define SPI_CTRL_DATA_OFF (16) + #define SPI_CTRL_DATA_MASK (7 << 16) + #define SPI_CTRL_BURST_OFF (20) + #define SPI_CTRL_BURST_MASK (0xFFF << 20) + #define SPI_INT_STAT_TC (1 << 7) + +#elif defined(IMX_CSPI_VER_2_3) + #define SPI_RX_DATA 0x0 + #define SPI_TX_DATA 0x4 + #define SPI_CON_REG 0x8 + #define SPI_CFG_REG 0xC + #define SPI_INT_REG 0x10 + #define SPI_DMA_REG 0x14 + #define SPI_STAT_REG 0x18 + #define SPI_PERIOD_REG 0x1C +#endif + +struct spi_reg_t { + u32 ctrl_reg; + u32 cfg_reg; +}; + +struct imx_spi_dev_t { + struct spi_slave slave; + u32 base; /* base address of SPI module */ + u32 freq; /* desired clock freq in Hz for this device */ + u32 ss_pol; /* ss polarity: 1=active high; 0=active low */ + u32 ss; /* slave select */ + u32 in_sctl; /* inactive sclk ctl: 1=stay low; 0=stay high */ + u32 in_dctl; /* inactive data ctl: 1=stay low; 0=stay high */ + u32 ssctl; /* single burst mode vs multiple: 0=single; 1=multi */ + u32 sclkpol; /* sclk polarity: active high=0; active low=1 */ + u32 sclkpha; /* sclk phase: 0=phase 0; 1=phase1 */ + u32 fifo_sz; /* fifo size in bytes for either tx or rx. */ + u32 us_delay; /* us delay in each xfer */ + struct spi_reg_t reg; /* pointer to a set of SPI registers */ +}; + +extern void spi_io_init(struct imx_spi_dev_t *dev, int active); +extern s32 spi_get_cfg(struct imx_spi_dev_t *dev); + +#endif /* __IMX_SPI_H__ */ -- 1.7.0.4

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Re: [U-Boot] OMAP3 performance regression in 2011.12
by Joe Woodward 16 Jan '12

16 Jan '12

-----Original Message----- From: Philip Balister <philip(a)balister.org> To: Joe Woodward <jw(a)terrafix.co.uk> Date: Fri, 13 Jan 2012 15:53:37 -0500 Subject: Re: OMAP3 performance regression in 2011.12 > Did you find out anymore info on this? I may have a customer who is > seeing this on a 3.o based overo. > (CC'ing in the mailing list again). Sadly not, no more replies to this. I think either this change needs reverting (but that'll break OMAP4) or at least encasing in #ifdefs so that it isn't applied for OMAP3. I was going to ask on the Linux OMAP mailing list if the L2/outer cache is enabled on OMAP3 in Linux but haven't got round to it yet! Cheers, Joe > Philip > > On 01/09/2012 10:48 AM, Joe Woodward wrote: > >> -----Original Message----- > >> From: Tom Rini <tom.rini(a)gmail.com> > >> To: Joe Woodward <jw(a)terrafix.co.uk> > >> Cc: u-boot(a)lists.denx.de > >> Date: Mon, 9 Jan 2012 08:11:07 -0700 > >> Subject: Re: [U-Boot] OMAP3 performance regression in 2011.12 > >> > >>> On Mon, Jan 9, 2012 at 3:27 AM, Joe Woodward <jw(a)terrafix.co.uk> > >> wrote: > >>>> Commit "armv7: disable L2 cache in cleanup_before_linux()" on 6th > >> Dec > >>> 2011 by Aneesh V adds the following: > >>>> > >>>> arch/arm/cpu/armv7/cpu.c:cleanup_before_linux() > >>>> > >>>> ... > >>>> v7_out_cache_disable(); > >>>> ... > >>>> > >>>> The commit message implies this change was to make booting > reliable > >>> on OMAP4 by disabling L2 cache before jumping to Linux. > >>>> > >>>> However, when running with a stock 3.2 Linux kernel on an OMAP3 it > >>> has the effect of massively reducing system performance (when > running > >>> using an OMAP3- > >>>> only 3.2 Linux Kernel on a GUSMTIX Overo OMAP3530). > >>>> > >>>> Therefore, I assume this means that the kernel isn't turning the > L2 > >>> cache back on for an OMAP3 (at least with my kernel build)! > >>>> > >>>> So, my question is... > >>>> > >>>> Are there any Kconfig options in Linux that will re-enable the L2 > >>> cache (something obvious that I've missed), or is this commit just > >>> bad-news for OMAP3? > >>> > >>> Are you certain that this is the commit that's causing your > problem? > >>> The kernel is responsible for turning the cache back on and has for > a > >>> long time, iirc. > >>> > >>> -- > >>> Tom > > > > (apologies for previous top posting, wasn't paying attention to what > I was doing!) > > > > I'm fairly certain... > > > > If I take the 2011.12 uBoot release the kernel takes about twice the > time to boot (compared to 2011.09), and the device is noticably slower. > > > > Then if I comment out the v7_out_cache_disable() line in cpu.c and > rebuild uBoot then everything speeds up again. > > > > I thought the kernel would turn on the cache again too... > > > > Is there any easy way from userspace to determine if the cache is on? > > > > I did a bit of Googling and found: > > http://www.spinics.net/lists/arm-kernel/msg50064.html > > http://www.spinics.net/lists/arm-kernel/msg50083.html > > > > It may be that the kernel is re-enabling the L1 cache, but expecting > L2 to be on? > > Or the way v7_out_cache_disable() disables L2 is not compatible with > the way the kernel expects to re-enable it? > > > > Also, in the Linux there seem to be OMAP4 specific functions for > re-enabling the L2 cache (omap4-common.c:omap_l2_cache_init()), but > none for OMAP3. I'm > > assuming this is because up to now OMAP3 is assumed to have the L2 > left enabled? Either that, or there is some generic Cortex-A8 method > for enabling the L2 > > cache in the kernel soures that I've not found... > > > > Cheers, > > Joe > > > >> > >> _______________________________________________ > >> U-Boot mailing list > >> U-Boot(a)lists.denx.de > >> http://lists.denx.de/mailman/listinfo/u-boot >

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[U-Boot] [PATCH] net/eth.c: fix eth_write_hwaddr() to use dev->enetaddr as fall back
by Eric Miao 16 Jan '12

16 Jan '12

Ignore the return value of eth_getenv_enetaddr_by_index(), and if it fails, fall back to use dev->enetaddr, which could be filled up by the ethernet device driver. Actually, this is the original behavior, and was later changed by commit 48506a2cde2458fa1f8c5993afc98e5a4617e1d3. Signed-off-by: Eric Miao <eric.miao(a)linaro.org> --- net/eth.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/net/eth.c b/net/eth.c index a34fe59..c4fbe11 100644 --- a/net/eth.c +++ b/net/eth.c @@ -195,8 +195,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, unsigned char env_enetaddr[6]; int ret = 0; - if (!eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr)) - return -1; + eth_getenv_enetaddr_by_index(base_name, eth_number, env_enetaddr); if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) && -- 1.7.4.1

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