January 2012 - U-Boot

[U-Boot] [PATCH v6 0/4] Add SMDK5250 board support
by Chander Kashyap 02 Feb '12

02 Feb '12

This patchset add support for Samsung's SMDK5250 board based on EXYNOS5250 based SoC. It also adds support for MMC SPL booting. The porting is done by Samsung engineers at HQ in System LSI Team. I am contributing in upstreaming the code for the board. Based upon discussions following patches are dropped in this version: Exynos: Add CONFIG_EXYNOS4 Macro to EXYNOS4 based boards Exynos: Clock.c: Replace exynos4 prefix with exynos SMDK5250: enable device tree support is squashed with EXYNOS: Add SMDK5250 board support Chander Kashyap (4): Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro ARM: EXYNOS: Add support for Exynos5 based SoCs EXYNOS: Add SMDK5250 board support EXYNOS: SMDK5250: Add MMC SPL support MAINTAINERS | 1 + arch/arm/cpu/armv7/exynos/clock.c | 214 ++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 326 ++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 35 ++- arch/arm/include/asm/arch-exynos/dmc.h | 146 +++++++ arch/arm/include/asm/arch-exynos/gpio.h | 99 +++++- arch/arm/include/asm/arch-exynos/tzpc.h | 52 +++ board/samsung/smdk5250/Makefile | 67 ++++ board/samsung/smdk5250/clock_init.c | 202 ++++++++++ board/samsung/smdk5250/dmc_init.c | 508 +++++++++++++++++++++++++ board/samsung/smdk5250/lowlevel_init.S | 96 +++++ board/samsung/smdk5250/mmc_boot.c | 58 +++ board/samsung/smdk5250/setup.h | 353 +++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 152 ++++++++ board/samsung/smdk5250/tools/mkexynos_image.c | 117 ++++++ board/samsung/smdk5250/tzpc_init.c | 48 +++ boards.cfg | 1 + include/configs/s5pc210_universal.h | 1 + include/configs/smdk5250.h | 202 ++++++++++ include/configs/trats.h | 1 + 20 files changed, 2662 insertions(+), 17 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h create mode 100644 board/samsung/smdk5250/Makefile create mode 100644 board/samsung/smdk5250/clock_init.c create mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/lowlevel_init.S create mode 100644 board/samsung/smdk5250/mmc_boot.c create mode 100644 board/samsung/smdk5250/setup.h create mode 100644 board/samsung/smdk5250/smdk5250.c create mode 100644 board/samsung/smdk5250/tools/mkexynos_image.c create mode 100644 board/samsung/smdk5250/tzpc_init.c create mode 100644 include/configs/smdk5250.h -- 1.7.5.4

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[U-Boot] [PATCH 1/2] SPL: Add YMODEM over UART load support
by Tom Rini 01 Feb '12

01 Feb '12

From: Matt Porter <mporter(a)ti.com> Adds support for loading U-Boot from UART using YMODEM protocol. If YMODEM support is enabled in SPL and the romcode indicates that SPL loaded via UART then SPL will wait for start of a YMODEM transfer via the console port. Signed-off-by: Matt Porter <mporter(a)ti.com> Signed-off-by: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap-common/Makefile | 3 + arch/arm/cpu/armv7/omap-common/spl.c | 5 ++ arch/arm/cpu/armv7/omap-common/spl_ymodem.c | 76 +++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 3 + common/Makefile | 3 + lib/Makefile | 3 + 6 files changed, 93 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap-common/spl_ymodem.c diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 3f7a0b2..447fcd5 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -52,6 +52,9 @@ endif ifdef CONFIG_SPL_MMC_SUPPORT COBJS += spl_mmc.o endif +ifdef CONFIG_SPL_YMODEM_SUPPORT +COBJS += spl_ymodem.o +endif endif ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 9c1f7e3..9018787 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -134,6 +134,11 @@ void board_init_r(gd_t *id, ulong dummy) spl_nand_load_image(); break; #endif +#ifdef CONFIG_SPL_YMODEM_SUPPORT + case BOOT_DEVICE_UART: + spl_ymodem_load_image(); + break; +#endif default: printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device); hang(); diff --git a/arch/arm/cpu/armv7/omap-common/spl_ymodem.c b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c new file mode 100644 index 0000000..47663f7 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/spl_ymodem.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Matt Porter <mporter(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <xyzModem.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> + +#define BUF_SIZE 1024 + +static int getcymodem(void) { + if (tstc()) + return (getc()); + return -1; +} + +void spl_ymodem_load_image(void) +{ + int size = 0; + int err; + int res; + int ret; + connection_info_t info; + char buf[BUF_SIZE]; + ulong store_addr = ~0; + ulong addr = 0; + + info.mode = xyzModem_ymodem; + ret = xyzModem_stream_open(&info, &err); + + if (!ret) { + while ((res = + xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { + if (addr == 0) + spl_parse_image_header((struct image_header *)buf); + store_addr = addr + spl_image.load_addr; + size += res; + addr += res; + memcpy((char *)(store_addr), buf, res); + } + } else { + printf("spl: ymodem err - %s\n", xyzModem_error(err)); + hang(); + } + + xyzModem_stream_close(&err); + xyzModem_stream_terminate(false, &getcymodem); + + printf("Loaded %d bytes\n", size); +} diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 34bec45..25f95b4 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -99,6 +99,9 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +/* YMODEM SPL functions */ +void spl_ymodem_load_image(void); + #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif diff --git a/common/Makefile b/common/Makefile index 2d9ae8c..0189aac 100644 --- a/common/Makefile +++ b/common/Makefile @@ -184,6 +184,9 @@ COBJS-$(CONFIG_UPDATE_TFTP) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o endif +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o +endif COBJS-y += console.o COBJS-y += dlmalloc.o COBJS-y += memsize.o diff --git a/lib/Makefile b/lib/Makefile index 35ba7ff..eb60b99 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -54,6 +54,9 @@ else COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o endif +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o +endif COBJS-y += ctype.o COBJS-y += div64.o COBJS-y += string.o -- 1.7.0.4

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Re: [U-Boot] SPL Linux Boot
by Stefano Babic 01 Feb '12

01 Feb '12

On 30/01/2012 19:05, Tom Rini wrote: Hi Tom, >> OK, doing a MAKEALL for omap3/4/5/am33xx/davinci shows we've got a few >> missing include problems, I'll go fix that up. > > OK, was it when you took over the series that you moved stuff to > common/spl.c ? That idea is breaking, badly, non-omap platforms. I am trying to summarize the different problems we have. Comparing to u-boot-ti, the patchset breaks the following boards: davinci: da850_am18xxevm da850evm hawkboard_nand omap4/5: fixed including spl.h into arch/arm/cpu/armv7/omap-common/boot-common.c mx28: m28evk mx28evk I have not seen other broken boards - let me know if you find something else. On omap4/5 is only a thing of include files, as you reported. A main issue is with davinci, because we have currently two different spl.c (arch/arm/cpu/arm926ejs/davinci/spl.c on davinci). The code can be factorized, if davinci will use preloader_console_init() as omap. The same problem rises with mx28: there is a specific file arch/arm/cpu/arm926ejs/mx28/spl_boot.c, that redefines board_init_f() and board_init_r() - as we try to have a common spl code, this muist be fixed, too. A way can be to add an arch weak function to add arch specific initialization inside board_init_*() functions, if any. Have you seen other issues other what I report now ? Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] [PATCH] i.mx: i.mx5: update imx_get_mac_from_fuse function
by Jason Liu 01 Feb '12

01 Feb '12

FEC does not work on the i.mx51/53evk board, it will hangup In: serial Out: serial Err: serial Net: After bisect, it due to the following commit: be252b6 net: imx: Add multi-FEC support for imx_get_mac_from_fuse has change the imx_get_mac_from_fuse fucntion prototype, but fail to update i.mx5, here it does it. After apply this patch, u-boot works again on i.mx51/53 evk boards. Signed-off-by: Jason Liu <jason.hui(a)linaro.org> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/mx5/soc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 1533dd8..3f5a4f7 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -72,7 +72,7 @@ u32 get_cpu_rev(void) } #if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(unsigned char *mac) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; -- 1.7.4.1

3 3

[U-Boot] [PATCH v3] arm, arm-kirkwood: disable l2c before linux boot
by Michael Walle 01 Feb '12

01 Feb '12

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled. Signed-off-by: Michael Walle <michael(a)walle.cc> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Wolfgang Denk <wd(a)denx.de> --- v3: remove unused enable function v2: replace magic number with macro arch/arm/cpu/arm926ejs/cache.c | 9 ++++++++ arch/arm/cpu/arm926ejs/cpu.c | 2 + arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 + arch/arm/cpu/arm926ejs/kirkwood/cache.c | 34 ++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index ee90ab7..504f604 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -68,3 +68,12 @@ void flush_cache(unsigned long start, unsigned long size) { } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +/* + * Stub implementations for l2 cache operations + */ +void __l2_cache_disable(void) +{ +} +void l2_cache_disable(void) + __attribute__((weak, alias("__l2_cache_disable"))); diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 5c902df..626384c 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -50,6 +50,8 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + l2_cache_disable(); + /* flush I/D-cache */ cache_flush(); diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -30,6 +30,7 @@ COBJS-y = cpu.o COBJS-y += dram.o COBJS-y += mpp.o COBJS-y += timer.o +COBJS-y += cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644 index 0000000..3e73565 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2011 Michael Walle + * Michael Walle <michael(a)walle.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <asm/arch/cpu.h> + +#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22) + +void l2_cache_disable() +{ + u32 ctrl; + + ctrl = readfr_extra_feature_reg(); + ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN; + writefr_extra_feature_reg(ctrl); +} -- 1.7.2.5

2 1

[U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)
by Eric Nelson 01 Feb '12

01 Feb '12

This patch set refactors mxc_spi as described in http://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in http://lists.denx.de/pipermail/u-boot/2012-January/116023.html in order to add support for the MX6Q in general and the mx6qsabrelite specifically. Patch 1 simply moves the conditional parts of mxc_spi.c into the respective CPU-specific imx-regs.h files. Patch 2 adds general support for SPI to the i.MX6. Patch 3 adds support to the mx6qsabrelite board

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[U-Boot] [PATCH 1/4] net: fec_mxc: add 1000 Mbps selection
by Troy Kisky 01 Feb '12

01 Feb '12

Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- drivers/net/fec_mxc.c | 18 +++++++++++++++++- drivers/net/fec_mxc.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 3affda8..3fffe79 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -378,6 +378,7 @@ static int fec_set_hwaddr(struct eth_device *dev) static int fec_open(struct eth_device *edev) { struct fec_priv *fec = (struct fec_priv *)edev->priv; + int speed; debug("fec_open: fec_open(dev)\n"); /* full-duplex, heartbeat disabled */ @@ -427,8 +428,23 @@ static int fec_open(struct eth_device *edev) #endif miiphy_wait_aneg(edev); - miiphy_speed(edev->name, fec->phy_id); + speed = miiphy_speed(edev->name, fec->phy_id); miiphy_duplex(edev->name, fec->phy_id); +#ifdef CONFIG_MX6Q + { + u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; + u32 rcr = (readl(&fec->eth->r_cntrl) & + ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | + FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; + if (speed == _1000BASET) + ecr |= FEC_ECNTRL_SPEED; + else if (speed != _100BASET) + rcr |= FEC_RCNTRL_RMII_10T; + writel(ecr, &fec->eth->ecntrl); + writel(rcr, &fec->eth->r_cntrl); + } +#endif + debug("%s:Speed=%i\n", __func__, speed); /* * Enable SmartDMA receive task diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 39337bf..1d6ab06 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -198,6 +198,7 @@ struct ethernet_regs { #define FEC_RCNTRL_FCE 0x00000020 #define FEC_RCNTRL_RGMII 0x00000040 #define FEC_RCNTRL_RMII 0x00000100 +#define FEC_RCNTRL_RMII_10T 0x00000200 #define FEC_TCNTRL_GTS 0x00000001 #define FEC_TCNTRL_HBC 0x00000002 @@ -207,6 +208,7 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ +#define FEC_ECNTRL_SPEED 0x00000020 #define FEC_ECNTRL_DBSWAP 0x00000100 #define FEC_X_WMRK_STRFWD 0x00000100 -- 1.7.5.4

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[U-Boot] [PATCH] arm, arm-kirkwood: disable l2c before linux boot
by Michael Walle 01 Feb '12

01 Feb '12

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled. Signed-off-by: Michael Walle <michael(a)walle.cc> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> --- arch/arm/cpu/arm926ejs/cache.c | 15 +++++++++++ arch/arm/cpu/arm926ejs/cpu.c | 2 + arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 + arch/arm/cpu/arm926ejs/kirkwood/cache.c | 41 ++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 4415642..7a7d0a6 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -73,3 +73,18 @@ void flush_cache(unsigned long start, unsigned long size) { } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +/* + * Stub implementations for l2 cache operations + */ +void __l2_cache_enable(void) +{ +} +void l2_cache_enable(void) + __attribute__((weak, alias("__l2_cache_enable"))); + +void __l2_cache_disable(void) +{ +} +void l2_cache_disable(void) + __attribute__((weak, alias("__l2_cache_disable"))); diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 5c902df..626384c 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -50,6 +50,8 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + l2_cache_disable(); + /* flush I/D-cache */ cache_flush(); diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/cpu/arm926ejs/kirkwood/Makefile @@ -30,6 +30,7 @@ COBJS-y = cpu.o COBJS-y += dram.o COBJS-y += mpp.o COBJS-y += timer.o +COBJS-y += cache.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644 index 0000000..84207f7 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/kirkwood/cache.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2011 Michael Walle + * Michael Walle <michael(a)walle.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <asm/arch/cpu.h> + +void l2_cache_enable() +{ + u32 ctrl; + + ctrl = readfr_extra_feature_reg(); + ctrl |= 1 << 22; /* enable l2 cache */ + writefr_extra_feature_reg(ctrl); +} + +void l2_cache_disable() +{ + u32 ctrl; + + ctrl = readfr_extra_feature_reg(); + ctrl &= ~(1 << 22); /* disable l2 cache */ + writefr_extra_feature_reg(ctrl); +} -- 1.7.2.5

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[U-Boot] slow flash write with Freescale P1020 and PC28F256J3 NOR-flash
by Daniel Nilsson 31 Jan '12

31 Jan '12

I am bringing up a board that has a Freescale P1020 (PowerPC e500v2) and a 16-bit PC28F256J3 NOR-flash on it. My problem is that both erases and programming takes very long time. Reading from the flash on the other hand, is quite fast (at least a few MByte/s). I have set up the BR0, OR0 and other GPCM-related parameters to be as fast as the datasheet allows. To give an example of how slow it is, programming 24MiB data takes around 45 minutes. Erasing the area before programming takes 2-3 minutes. I have based my project on a 2011.09 version of u-boot. Is there any known limitation, problem or workaround? Regards Daniel Nilsson

2 1

[U-Boot] [PATCH 1/2] sf: drop unused/duplicate command defines
by Mike Frysinger 31 Jan '12

31 Jan '12

In an effort to unify the spi flash drivers further, drop all the unused and/or duplicate command defines. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/mtd/spi/eon.c | 9 --------- drivers/mtd/spi/macronix.c | 11 +---------- drivers/mtd/spi/ramtron.c | 23 +++++------------------ drivers/mtd/spi/spansion.c | 10 ---------- drivers/mtd/spi/spi_flash_internal.h | 2 +- drivers/mtd/spi/sst.c | 14 ++++---------- drivers/mtd/spi/stmicro.c | 8 -------- drivers/mtd/spi/winbond.c | 9 --------- 8 files changed, 11 insertions(+), 75 deletions(-) diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c index f9352f9..6a3bf0f 100644 --- a/drivers/mtd/spi/eon.c +++ b/drivers/mtd/spi/eon.c @@ -11,17 +11,8 @@ #include "spi_flash_internal.h" /* EN25Q128-specific commands */ -#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ -#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ -#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25Q128_PP 0x02 /* Page Program */ #define CMD_EN25Q128_SE 0x20 /* Sector Erase */ #define CMD_EN25Q128_BE 0xd8 /* Block Erase */ -#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ struct eon_spi_flash_params { u8 idcode1; diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index dacbc28..87a3ad0 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -36,18 +36,9 @@ #include "spi_flash_internal.h" /* MX25xx-specific commands */ -#define CMD_MX25XX_WREN 0x06 /* Write Enable */ -#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ -#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ -#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ -#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ -#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_MX25XX_PP 0x02 /* Page Program */ #define CMD_MX25XX_SE 0x20 /* Sector Erase */ #define CMD_MX25XX_BE 0xD8 /* Block Erase */ #define CMD_MX25XX_CE 0xc7 /* Chip Erase */ -#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ -#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ struct macronix_spi_flash_params { u16 idcode; @@ -128,7 +119,7 @@ static int macronix_write_status(struct spi_flash *flash, u8 sr) return ret; } - cmd = CMD_MX25XX_WRSR; + cmd = CMD_WRITE_STATUS; ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1); if (ret) { debug("SF: fail to write status register\n"); diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c index 27d4039..0999781 100644 --- a/drivers/mtd/spi/ramtron.c +++ b/drivers/mtd/spi/ramtron.c @@ -54,19 +54,6 @@ #include <spi_flash.h> #include "spi_flash_internal.h" -/* RAMTRON commands common to all devices */ -#define CMD_RAMTRON_WREN 0x06 /* Write Enable */ -#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */ -#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */ -#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */ -#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */ -#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */ -/* not all have those: */ -#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */ -#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */ -#define CMD_RAMTRON_RDID 0x9f /* Read ID */ -#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */ - /* * Properties of supported FRAMs * Note: speed is currently not used because we have no method to deliver that @@ -196,7 +183,7 @@ static int ramtron_common(struct spi_flash *flash, return ret; } - if (command == CMD_RAMTRON_WRITE) { + if (command == CMD_PAGE_PROGRAM) { /* send WREN */ ret = spi_flash_cmd_write_enable(flash); if (ret < 0) { @@ -206,7 +193,7 @@ static int ramtron_common(struct spi_flash *flash, } /* do the transaction */ - if (command == CMD_RAMTRON_WRITE) + if (command == CMD_PAGE_PROGRAM) ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len); else ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len); @@ -223,14 +210,14 @@ static int ramtron_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) { return ramtron_common(flash, offset, len, buf, - CMD_RAMTRON_READ); + CMD_READ_ARRAY_SLOW); } static int ramtron_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { return ramtron_common(flash, offset, len, (void *)buf, - CMD_RAMTRON_WRITE); + CMD_PAGE_PROGRAM); } static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len) @@ -270,7 +257,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) * We COULD have a non JEDEC conformant FRAM here, * read the status register to verify */ - ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1); + ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1); if (ret) return NULL; diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 6301d87..b99bd13 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -32,18 +32,8 @@ #include "spi_flash_internal.h" /* S25FLxx-specific commands */ -#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ -#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ -#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ -#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ -#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ -#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ -#define CMD_S25FLXX_PP 0x02 /* Page Program */ #define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ #define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ -#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ -#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ #define SPSN_ID_S25FL008A 0x0213 #define SPSN_ID_S25FL016A 0x0214 diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 91e036a..0c78249 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -17,8 +17,8 @@ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b -#define CMD_READ_ARRAY_LEGACY 0xe8 +#define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 9559c80..e51dfc7 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -18,12 +18,6 @@ #include "spi_flash_internal.h" -#define CMD_SST_WREN 0x06 /* Write Enable */ -#define CMD_SST_WRDI 0x04 /* Write Disable */ -#define CMD_SST_RDSR 0x05 /* Read Status Register */ -#define CMD_SST_WRSR 0x01 /* Write Status Register */ -#define CMD_SST_READ 0x03 /* Read Data Bytes */ -#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ #define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ #define CMD_SST_SE 0x20 /* Sector Erase */ @@ -137,7 +131,7 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); ret = sst_enable_writing(flash); if (ret) @@ -184,7 +178,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0], offset); ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, @@ -232,13 +226,13 @@ sst_unlock(struct spi_flash *flash) if (ret) return ret; - cmd = CMD_SST_WRSR; + cmd = CMD_WRITE_STATUS; status = 0; ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); if (ret) debug("SF: Unable to set status byte\n"); - debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); + debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_READ_STATUS)); return ret; } diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index a9b33cf..5b68479 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -34,16 +34,8 @@ #include "spi_flash_internal.h" /* M25Pxx-specific commands */ -#define CMD_M25PXX_WREN 0x06 /* Write Enable */ -#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ -#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ -#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ -#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ -#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_M25PXX_PP 0x02 /* Page Program */ #define CMD_M25PXX_SE 0xd8 /* Sector Erase */ #define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ -#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ #define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ struct stmicro_spi_flash_params { diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index a6a6653..05e555a 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -11,18 +11,9 @@ #include "spi_flash_internal.h" /* M25Pxx-specific commands */ -#define CMD_W25_WREN 0x06 /* Write Enable */ -#define CMD_W25_WRDI 0x04 /* Write Disable */ -#define CMD_W25_RDSR 0x05 /* Read Status Register */ -#define CMD_W25_WRSR 0x01 /* Write Status Register */ -#define CMD_W25_READ 0x03 /* Read Data Bytes */ -#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_W25_PP 0x02 /* Page Program */ #define CMD_W25_SE 0x20 /* Sector (4K) Erase */ #define CMD_W25_BE 0xd8 /* Block (64K) Erase */ #define CMD_W25_CE 0xc7 /* Chip Erase */ -#define CMD_W25_DP 0xb9 /* Deep Power-down */ -#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ struct winbond_spi_flash_params { uint16_t id; -- 1.7.8.4

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