January 2012 - U-Boot

[U-Boot] [PATCH 1/4] fpga: add definition for Xilinx Spartan-6 XC6SLX4
by Stefano Babic 08 Feb '12

08 Feb '12

Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- include/spartan3.h | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/include/spartan3.h b/include/spartan3.h index 67ede4b..89f1156 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -80,6 +80,12 @@ typedef struct { #define XILINX_XC3S1200E_SIZE 3841184/8 #define XILINX_XC3S1600E_SIZE 5969696/8 +/* + * Spartan-6 : the Spartan-6 family can be programmed + * exactly as the Spartan-3 + */ +#define XILINK_XC6SLX4_SIZE (3713568/8) + /* Descriptor Macros *********************************************************************/ /* Spartan-III devices */ @@ -123,4 +129,7 @@ typedef struct { #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */ -- 1.7.5.4

4 17

[U-Boot] [PATCH V4 0/2] Support for HTKW mcx board
by Ilya Yanok 08 Feb '12

08 Feb '12

Hi All, these patches introduce support for HTKW mcx board (AM3517-based) including OMAP3 EHCI support. Regards, Ilya. Ilya Yanok (2): ehci-omap: driver for EHCI host on OMAP3 mcx: support for HTKW mcx board MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 ++++ board/htkw/mcx/mcx.c | 91 +++++++++ board/htkw/mcx/mcx.h | 408 ++++++++++++++++++++++++++++++++++++++++ board/ti/beagle/beagle.c | 101 ---------- boards.cfg | 1 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 +++++++++++++++ include/configs/mcx.h | 371 ++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 10 files changed, 1073 insertions(+), 101 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 drivers/usb/host/ehci-omap.c create mode 100644 include/configs/mcx.h -- 1.7.6.4

7 40

[U-Boot] [PATCH] kirkwood: add support for D-Link DNS-325
by Stefan Herbrechtsmeier 08 Feb '12

08 Feb '12

From: Stefan <stefan(a)odin.(none)> This patch adds support for D-Link DNS-325 ShareCenter NAS. Signed-off-by: Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> Cc: prafulla(a)marvell.com Cc: albert.u.boot(a)aribaud.net --- MAINTAINERS | 4 + board/d-link/dns325/Makefile | 49 +++++++++ board/d-link/dns325/dns325.c | 148 +++++++++++++++++++++++++++ board/d-link/dns325/dns325.h | 48 +++++++++ board/d-link/dns325/kwbimage.cfg | 208 ++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/dns325.h | 188 ++++++++++++++++++++++++++++++++++ 7 files changed, 646 insertions(+), 0 deletions(-) create mode 100644 board/d-link/dns325/Makefile create mode 100644 board/d-link/dns325/dns325.c create mode 100644 board/d-link/dns325/dns325.h create mode 100644 board/d-link/dns325/kwbimage.cfg create mode 100644 include/configs/dns325.h diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..2c4b968 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -668,6 +668,10 @@ Kshitij Gupta <kshitij(a)ti.com> omap1510inn ARM925T omap1610inn ARM926EJS +Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> + + dns325 ARM926EJS (Kirkwood SoC) + Vaibhav Hiremath <hvaibhav(a)ti.com> am3517_evm ARM ARMV7 (AM35x SoC) diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile new file mode 100644 index 0000000..35da21a --- /dev/null +++ b/board/d-link/dns325/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2011 +# Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := dns325.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c new file mode 100644 index 0000000..990d79f --- /dev/null +++ b/board/d-link/dns325/dns325.c @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2011 + * Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> +#include "dns325.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH, + DNS325_OE_LOW, DNS325_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, /* sata1(left) status led */ + MPP21_SATA0_ACTn, /* sata0(right) status led */ + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, /* power off out */ + MPP25_GPIO, + MPP26_GPIO, /* power led */ + MPP27_GPIO, /* sata0(right) error led */ + MPP28_GPIO, /* sata1(left) error led */ + MPP29_GPIO, /* usb error led */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, /* power key */ + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, /* enable sata 0 */ + MPP40_GPIO, /* enable sata 1 */ + MPP41_GPIO, /* hdd0 present */ + MPP42_GPIO, /* hdd1 present */ + MPP43_GPIO, /* usb status led */ + MPP44_GPIO, /* fan status */ + MPP45_GPIO, /* fan high speed */ + MPP46_GPIO, /* fan low speed */ + MPP47_GPIO, /* usb umount */ + MPP48_GPIO, /* factory reset */ + MPP49_GPIO, /* thermal sensor */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); + + kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1); + return 0; +} + +int board_init(void) +{ + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + debug("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h new file mode 100644 index 0000000..7859cea --- /dev/null +++ b/board/d-link/dns325/dns325.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2011 + * Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __DNS325_H +#define __DNS325_H + +/* GPIO configuration */ +#define DNS325_OE_LOW 0x00000000 +#define DNS325_OE_HIGH 0x00039604 +#define DNS325_OE_VAL_LOW 0x38000000 /* disable leds */ +#define DNS325_OE_VAL_HIGH 0x00000800 /* disable leds */ + +#define DNS325_GPIO_LED_POWER 26 +#define DNS325_GPIO_SATA0_EN 39 +#define DNS325_GPIO_SATA1_EN 40 + +/* PHY related */ +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __DNS325_H */ diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg new file mode 100644 index 0000000..97cb090 --- /dev/null +++ b/board/d-link/dns325/kwbimage.cfg @@ -0,0 +1,208 @@ +# +# Copyright (C) 2011 +# Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, 3120 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +DATA 0xFFD01404 0x39543000 # DDR Controller Control Low +# bit3-0: 0 required +# bit4: 0, addr/cmd in smame cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) +# bit3-0: 1, 18 cycle tRAS (tRAS[3-0]) +# bit7-4: 5, 6 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 5, 6 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 1, 18 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 2, 3 cycle tRRD +# bit31-28: 2, 3 cyle tRTP + +DATA 0xFFD0140C 0x00000833 # DDR Timing (High) +# bit6-0: 0x33, 33 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +DATA 0xFFD01410 0x0000000c # DDR Address Control +# bit1-0: 0, Cs0width=x8 +# bit3-2: 3, Cs0size=1Gb +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 0, Write recovery for auto-precharge (3 required ??) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DRAM DLL enabled +# bit1: 0, DRAM drive strength normal +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) +# bit5-3: 0 required +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 1, CS1 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1 +# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM +# bit31-24: 0 required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..b443c45 100644 --- a/boards.cfg +++ b/boards.cfg @@ -136,6 +136,7 @@ hawkboard arm arm926ejs da8xxevm davinci hawkboard_nand arm arm926ejs da8xxevm davinci davinci hawkboard:NAND_U_BOOT hawkboard_uart arm arm926ejs da8xxevm davinci davinci hawkboard:UART_U_BOOT enbw_cmc arm arm926ejs enbw_cmc enbw davinci +dns325 arm arm926ejs - d-link kirkwood km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX mgcoge3un arm arm926ejs km_arm keymile kirkwood diff --git a/include/configs/dns325.h b/include/configs/dns325.h new file mode 100644 index 0000000..b7a89d3 --- /dev/null +++ b/include/configs/dns325.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 + * Stefan Herbrechtsmeier <stefan(a)code.herbrechtsmeier.net> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_DNS325_H +#define _CONFIG_DNS325_H + +/* + * Machine number definition + */ +#define MACH_TYPE_DNS325 3800 +#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 +#define CONFIG_IDENT_STRING "\nD-Link DNS-325" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DATE +#define CONFIG_SYS_MVFS + +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ +#define CONFIG_NETCONSOLE +#endif + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif + +/* + * RTC driver configuration + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MV +#endif + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Display cpu info at boot + */ +#define CONFIG_DISPLAY_CPUINFO + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_ADDR 0xe0000 +#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */ + +/* + * Default environment variables + */ +#define MTDIDS_DEFAULT "nand0=orion_nand" + +#define MTDPARTS_DEFAULT "mtdparts=orion_nand:" \ + "896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "console=ttyS0,115200\0" \ + "mtdparts="MTDPARTS_DEFAULT \ + "optargs=\0" \ + "bootenv=uEnv.txt\0" \ + "importbootenv=echo Importing environment ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \ + "setbootargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${bootenvroot} " \ + "rootfstype=${bootenvrootfstype}\0" \ + "subbootcmd=run setbootargs; " \ + "if run bootenvloadimage; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ + "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \ + "nandrootfstype=ubifs\0" \ + "nandloadimage=nand read ${loadaddr} kernel\0" \ + "setnandbootenv=echo Booting from nand ...; " \ + "setenv bootenvroot ${nandroot}; " \ + "setenv bootenvrootfstype ${nandrootfstype}; " \ + "setenv bootenvloadimage ${nandloadimage}\0" + +#define CONFIG_BOOTCOMMAND \ + "if test -n ${bootenv} && usb start; then " \ + "if run loadbootenv; then " \ + "echo Loaded environment ${bootenv} from usb;" \ + "run importbootenv;" \ + "fi;" \ + "if test -n ${bootenvcmd}; then " \ + "echo Running bootenvcmd ...;" \ + "run bootenvcmd;" \ + "fi;" \ + "fi;" \ + "run setnandbootenv subbootcmd;" + +#endif /* _CONFIG_DNS325_H */ -- 1.7.5.4

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[U-Boot] [PATCH 0/4] Add USB support to orion5x and edminiv2
by Albert ARIBAUD 08 Feb '12

08 Feb '12

This patch set adds USB support to the LaCie ED Mini V2 by renaming the 'kirkwood' USB driver a 'marvell' USB driver, sharing it between the orion5x SoC family and enabling it for the edminiv2 board. (this is similar to what was done with the 'mvgbe' driver in commits 9b6bcdcb to ab9164d0) Albert ARIBAUD (4): Rename ehci-kirkwood as ehci-marvell Remove kirkwood-specifics from marvell EHCI driver orion5x: add USB host ehci-marvell support edminiv2: add USB host support arch/arm/include/asm/arch-kirkwood/config.h | 2 +- arch/arm/include/asm/arch-kirkwood/kirkwood.h | 12 ++++++ arch/arm/include/asm/arch-orion5x/orion5x.h | 12 ++++++ drivers/usb/host/Makefile | 2 +- .../usb/host/{ehci-kirkwood.c => ehci-marvell.c} | 36 ++++++++++++-------- include/configs/edminiv2.h | 14 ++++++++ 6 files changed, 62 insertions(+), 16 deletions(-) rename drivers/usb/host/{ehci-kirkwood.c => ehci-marvell.c} (73%) -- 1.7.5.4

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[U-Boot] [PATCH 1/2] arm/km: speed up i2c access for keymile boards
by Holger Brunck 08 Feb '12

08 Feb '12

We don't need 3us delay for our i2c bus. Decrease it to 1us. It would also be possible to use 100ns in the future, but currently kirkwood has no ndelay implementation. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> Cc: Valentin Longchamp <valentin.longchamp(a)keymile.com> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Heiko Schocher <hs(a)denx.de> --- include/configs/km/km_arm.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 700124c..ca84932 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -195,7 +195,7 @@ int get_scl(void); #define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) #endif -#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ +#define I2C_DELAY udelay(1) #define I2C_SOFT_DECLARATIONS #endif -- 1.7.1

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[U-Boot] [PATCH] i.MX28: Fix VDDIO and VDDA setup
by Marek Vasut 07 Feb '12

07 Feb '12

The DC power STS shouldn't be checked if booting off 5V supply. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Detlev Zundel <dzu(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Robert Deliën <robert(a)delien.nl> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) Note: Guys, please give this a testrun. I think it might fix the issue Robert was observing. I dug into the imx-bootlets and the bootrom X-Files and found this paranormal piece of code. Adding it fixes the boot issue on my crappy board. M diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index ee0f237..c6c25d9 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -802,7 +802,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -837,7 +839,9 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vddioctrl, POWER_VDDIOCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -895,7 +899,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & @@ -930,7 +936,9 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); - if (powered_by_linreg) + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & -- 1.7.8.3

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[U-Boot] [PATCH 1/3] mx28evk: add RTC support
by Matthias Fuchs 07 Feb '12

07 Feb '12

This patch adds support for the MX28 internal RTC and enables u-boot's date command. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- include/configs/mx28evk.h | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bea46e7..8a752aa 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_GPIO #define CONFIG_CMD_MII @@ -150,6 +151,13 @@ #endif /* + * RTC + */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MXS +#endif + +/* * Boot Linux */ #define CONFIG_CMDLINE_TAG -- 1.6.1

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[U-Boot] flash post test
by vk 07 Feb '12

07 Feb '12

Hi all, Currently I am testing the Flash memory by using "Write and Read the same pattern" method (Protecting the UBoot Flash Sectors). Is it safer to test flash memory during bootup?what if power gets off during process? I want to know whether there is any alternative method to test the complete FLASH MEMORY.

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[U-Boot] Can u-Boot Ran from RAM?
by Bud Miljkovic 06 Feb '12

06 Feb '12

Hi there, While getting acquainted with possible u-Boot development issues, I read FAQ "14.2.1. Can U-Boot be configured such that it can be started in RAM?" and was puzzled to learn that u-Boot cannot run from RAM. Considering a custom platform, using i.MX536, I understand that the i.MX53x processor has its own ROM-based code that performs boot time essential devices initialisation, etc. In the case when NAND flash is the program-image medium at the boot stage, first, the ROM-based code checks for Discovered Bad Blocks Table (DBBT) presence and searches for valid Firmware Configuration Block (FCB) on external NAND Flash. If FCB is found that points to the NAND Flash page(s) that contain the first 4K of initial firmware to be loaded from NAND Flash. Then, it loads the 4K of data, pointed by FCB, into the NFC RAM buffer. These data contain a valid Image Vector Table (IVT). Then, the ROM-based code processes IVT, executes the Device Configuration Data (DCD) sequences to initialize boot-related integrated peripherals (typically, these are IOMUX, SDRAM controller and boot memory controller), then copies the application code, also contained in IVT, to target memory (typically, SDRAM) and jumps to it. Typically, this application code is the custom primary bootloader that completes loading the application code (e.g. main OS bootloader) and passes the control to it. If FCB is not found the ROM-based code starts executing a download protocol over UART or USB port in an attempt to get a valid IVT from a host. If the IVT is eventually obtained it is processed as before. So the question is can this "custom primary bootloader" role, in fact, be played by u-Boot. Reading your text of FAQ 14.2.1., it seems to me that it cannot. On the other hand I know of some Freescale i.MX53x demo boards (e.g. ARD, LOCO) that use u-Boot. I wonder what I'm missing here. Regards, Bud

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[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 06 Feb '12

06 Feb '12

Hi Albert, please pull from u-boot-imx, thanks. The following changes since commit 5d250e52ffd5554834a45ac8d53762fbbf36933c: tegra2: Enable data cache (2012-01-18 15:54:07 -0700) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master Dirk Behme (4): imximage: Add MX53 to the documentation imximage: Add support for i.MX6 imximage: Sort bootops alphabetically i.mx6q: configs: Add fdt_high and initrd_high variables Fabio Estevam (2): sdhc_boot: Introduce CONFIG_FSL_FIXED_MMC_LOCATION option configs: Remove CONFIG_NET_MULTI from board files Helmut Raiger (1): mmc: access mxcmmc from mx31 boards Jason Liu (1): i.mx6q: mx6qsabrelite: Add the ethernet function support Stefano Babic (1): imx6: mx6qarm2: updated board_mmc_getcd() to the new prototype Troy Kisky (2): i.mx6: mx6x_pins: Fix uart txd definitions i.mx6q: mx6qsabrelite: Setup uart1 pinmux arch/arm/cpu/arm1136/mx31/generic.c | 1 + arch/arm/cpu/arm926ejs/mx27/generic.c | 35 ++++++-- arch/arm/include/asm/arch-mx27/clock.h | 22 ++--- arch/arm/include/asm/arch-mx31/clock.h | 3 +- arch/arm/include/asm/arch-mx31/imx-regs.h | 11 +++ arch/arm/include/asm/arch-mx31/sys_proto.h | 2 +- arch/arm/include/asm/arch-mx6/mx6x_pins.h | 36 +++----- board/freescale/common/Makefile | 2 +- board/freescale/mx6qarm2/mx6qarm2.c | 9 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 114 +++++++++++++++++++++++++ doc/README.imximage | 13 ++-- drivers/mmc/mxcmmc.c | 8 +- include/configs/MPC8536DS.h | 1 + include/configs/P1010RDB.h | 5 +- include/configs/P1_P2_RDB.h | 1 + include/configs/P2020COME.h | 1 + include/configs/P2020DS.h | 1 + include/configs/P2041RDB.h | 1 + include/configs/PM826.h | 2 - include/configs/PM828.h | 2 - include/configs/cam_enc_4xx.h | 1 - include/configs/coreboot.h | 6 -- include/configs/corenet_ds.h | 1 + include/configs/ecovec.h | 1 - include/configs/efikamx.h | 1 - include/configs/enbw_cmc.h | 1 - include/configs/ethernut5.h | 1 - include/configs/flea3.h | 1 - include/configs/m28evk.h | 1 - include/configs/mx6qarm2.h | 2 + include/configs/mx6qsabrelite.h | 15 +++- include/configs/omap3_evm_common.h | 1 - include/configs/omap3_mvblx.h | 1 - include/configs/p1_p2_rdb_pc.h | 7 +-- include/configs/tam3517-common.h | 1 - tools/imximage.c | 8 +- tools/imximage.h | 2 + 37 files changed, 222 insertions(+), 99 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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