January 2012 - U-Boot

[U-Boot] [PATCH V4] AT91: pio: Add PIO3 features
by Hong Xu 06 Feb '12

06 Feb '12

This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu <hong.xu(a)atmel.com> Acked-by: Remy Bohmer <linux(a)bohmer.net> --- Changes since V3 Add Acked-by from Remy Bohmer arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++++++++++- drivers/gpio/at91_gpio.c | 130 +++++++++++++++++++++++++++- 2 files changed, 171 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..069368d 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) * * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. @@ -17,7 +18,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) @@ -66,14 +66,51 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(ATMEL_CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ +#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(ATMEL_CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* Additional Interrupt Modes Enable Register*/ + u32 aimdr; /* Additional Interrupt Modes Disable Register*/ + u32 aimmr; /* Additional Intterupt Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/ + u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE4 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +131,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..3676ba1 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -1,6 +1,8 @@ /* * Memory Setup stuff - taken from blob memsetup.S * + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) + * * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) * * Copyright (C) 2005 HP Labs @@ -58,7 +60,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "GPIO" peripheral role. + * mux the pin to the "GPIO" peripheral function. */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { @@ -75,7 +77,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "A" internal peripheral role. + * mux the pin to the "A" internal peripheral function. */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { @@ -86,14 +88,21 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } /* - * mux the pin to the "B" internal peripheral role. + * mux the pin to the "B" internal peripheral function. */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { @@ -104,13 +113,120 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +#if defined(ATMEL_CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral function. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); writel(mask, &pio->port[port].pdr); } return 0; } /* + * mux the pin to the "D" internal peripheral function. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (is_on) { + writel(1 << pin, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV_MASK, &pio->port[port].scdr); + writel(1 << pin, &pio->port[port].ifer); + } else { + writel(1 << pin, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_pulldown) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + writel(1 << pin, &pio->port[port].pudr); + if (is_pulldown) + writel(1 << pin, &pio->port[port].ppder); + else + writel(1 << pin, &pio->port[port].ppddr); + } + return 0; +} + +/* + * Set Schmitt trigger mode + */ +int at91_set_pio_schmitt_trig(unsigned port, unsigned pin, int is_enabled) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 data; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + data = readl(&pio->port[port].schmitt); + if (is_enabled) + data &= ~(1 << pin); + else + data |= (1 << pin); + writel(data, &pio->port[port].schmitt); + } + return 0; +} +#endif + +/* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. */ @@ -162,10 +278,14 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(ATMEL_CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } } return 0; } -- 1.7.3.3

1 1

[U-Boot] [PATCH] TRATS: set gpio of UART correctly
by Minkyu Kang 06 Feb '12

06 Feb '12

Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> Cc: Chander Kashyap <chander.kashyap(a)linaro.org> --- board/samsung/trats/trats.c | 18 +++++++----------- 1 files changed, 7 insertions(+), 11 deletions(-) diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f795ff0..aa4291d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -336,21 +336,17 @@ static void board_uart_init(void) (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); int i; - /* UART0-UART1 GPIOs (part1) : 0x22222222 */ - for (i = 0; i < 7; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); - } - /* - * UART2-UART3 GPIOs (part2) : 0x00223322 - * GPA1CON[3] = I2C_3_SCL (3) + * UART2 GPIOs + * GPA1CON[0] = UART_2_RXD(2) + * GPA1CON[1] = UART_2_TXD(2) * GPA1CON[2] = I2C_3_SDA (3) + * GPA1CON[3] = I2C_3_SCL (3) */ - for (i = 0; i < 5; i++) { + + for (i = 0; i < 4; i++) { s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, - GPIO_FUNC((i == 2 || i == 3) ? 0x3 : 0x2)); + s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ -- 1.7.5.4

2 1

[U-Boot] [PATCH 0/7] tegra: Add I2C driver and associated parts
by Simon Glass 04 Feb '12

04 Feb '12

This series brings in an I2C driver for Tegra which can be configured by a flat device tree. It supports 8- and 16-bit addresses and both the normal I2C ports and the DVC port (for controlling the power management unit (PMU)). Simon Glass (6): tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE tegra: fdt: Add extra I2C definitions for U-Boot tegra: Add I2C support to funcmux tegra: Initialise I2C on Nvidia boards tegra: Select I2C ordering for Seaboard tegra: Enable I2C on Seaboard Yen Lin (1): tegra: Add I2C driver arch/arm/cpu/armv7/tegra2/ap20.c | 10 +- arch/arm/cpu/armv7/tegra2/board.c | 2 +- arch/arm/cpu/armv7/tegra2/funcmux.c | 75 +++- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/include/asm/arch-tegra2/funcmux.h | 3 + arch/arm/include/asm/arch-tegra2/tegra2.h | 8 +- arch/arm/include/asm/arch-tegra2/tegra2_i2c.h | 167 ++++++++ board/nvidia/common/board.c | 4 + board/nvidia/dts/tegra2-seaboard.dts | 5 + drivers/i2c/Makefile | 1 + drivers/i2c/tegra2_i2c.c | 533 +++++++++++++++++++++++++ include/configs/seaboard.h | 8 + include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 14 files changed, 809 insertions(+), 21 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_i2c.h create mode 100644 drivers/i2c/tegra2_i2c.c -- 1.7.3.1

5 32

[U-Boot] [PATCH] nand_spl_simple: store ecc data on the stack
by Stefano Babic 03 Feb '12

03 Feb '12

Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM which is likely to contain already loaded data. The patch saves the oob data and the ecc on the stack replacing the fixed address in RAM. Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Ilya Yanok <yanok(a)emcraft.com> CC: Scott Wood <scottwood(a)freescale.com> CC: Tom Rini <tom.rini(a)gmail.com> CC: Simon Schwarz <simonschwarzcor(a)googlemail.com> CC: Wolfgang Denk <wd(a)denx.de> CC: Heiko Schocher <hs(a)denx.de> --- Note: Ilya has already submitted a patch to fix this issue: http://patchwork.ozlabs.org/patch/128018/ after discussing on ML about booting linux from SPL, we agree about putting the data on the stack. drivers/mtd/nand/nand_spl_simple.c | 27 ++++++--------------------- 1 files changed, 6 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index ed821f2..a3d1af0 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -145,9 +145,9 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, uchar *dst) { struct nand_chip *this = mtd.priv; - u_char *ecc_calc; - u_char *ecc_code; - u_char *oob_data; + u_char ecc_calc[CONFIG_SYS_NAND_ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES]; + u_char ecc_code[CONFIG_SYS_NAND_ECCTOTAL]; + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; int eccsize = CONFIG_SYS_NAND_ECCSIZE; int eccbytes = CONFIG_SYS_NAND_ECCBYTES; @@ -155,14 +155,6 @@ static int nand_read_page(int block, int page, uchar *dst) uint8_t *p = dst; int stat; - /* - * No malloc available for now, just use some temporary locations - * in SDRAM - */ - ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000); - ecc_code = ecc_calc + 0x100; - oob_data = ecc_calc + 0x200; - nand_command(block, page, 0, NAND_CMD_READOOB); this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); nand_command(block, page, 0, NAND_CMD_READ0); @@ -185,9 +177,9 @@ static int nand_read_page(int block, int page, uchar *dst) static int nand_read_page(int block, int page, void *dst) { struct nand_chip *this = mtd.priv; - u_char *ecc_calc; - u_char *ecc_code; - u_char *oob_data; + u_char ecc_calc[CONFIG_SYS_NAND_ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES]; + u_char ecc_code[CONFIG_SYS_NAND_ECCTOTAL]; + u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; int eccsize = CONFIG_SYS_NAND_ECCSIZE; int eccbytes = CONFIG_SYS_NAND_ECCBYTES; @@ -197,13 +189,6 @@ static int nand_read_page(int block, int page, void *dst) nand_command(block, page, 0, NAND_CMD_READ0); - /* No malloc available for now, just use some temporary locations - * in SDRAM - */ - ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000); - ecc_code = ecc_calc + 0x100; - oob_data = ecc_calc + 0x200; - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { if (this->ecc.mode != NAND_ECC_SOFT) this->ecc.hwctl(&mtd, NAND_ECC_READ); -- 1.7.5.4

8 27

[U-Boot] compile the u-boot
by Jilin Zhou 03 Feb '12

03 Feb '12

Hi there, Today I downloaded u-boot-2011.12. When I tried to build the u-boot for omap4_panda, I go the following error msg: /u-boot-2011.12/include/common.h:744: error: expected declaration specifiers or '...' before 'va_list' In file included from lib/asm-offsets.c:18: /u-boot-2011.12/include/common.h:777: error: expected declaration specifiers or '...' before 'va_list' make: *** [lib/asm-offsets.s] Error 1 What is the issue? Thanks, Jilin

3 4

[U-Boot] mx28: booting u-boot via USB
by Matthias Fuchs 03 Feb '12

03 Feb '12

Hi, I have a problem booting the current u-boot-imx version on a MX28EVK via USB. The i.MX28 CPU supports a special boot mode where the image (sb boot stream) is downloaded via USB device (all DIP switches in position 'off' on the EVK). The CPU's internal bootrom implements a HID device in this mode. Freescale provides a download tool "sb_loader" for this purpose. There is also a GPL'd implementation based on libusb. So back to my problem: I build u-boot from the u-boot-imx repository. This runs fine when booting from SD/MMC or SPI-flash. But the console stays dark when using the USB download mode. USB download works fine with the Freescale provided U-Boot sources together with the imx-bootlets SPL code. Now I digged a little bit deeper to find out the cause: When downloading via USB I saw the SPL running correctly. board_init_ll() (arch/arm/cpu/arm926ejs/mx28/start.S) runs through correctly. Then control is passed back to the bootrom. That's where things end as far as I can see. The 2nd stage of u-boot is not started. The USB boot mechanism is not documented that detailed. Is it possible that the SPL code overwrites the bootroms ivt and in consequence crashes the bootrom's USB code? Any further ideas? Matthias

3 6

[U-Boot] [PATCH] arm, davinci: cam_enc_4xx board updates
by Heiko Schocher 02 Feb '12

02 Feb '12

- CONFIG_SYS_MMC_ENV_DEV, needed if environment on mmc - wait for 1 second timer in board_late_init() only, if timer is running. - add UBI/UBIFS support - add FIT images support - menu support - U-Boot max size now 0xa0000 - SPL now Block 0 page 0 - new MTD partitioning 0x00000000 SPL 0x00020000 UBL-Header 0x00040000 UBL-Header 0x00060000 UBL-Header 0x00080000 UBoot (0xa0000(U-Boot length) + 0x60000(3 spare blocks)) 0x00180000 ENV- Variablen (1) 0x001a0000 ENV- Variablen (2) 0x001c0000 ENV- Variablen (reserved for Bad Block) 0x001e0000 ENV- Variablen (reserved for Bad Block) 0x00200000 UBI-Device UBI Volumes: „default“: contain environment-default values „rootfs1“: UBIFS root-fs (1); contain linux kernel image „rootfs2“: UBIFS root-fs (2); contain linux kernel image „data-ro“: UBIFS data (read only) „data-rw“: UBIFS data (read/write) - new environment variables: - app_reset (this is only passed per cmdline to linux) - dvn_app_vers string from ramdisk description contained in the FIT image - dvn_boot_vers string from ubootimage description contained in the FIT image - saveparms, restoreparms, restoretmpparms, savetmpparms helper for saving network parameter. - ubiargs set ubi kernel cmdlinargs for booting with a ubifs rootfs - ubi_ubi boot with reading kernel image from ubifs, and use a ubifs as rootfs Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Tom Rini <tom.rini(a)gmail.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- - checkpatch shows no errors/warnings - patches needed for this patch: - arm, davinci: add workaround for not resetting DMA bus and VPSS modules http://patchwork.ozlabs.org/patch/136155/ - arm, davinci: add timer defines for tcr field http://patchwork.ozlabs.org/patch/136156/ - common, image: introduce new uimage types http://patchwork.ozlabs.org/patch/136157/ - common, menu: enhancements http://lists.denx.de/pipermail/u-boot/2012-January/115904.html patches: - common: add possibility for readline_into_buffer timeout http://patchwork.ozlabs.org/patch/136161/ - common, menu: add statusline support http://patchwork.ozlabs.org/patch/136163/ - common, menu: show menu on startup if CONFIG_MENU_SHOW is defined http://patchwork.ozlabs.org/patch/136162/ - a "MAKEALL -a arm" compiiles fine with this patches board/ait/cam_enc_4xx/cam_enc_4xx.c | 626 ++++++++++++++++++++++++++++++++++- board/ait/cam_enc_4xx/ublimage.cfg | 2 +- include/configs/cam_enc_4xx.h | 131 ++++++-- 3 files changed, 730 insertions(+), 29 deletions(-) diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index f438c15..c447fdc 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -20,6 +20,7 @@ */ #include <common.h> +#include <errno.h> #include <linux/mtd/nand.h> #include <nand.h> #include <miiphy.h> @@ -46,6 +47,12 @@ static unsigned long get_timer_val(void) return now; } +static int timer_running(void) +{ + return readl(&timer->tcr) & + (DV_TIMER_TCR_ENAMODE_MASK << DV_TIMER_TCR_ENAMODE34_SHIFT); +} + static void stop_timer(void) { writel(0x0, &timer->tcr); @@ -66,8 +73,43 @@ int board_init(void) } #ifdef CONFIG_DRIVER_TI_EMAC +static int cam_enc_4xx_check_network(void) +{ + char *s; + + s = getenv("ethaddr"); + if (!s) + return -EINVAL; + + if (!is_valid_ether_addr((const u8 *)s)) + return -EINVAL; + + s = getenv("ipaddr"); + if (!s) + return -EINVAL; + + s = getenv("netmask"); + if (!s) + return -EINVAL; + + s = getenv("serverip"); + if (!s) + return -EINVAL; + + s = getenv("gatewayip"); + if (!s) + return -EINVAL; + + return 0; +} int board_eth_init(bd_t *bis) { + int ret; + + ret = cam_enc_4xx_check_network(); + if (ret) + return ret; + davinci_emac_initialize(); return 0; @@ -254,8 +296,11 @@ static int nand_switch_hw_func(int mode) nand = mtd->priv; if (mode == 0) { - printf("switching to uboot hw functions.\n"); - memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl)); + if (notsaved == 0) { + printf("switching to uboot hw functions.\n"); + memcpy(&nand->ecc, &org_ecc, + sizeof(struct nand_ecc_ctrl)); + } } else { /* RBL */ printf("switching to RBL hw functions.\n"); @@ -329,7 +374,8 @@ int board_late_init(void) struct davinci_gpio *gpio = davinci_gpio_bank45; /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */ - while (get_timer_val() < 0x186a00) + while ((get_timer_val() < CONFIG_AIT_TIMER_TIMEOUT) && + timer_running()) ; /* 1 sec reached -> stop timer, clear all LED */ @@ -429,3 +475,577 @@ void arch_memory_failure_handle(void) ; } #endif +#if defined(CONFIG_MENU) +#include "menu.h" + +#define MENU_EXIT -1 +#define MENU_EXIT_BOOTCMD -2 +#define MENU_STAY 0 +#define MENU_MAIN 1 +#define MENU_UPDATE 2 +#define MENU_NETWORK 3 +#define MENU_LOAD 4 + +static int menu_start; + +struct fit_images_info { + u_int8_t type; + char desc[200]; + const void *data; + size_t size; +}; + +static struct fit_images_info images[10]; + +struct menu_display { + char title[50]; + int timeout; /* in sec */ + int id; /* MENU_* */ + char **menulist; + int (*menu_evaluate)(char *choice); +}; + +char *menu_main[] = { + "(1) Boot", + "(2) Update Software", + "(3) Reset to default setting and boot", + "(4) Enter U-Boot console", + NULL +}; + +char *menu_update[] = { + "(1) Network settings", + "(2) load image", + "(3) back to main", + NULL +}; + +char *menu_load[] = { + "(1) install image", + "(2) cancel", + NULL +}; + +char *menu_network[] = { + "(1) ipaddr ", + "(2) netmask ", + "(3) serverip ", + "(4) gatewayip", + "(5) tftp image name", + "(6) back to update software", + NULL +}; + +static void ait_menu_print(void *data) +{ + printf("%s\n", (char *)data); + return; +} + +static char *menu_handle(struct menu_display *display) +{ + struct menu *m; + int i; + char *choice = NULL; + char key[2]; + int ret; + char *s; + char temp[6][200]; + + m = menu_create(display->title, display->timeout, 1, ait_menu_print); + + for (i = 0; display->menulist[i]; i++) { + sprintf(key, "%d", i + 1); + if (display->id == MENU_NETWORK) { + switch (i) { + case 0: + s = getenv("ipaddr"); + break; + case 1: + s = getenv("netmask"); + break; + case 2: + s = getenv("serverip"); + break; + case 3: + s = getenv("gatewayip"); + break; + case 4: + s = getenv("img_file"); + break; + default: + s = NULL; + break; + } + if (s) { + sprintf(temp[i], "%s: %s", + display->menulist[i], s); + ret = menu_item_add(m, key, temp[i]); + } else { + ret = menu_item_add(m, key, + display->menulist[i]); + } + } else { + ret = menu_item_add(m, key, display->menulist[i]); + } + + if (ret != 1) { + printf("failed to add item!"); + menu_destroy(m); + return NULL; + } + } + sprintf(key, "%d", 1); + menu_default_set(m, key); + + if (menu_get_choice(m, (void **)&choice) != 1) + debug("Problem picking a choice!\n"); + + menu_destroy(m); + + return choice; +} + +static int ait_menu_show(struct menu_display *display) +{ + int end = MENU_STAY; + char *choice; + char *s; + int bootdelay = 0; + + if ((menu_start == 0) && (display->id == MENU_MAIN)) { + s = getenv("bootdelay"); + bootdelay = s ? (int)simple_strtol(s, NULL, 10) : + CONFIG_BOOTDELAY; + display->timeout = bootdelay; + } else { + display->timeout = 0; + } + while (end == MENU_STAY) { + choice = menu_handle(display); + if (choice) + end = display->menu_evaluate(choice); + + if (end == display->id) + end = MENU_STAY; + if (display->id == MENU_MAIN) { + if (menu_start == 0) + end = MENU_EXIT_BOOTCMD; + else + display->timeout = 0; + } + } + return end; +} + +static int ait_writeublheader(void) +{ + char s[20]; + unsigned long i; + int ret; + + for (i = CONFIG_SYS_NAND_BLOCK_SIZE; + i < CONFIG_SYS_NAND_U_BOOT_OFFS; + i += CONFIG_SYS_NAND_BLOCK_SIZE) { + sprintf(s, "%lx", i); + ret = setenv("header_addr", s); + if (ret == 0) + ret = run_command2("run img_writeheader", 0); + if (ret != 0) + break; + } + return ret; +} + +static int ait_menu_install_images(void) +{ + int ret = 0; + int count = 0; + char s[100]; + char *t; + + /* + * possible image types: + * IH_TYPE_UBOOTIMAGE + * IH_TYPE_UBLHEADER + * IH_TYPE_UBLIMAGE + * IH_TYPE_SPLIMAGE + * IH_TYPE_RAMDISK + * IH_TYPE_DFENVIMAGE + * + * use Envvariables: + * img_addr_r: image start addr + * header_addr: addr where to write to UBL header + * img_writeheader: write ubl header to nand + * img_writespl: write spl to nand + * img_writeuboot: write uboot to nand + * img_writedfenv: write default environment to ubi volume + * img_volume: which ubi volume should be updated with img_writeramdisk + * filesize: size of data for updating ubi volume + * img_writeramdisk: write ramdisk to ubi volume + */ + + while (images[count].type != IH_TYPE_INVALID) { + printf("Installing %s\n", + genimg_get_type_name(images[count].type)); + sprintf(s, "%p", images[count].data); + setenv("img_addr_r", s); + sprintf(s, "%lx", (unsigned long)images[count].size); + setenv("filesize", s); + switch (images[count].type) { + case IH_TYPE_DFENVIMAGE: + ret = run_command2("run img_writedfenv", 0); + break; + case IH_TYPE_RAMDISK: + t = getenv("img_volume"); + if (!t) { + ret = setenv("img_volume", "rootfs1"); + } else { + /* switch to other volume */ + if (strncmp(t, "rootfs1", 7) == 0) + ret = setenv("img_volume", "rootfs2"); + else + ret = setenv("img_volume", "rootfs1"); + } + if (ret != 0) + break; + + ret = run_command2("run img_writeramdisk", 0); + break; + case IH_TYPE_SPLIMAGE: + ret = run_command2("run img_writespl", 0); + break; + case IH_TYPE_UBLHEADER: + ret = ait_writeublheader(); + break; + case IH_TYPE_UBLIMAGE: + break; + case IH_TYPE_UBOOTIMAGE: + ret = run_command2("run img_writeuboot", 0); + break; + default: + /* not supported type */ + break; + } + count++; + } + /* now save dvn_* and img_volume env vars to new values */ + if (ret == 0) + ret = run_command2("run savenewvers", 0); + + return ret; +} + +static int ait_menu_evaluate_load(char *choice) +{ + if (!choice) + return -1; + + switch (choice[1]) { + case '1': + /* install image */ + ait_menu_install_images(); + break; + case '2': + /* cancel, back to main */ + break; + } + + return MENU_MAIN; +} + +struct menu_display ait_load = { + .title = "AIT load image", + .timeout = 0, + .id = MENU_LOAD, + .menulist = menu_load, + .menu_evaluate = ait_menu_evaluate_load, +}; + +static void ait_menu_read_env(char *name) +{ + char output[CONFIG_SYS_CBSIZE]; + char cbuf[CONFIG_SYS_CBSIZE]; + int readret; + int ret; + + sprintf(output, "%s old: %s value: ", name, getenv(name)); + memset(cbuf, 0, CONFIG_SYS_CBSIZE); + readret = readline_into_buffer(output, cbuf, 0); + + if (readret >= 0) { + ret = setenv(name, cbuf); + if (ret) { + printf("Error setting %s\n", name); + return; + } + } + return; +} + +static int ait_menu_evaluate_network(char *choice) +{ + if (!choice) + return MENU_MAIN; + + switch (choice[1]) { + case '1': + ait_menu_read_env("ipaddr"); + break; + case '2': + ait_menu_read_env("netmask"); + break; + case '3': + ait_menu_read_env("serverip"); + break; + case '4': + ait_menu_read_env("gatewayip"); + break; + case '5': + ait_menu_read_env("img_file"); + break; + case '6': + return MENU_UPDATE; + break; + } + + return MENU_STAY; +} + +struct menu_display ait_network = { + .title = "AIT network settings", + .timeout = 0, + .id = MENU_NETWORK, + .menulist = menu_network, + .menu_evaluate = ait_menu_evaluate_network, +}; + +static int ait_menu_check_image(void) +{ + char *s; + unsigned long fit_addr; + void *addr; + int format; + char *desc; + int images_noffset; + int noffset; + int ndepth; + int count = 0; + int ret; + int i; + int found_uboot = -1; + int found_ramdisk = -1; + + memset(images, 0, sizeof(images)); + s = getenv("fit_addr_r"); + fit_addr = s ? (unsigned long)simple_strtol(s, NULL, 16) : \ + CONFIG_BOARD_IMG_ADDR_R; + + addr = (void *)fit_addr; + /* check if it is a FIT image */ + format = genimg_get_format(addr); + if (format != IMAGE_FORMAT_FIT) + return -EINVAL; + + if (!fit_check_format(addr)) + return -EINVAL; + + /* print the FIT description */ + ret = fit_get_desc(addr, 0, &desc); + printf("FIT description: "); + if (ret) + printf("unavailable\n"); + else + printf("%s\n", desc); + + /* find images */ + images_noffset = fdt_path_offset(addr, FIT_IMAGES_PATH); + if (images_noffset < 0) { + printf("Can't find images parent node '%s' (%s)\n", + FIT_IMAGES_PATH, fdt_strerror(images_noffset)); + return -EINVAL; + } + + /* Process its subnodes, print out component images details */ + for (ndepth = 0, count = 0, + noffset = fdt_next_node(addr, images_noffset, &ndepth); + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node(addr, noffset, &ndepth)) { + if (ndepth == 1) { + /* + * Direct child node of the images parent node, + * i.e. component image node. + */ + printf("Image %u (%s)\n", count, + fit_get_name(addr, noffset, NULL)); + + fit_image_print(addr, noffset, ""); + + fit_image_get_type(addr, noffset, + &images[count].type); + /* Mandatory properties */ + ret = fit_get_desc(addr, noffset, &desc); + printf("Description: "); + if (ret) + printf("unavailable\n"); + else + printf("%s\n", desc); + + sprintf(images[count].desc, "%s", desc); + + ret = fit_image_get_data(addr, noffset, + &images[count].data, + &images[count].size); + + printf("Data Size: "); + if (ret) + printf("unavailable\n"); + else + genimg_print_size(images[count].size); + printf("Data @ %p\n", images[count].data); + count++; + } + } + + for (i = 0; i < count; i++) { + if (images[i].type == IH_TYPE_UBOOTIMAGE) + found_uboot = i; + if (images[i].type == IH_TYPE_RAMDISK) + found_ramdisk = i; + } + + /* dvn_* env var update, if the FIT descriptors are different */ + if (found_uboot >= 0) { + s = getenv("dvn_boot_vers"); + if (s) { + ret = strcmp(s, images[found_uboot].desc); + if (ret != 0) { + setenv("dvn_boot_vers", + images[found_uboot].desc); + } else { + found_uboot = -1; + printf("no new uboot version\n"); + } + } else { + setenv("dvn_boot_vers", images[found_uboot].desc); + } + } + if (found_ramdisk >= 0) { + s = getenv("dvn_app_vers"); + if (s) { + ret = strcmp(s, images[found_ramdisk].desc); + if (ret != 0) { + setenv("dvn_app_vers", + images[found_ramdisk].desc); + } else { + found_ramdisk = -1; + printf("no new ramdisk version\n"); + } + } else { + setenv("dvn_app_vers", images[found_ramdisk].desc); + } + } + if ((found_uboot == -1) && (found_ramdisk == -1)) + return -EINVAL; + + return 0; +} + +static int ait_menu_evaluate_update(char *choice) +{ + int ret; + + if (!choice) + return MENU_MAIN; + + switch (choice[1]) { + case '1': + return ait_menu_show(&ait_network); + break; + case '2': + /* load image */ + ret = run_command2("run load_img", 0); + printf("ret: %d\n", ret); + if (ret) + return MENU_UPDATE; + + ret = ait_menu_check_image(); + if (ret) + return MENU_UPDATE; + + return ait_menu_show(&ait_load); + break; + case '3': + return MENU_MAIN; + break; + + } + + return MENU_MAIN; +} + +struct menu_display ait_update = { + .title = "AIT Update Software", + .timeout = 0, + .id = MENU_UPDATE, + .menulist = menu_update, + .menu_evaluate = ait_menu_evaluate_update, +}; + +static int ait_menu_evaluate_main(char *choice) +{ + if (!choice) + return MENU_STAY; + + menu_start = 1; + switch (choice[1]) { + case '1': + /* run bootcmd */ + return MENU_EXIT_BOOTCMD; + break; + case '2': + return ait_menu_show(&ait_update); + break; + case '3': + /* reset to default settings */ + setenv("app_reset", "yes"); + return MENU_EXIT_BOOTCMD; + break; + case '4': + /* u-boot shell */ + return MENU_EXIT; + break; + } + + return MENU_EXIT; +} + +struct menu_display ait_main = { + .title = "AIT Main", + .timeout = CONFIG_BOOTDELAY, + .id = MENU_MAIN, + .menulist = menu_main, + .menu_evaluate = ait_menu_evaluate_main, +}; + +int menu_show(void) +{ + int ret; + + run_command2("run saveparms", 0); + ret = ait_menu_show(&ait_main); + run_command2("run restoreparms", 0); + + if (ret == MENU_EXIT_BOOTCMD) + return 0; + + return MENU_EXIT; +} + +void menu_display_statusline(struct menu *m) +{ + printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", + getenv("dvn_boot_vers"), getenv("dvn_app_vers")); + return; +} +#endif diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg index 95182ca..2374c72 100644 --- a/board/ait/cam_enc_4xx/ublimage.cfg +++ b/board/ait/cam_enc_4xx/ublimage.cfg @@ -39,7 +39,7 @@ PAGES 6 # Block number where user bootloader is present # RBL starts always with block 1 -START_BLOCK 5 +START_BLOCK 0 # Page number where user bootloader is present # Page 0 is always UBL header diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 50a967c..82c8fb1 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -135,7 +135,9 @@ #define CONFIG_MTD_DEVICE #define CONFIG_CMD_NAND #define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS #define CONFIG_RBTREE +#define CONFIG_LZO #endif #define CONFIG_CRC32_VERIFY @@ -153,15 +155,24 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LONGHELP +#define CONFIG_MENU +#define CONFIG_MENU_SHOW +#define CONFIG_FIT +#define CONFIG_CMD_PXE +#define CONFIG_BOARD_IMG_ADDR_R 0x80000000 + #ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_SIZE (16 << 10) #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x0 +#define CONFIG_ENV_OFFSET 0x180000 +#define CONFIG_ENV_OFFSET_REDUND 0x1c0000 +#define CONFIG_ENV_RANGE 0x020000 #undef CONFIG_ENV_IS_IN_FLASH #endif #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) #define CONFIG_CMD_ENV +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ #define CONFIG_ENV_IS_IN_MMC @@ -169,6 +180,11 @@ #endif #define CONFIG_BOOTDELAY 3 +/* + * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running + * Timeout 1 second. + */ +#define CONFIG_AIT_TIMER_TIMEOUT 0x186a00 #define CONFIG_CMDLINE_EDITING #define CONFIG_VERSION_VARIABLE @@ -187,20 +203,17 @@ #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ #define MTDIDS_DEFAULT "nand0=davinci_nand.0" - -#ifdef CONFIG_SYS_NAND_LARGEPAGE -/* Use same layout for 128K/256K blocks; allow some bad blocks */ -#define PART_BOOT "2m(bootloader)ro," -#endif - -#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ -#define PART_REST "-(filesystem)" - -#define MTDPARTS_DEFAULT \ - "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST - -#define CONFIG_SYS_NAND_PAGE_SIZE (0x800) -#define CONFIG_SYS_NAND_BLOCK_SIZE (0x20000) +#define MTDPARTS_DEFAULT \ + "mtdparts=" \ + "davinci_nand.0:" \ + "128k(spl)," \ + "384k(UBLheader)," \ + "1m(u-boot)," \ + "512k(env)," \ + "-(ubi)" + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 /* Defines for SPL */ #define CONFIG_SPL @@ -244,7 +257,6 @@ * so we can define, how many UBL Headers * we can write before the real spl code */ -#define CONFIG_SYS_NROF_UBL_HEADER 5 #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6 #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */ @@ -261,8 +273,8 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xc0000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 /* * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is @@ -414,14 +426,14 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \ - "load=tftp ${u_boot_addr_r} ${uboot}\0" \ + "load=tftp ${u_boot_addr_r} ${u-boot}\0" \ "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \ - "writeheader=nandrbl rbl;nand erase 80000 ${pagesz};" \ - "nand write ${u_boot_addr_r} 80000 ${pagesz};" \ + "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \ + "nand write ${u_boot_addr_r} 20000 ${pagesz};" \ "nandrbl uboot\0" \ - "writenand_spl=nandrbl rbl;nand erase a0000 3000;" \ + "writenand_spl=nandrbl rbl;nand erase 0 3000;" \ "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \ - " a0000 3000;nandrbl uboot\0" \ + " 0 3000;nandrbl uboot\0" \ "writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ @@ -429,8 +441,77 @@ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ "update=run load writenand_spl writeuboot\0" \ - "bootcmd=run bootcmd\0" \ + "bootcmd=run net_nfs\0" \ + "rootpath=/opt/eldk-arm/arm\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "netdev=eth0\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyS0," \ + "${baudrate}n8\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \ "rootpath=/opt/eldk-arm/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ + "kernel_addr_r=80600000\0" \ + "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \ + "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "ubifsload ${kernel_addr_r} boot/uImage\0" \ + "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \ + "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \ + "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \ + "header_addr=20000\0" \ + "img_writeheader=nandrbl rbl;" \ + "nand erase ${header_addr} ${pagesz};" \ + "nand write ${img_addr_r} ${header_addr} ${pagesz};" \ + "nandrbl uboot\0" \ + "img_writespl=nandrbl rbl;nand erase 0 3000;" \ + "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \ + "img_writeuboot=nandrbl uboot;" \ + "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ + xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + ";nand write ${img_addr_r} " \ + xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ + xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ + "img_writedfenv=ubi part ubi 2048;" \ + "ubi write ${img_addr_r} default ${filesize}\0" \ + "img_volume=rootfs1\0" \ + "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \ + "load_img=tftp ${fit_addr_r} ${img_file}\0" \ + "net_nfs=run load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "ubi_ubi=run ubi_load_kernel; " \ + "run ubiargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "ubiargs=setenv bootargs ubi.mtd=4,2048" \ + " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \ + "app_reset=no\0" \ + "dvn_app_vers=void\0" \ + "dvn_boot_vers=void\0" \ + "savenewvers=run savetmpparms restoreparms; saveenv;" \ + "run restoretmpparms\0" \ + "savetmpparms=setenv y_ipaddr ${ipaddr};" \ + "setenv y_netmask ${netmask};" \ + "setenv y_serverip ${serverip};" \ + "setenv y_gatewayip ${gatewayip}\0" \ + "saveparms=setenv x_ipaddr ${ipaddr};" \ + "setenv x_netmask ${netmask};" \ + "setenv x_serverip ${serverip};" \ + "setenv x_gatewayip ${gatewayip}\0" \ + "restoreparms=setenv ipaddr ${x_ipaddr};" \ + "setenv netmask ${x_netmask};" \ + "setenv serverip ${x_serverip};" \ + "setenv gatewayip ${x_gatewayip}\0" \ + "restoretmpparms=setenv ipaddr ${y_ipaddr};" \ + "setenv netmask ${y_netmask};" \ + "setenv serverip ${y_serverip};" \ + "setenv gatewayip ${y_gatewayip}\0" \ "\0" /* USB Configuration */ -- 1.7.7.4

2 4

[U-Boot] [PATCH] OMAP SPL: Fix missing timer_init() call in OMAP4 s_init()
by Nicolas Dechesne 02 Feb '12

02 Feb '12

In 8775471bb, the call to timer_init() was removed from common code and put in OMAP3 s_init() function. As a result the boot was broken on OMAP4. This patch adds timer_init() in OMAP4 s_init(), that fix boot on all OMAP4 boards. Signed-off-by: Nicolas Dechesne <n-dechesne(a)ti.com> Tested-by: Robert P. J. Day <rpjday(a)crashcourse.ca> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Tom Rini <trini(a)ti.com> --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 49cdc39..ab46bff 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -120,6 +120,8 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD + timer_init(); + /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); init_boot_params(); -- 1.7.8.3

2 1

[U-Boot] [PATCHv2] OMAP3: Add Corscience Tricorder board
by Thomas Weber 02 Feb '12

02 Feb '12

From: Thomas Weber <weber(a)corscience.de> Tricorder is a board which is very similar to the Devkit8000. It is designed as a base platform for further medical devices. www.corscience.de/en/medical-engineering/products/multiparameter/mp10-board… Signed-off-by: Thomas Weber <weber(a)corscience.de> --- Sorry for the long time between V1 and V2. Changes from V1: - Reworked after comments from Tom and Igor. Thanks. - Changed authorship/derived from - Fix ubifs environment part - Replaced whitespaces with tabs MAINTAINERS | 1 + board/corscience/tricorder/Makefile | 46 ++++ board/corscience/tricorder/tricorder.c | 105 +++++++++ board/corscience/tricorder/tricorder.h | 375 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/tricorder.h | 320 +++++++++++++++++++++++++++ 6 files changed, 848 insertions(+), 0 deletions(-) create mode 100644 board/corscience/tricorder/Makefile create mode 100644 board/corscience/tricorder/tricorder.c create mode 100644 board/corscience/tricorder/tricorder.h create mode 100644 include/configs/tricorder.h diff --git a/MAINTAINERS b/MAINTAINERS index 8c4fe2d..61caa96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,7 @@ Stephen Warren <swarren(a)nvidia.com> Thomas Weber <weber(a)corscience.de> devkit8000 ARM ARMV7 (OMAP3530 SoC) + tricorder ARM ARMV7 (OMAP3503 SoC) Lei Wen <leiwen(a)marvell.com> diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile new file mode 100644 index 0000000..16ef3a3 --- /dev/null +++ b/board/corscience/tricorder/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2012 +# Thomas Weber <weber(a)corscience.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tricorder.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c new file mode 100644 index 0000000..435711a --- /dev/null +++ b/board/corscience/tricorder/tricorder.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2012 + * Corscience GmbH & Co. KG, <www.corscience.de> + * Thomas Weber <weber(a)corscience.de> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * + * Derived from Devkit8000 code by + * Frederik Kriewitz <frederik(a)kriewitz.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include "tricorder.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + twl4030_power_init(); +#ifdef CONFIG_TWL4030_LED + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_TRICORDER(); +} + +#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. We have either one or two banks of 128MB DDR. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *mr = MICRON_V_MR_165; +} diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h new file mode 100644 index 0000000..cae8c75 --- /dev/null +++ b/board/corscience/tricorder/tricorder.h @@ -0,0 +1,375 @@ +/* + * (C) Copyright 2008 + * Dirk Behme <dirk.behme(a)gmail.com> + * + * (C) Copyright 2012 + * Corscience GmbH & Co. KG, <www.corscience.de> + * Thomas Weber <weber(a)corscience.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _TRICORDER_H_ +#define _TRICORDER_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 Tricorder", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_TRICORDER() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /* Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /* MMC Slot */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /* Expansion Header */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\ + MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ + /* Serial Interface */\ + MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + /* Host USB0 */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ + /* USB EHCI (port 2) */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - BOOTMODE*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SIMO*/\ + MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SOMI*/\ + MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS0*/\ + MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CLK*/\ + MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M4)) /*GPIO_18*/\ + MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M4)) /*GPIO_19*/\ + MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M4)) /*GPIO_20*/\ + MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS1*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M4)) /*MSECURE*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ + /*HSUSB2 */\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\ + /* */\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/ + +#endif diff --git a/boards.cfg b/boards.cfg index 2f90dbf..d7b41a4 100644 --- a/boards.cfg +++ b/boards.cfg @@ -213,6 +213,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h new file mode 100644 index 0000000..f87696b --- /dev/null +++ b/include/configs/tricorder.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * (C) Copyright 2012 + * Corscience GmbH & Co. KG + * Thomas Weber <weber(a)corscience.de> + * + * Configuration settings for the Tricorder board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ + +#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Display CPU and Board information */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_OF_LIBFDT + +/* Size of malloc() pool */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512 << 10)) + +/* Hardware drivers */ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* select serial console configuration */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* TWL4030 */ +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED + +/* Board NAND Info */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:" \ + "512k(u-boot-spl)," \ + "1920k(u-boot)," \ + "128k(u-boot-env)," \ + "4m(kernel)," \ + "-(fs)" + +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ +#define CONFIG_CMD_UBI /* UBIFS commands */ + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +/* needed for ubi */ +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS + +/* Environment information */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "vram=12M\0" \ + "lcdmode=800x600\0" \ + "defaultdisplay=lcd\0" \ + "kernelopts=rw rootwait\0" \ + "commonargs=" \ + "setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=lcd:${lcdmode} " \ + "omapdss.def_disp=${defaultdisplay}\0" \ + "mmcargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 " \ + "${kernelopts}\0" \ + "nandargs=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "omapfb.mode=lcd:${lcdmode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=ubi0:rootfs " \ + "rootfstype=ubifs " \ + "${kernelopts}\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + "autoboot=if mmc init 0; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi\0" + + +#define CONFIG_BOOTCOMMAND "run autoboot" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 0x01000000) /* 16MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* The stack sizes are set up in start.S using the settings below */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* NAND and environment organization */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* SRAM config */ +#define CONFIG_SYS_SRAM_START 0x40200000 +#define CONFIG_SYS_SRAM_SIZE 0x10000 + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ + +#endif /* __CONFIG_H */ -- 1.7.8.4

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[U-Boot] [PATCH v5 0/7] Change ARM926EJ-S startup code, hawkboard and calimain
by Christian Riesch 02 Feb '12

02 Feb '12

Hi, In this patchset I tried to put everything from the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html Although this is the first version of this patchset, the version number is v5 since Sughosh's patches were already v4. Regards, Christian Christian Riesch (5): arm, davinci: Add lowlevel_init for SoCs other than DM644X arm, arm926ejs: Do cpu critical inits only for boards that require it arm, arm926ejs: Do not clear the V bit on DA850 SoCs arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined arm, davinci: Add support for the Calimain board from OMICRON electronics Sughosh Ganu (2): arm, arm926ejs: Flush the data cache before disabling it Changes to move hawkboard to the new spl infrastructure MAINTAINERS | 5 + arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 24 +- arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 4 + arch/arm/cpu/arm926ejs/davinci/spl.c | 4 +- arch/arm/cpu/arm926ejs/start.S | 26 +- arch/arm/include/asm/arch-davinci/da850_lowlevel.h | 9 + board/davinci/da8xxevm/da850evm.c | 4 +- board/davinci/da8xxevm/hawkboard.c | 23 ++ board/davinci/da8xxevm/hawkboard_nand_spl.c | 115 ------- .../{u-boot-spl.lds => u-boot-spl-da850evm.lds} | 0 .../davinci/da8xxevm/u-boot-spl-hawk.lds | 22 +- board/enbw/enbw_cmc/enbw_cmc.c | 13 +- board/omicron/calimain/Makefile | 45 +++ board/omicron/calimain/calimain.c | 188 ++++++++++ boards.cfg | 2 +- doc/README.hawkboard | 43 ++-- include/configs/calimain.h | 362 ++++++++++++++++++++ include/configs/cam_enc_4xx.h | 6 - include/configs/da850evm.h | 6 +- include/configs/enbw_cmc.h | 5 +- include/configs/hawkboard.h | 23 +- nand_spl/board/davinci/da8xxevm/Makefile | 155 --------- 22 files changed, 738 insertions(+), 346 deletions(-) delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c rename board/davinci/da8xxevm/{u-boot-spl.lds => u-boot-spl-da850evm.lds} (100%) rename nand_spl/board/davinci/da8xxevm/u-boot.lds => board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%) create mode 100644 board/omicron/calimain/Makefile create mode 100644 board/omicron/calimain/calimain.c create mode 100644 include/configs/calimain.h delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile

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