August 2011 - U-Boot

[U-Boot] [PATCH] omap4: fix pad configuration settings for SDP and Panda
by Aneesh V 19 Aug '11

19 Aug '11

Signed-off-by: Aneesh V <aneesh(a)ti.com> Signed-off-by: Sebastien Jan <s-jan(a)ti.com> Signed-off-by: David Anders <x0132446(a)ti.com> --- board/ti/panda/panda_mux_data.h | 41 ++++++++++++++++------------------ board/ti/sdp4430/sdp4430_mux_data.h | 9 ++----- 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 16cc0ad..63448b6 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -23,8 +23,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _SDP4430_MUX_DATA_H -#define _SDP4430_MUX_DATA_H +#ifndef _PANDA_MUX_DATA_H_ +#define _PANDA_MUX_DATA_H_ #include <asm/arch/mux_omap4.h> @@ -43,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ {GPMC_A20, (IEN | M3)}, /* gpio_44 */ {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A22, (M3)}, /* gpio_46 */ {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ {GPMC_A24, (PTD | M3)}, /* gpio_48 */ {GPMC_A25, (PTD | M3)}, /* gpio_49 */ @@ -57,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ {C2C_DATA14, (M1)}, /* dsi2_te0 */ {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ @@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ @@ -115,7 +115,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ {UART2_RTS, (M0)}, /* uart2_rts */ @@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {UART4_RX, (IEN | M0)}, /* uart4_rx */ {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ @@ -155,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ + {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ + {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ @@ -171,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {SYS_BOOT1, (M3)}, /* gpio_185 */ {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ + {SYS_BOOT3, (M3)}, /* gpio_187 */ {SYS_BOOT4, (M3)}, /* gpio_188 */ {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ @@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ + {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ - {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ }; -#endif /* _SDP4430_MUX_DATA_H */ +#endif /* _PANDA_MUX_DATA_H_ */ diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 16cc0ad..06efaea 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 - Debug led-2 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ - {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ }; #endif /* _SDP4430_MUX_DATA_H */ -- 1.7.0.4

1 0

[U-Boot] Ns16550 doesn't send anything
by Altunbas Sabri (DC-IA/EAH2) 19 Aug '11

19 Aug '11

Hi, I port u-boot last version on my board with SH7785. My board has no serial port (SCIF's are not connected). Therefore i try to communicate over a pci2s-card which has a ns16650 chip. i debug with Lauterbach-Debugger and can see the character in THR/RHR register. i can receive the character but can not send any character. though I write the character in the THR-register. i have no more idea. Thanks, for any clue Best regards, S.Altunbas

1 0

[U-Boot] DEAR FRIEND KINDLY VIEW THE ATTACHED FILE AND GET BACK TO ME URGENTLY REGARDS DOUGLAS AKANA
by Douglas Akana 19 Aug '11

19 Aug '11

1 0

[U-Boot] very urgent
by Young 19 Aug '11

19 Aug '11

May I ask if you would be eligible to pursue a Business Proposal of $19.7m with me if you dont mind? Let me know if you are interested.

1 0

[U-Boot] [PATCH] Powerpc/85xx: set liodn for srio in device tree
by Shaohui Xie 19 Aug '11

19 Aug '11

Previous, U-boot did not set fsl,liodn for rapidio in device tree, which is needed by HV(hypervisor), and HV needs fsl,liodn of rapidio have more values, for ex for P4080, fsl,liodn = <198 199 200>; while P2040/P3041/P5020 has 4 LIODNs respectivelly. This patch using a generic mechanism which allow a device have mutilple liodns. Reported-and-tested-by: Diana CRACIUN <Diana.Craciun(a)freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/liodn.c | 20 +++++++++++++++++--- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 6 +++--- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 8 ++++---- 5 files changed, 32 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index bd19094..5ccaaf5 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -149,7 +149,11 @@ void set_liodns(void) static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) { - int i; + int i, j; + int fdt_liodn[8]; + int *p = fdt_liodn; + char *p_compat = NULL; + phys_addr_t cmp_offset = 0; for (i = 0; i < sz; i++) { int off; @@ -160,9 +164,19 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) off = fdt_node_offset_by_compat_reg(blob, tbl[i].compat, tbl[i].compat_offset); if (off >= 0) { + if (p_compat != NULL) { + if (strcmp(tbl[i].compat, p_compat)) + p = fdt_liodn; + else if (cmp_offset != tbl[i].compat_offset) + p = fdt_liodn; + } + for (j = 0; j < tbl[i].num_ids; j++) + *p++ = tbl[i].id[j]; off = fdt_setprop(blob, off, "fsl,liodn", - &tbl[i].id[0], - sizeof(u32) * tbl[i].num_ids); + fdt_liodn, + sizeof(u32) * (p - fdt_liodn)); + p_compat = (char *)tbl[i].compat; + cmp_offset = tbl[i].compat_offset; if (off > 0) printf("WARNING unable to set fsl,liodn for " "%s: %s\n", diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 112ea56..f3b2e7f 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -63,10 +63,10 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 200, rio2liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 201, rio1maintliodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 202, rio2maintliodnr, 0xc0000), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 9836588..b1fbd74 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -64,10 +64,10 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 200, rio2liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 201, rio1maintliodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 202, rio2maintliodnr, 0xc0000), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 560c02a..04164ba 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -53,9 +53,9 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), - SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio2liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 200, rio1maintliodnr, 0xc0000), #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 9836588..b1fbd74 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -64,10 +64,10 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 200, rio2liodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 201, rio1maintliodnr, 0xc0000), + SET_GUTS_LIODN("fsl,rapidio-delta", 202, rio2maintliodnr, 0xc0000), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); -- 1.6.4

1 0

[U-Boot] spi subystem maintainer?
by Kumar Gala 18 Aug '11

18 Aug '11

Do we have one? - k

5 11

[U-Boot] Selectable / delayed initialization
by Simon Glass 18 Aug '11

18 Aug '11

Hi, When U-Boot starts up it initializes all the peripherals which are enabled This might include USB, I2C, SD/MMC, LCD, Ethernet, UARTs, etc. To save time, reduce the amount of code executed and thereby improve security, we are wanting to initialize only some peripherals at the start. For example we might start up I2C and SC/MMC. Later when it becomes clear that USB and Ethernet are needed we want to init those also. I suppose the easiest way of describing this is that we want to have some 'level 0' init, then perhaps move to level 1 and init peripherals at that level, then perhaps to level 2, etc. Quite often we will only get to level 1 before jumping to the kernel. At the moment the U-Boot init code is spread around a bit - there are files called board.c within arch/xx/cpu/, board/xx/ and arch/xx/lib/. So it is hard to make this change just within a board file. Some other files have big lists of init calls like stdio.c and serial.c. I am thinking of creating a way of specifying a list of peripherals which should be inited in each level, then moving all init code into a function which knows how to init each peripheral. Then we can call init_level(2) for example, to start up peripherals in that level. Perhaps level 0 would be reserved for pre-relocation init. I am interested in any thoughts that people have about this and whether it might be implemented in a generally useful way. I am assuming that a driver registration / initcall approach would be a bridge too far for U-Boot at the moment, so I am thinking of a function with a big 'switch' statement. The other related issue is that I notice that the arch/xxx/lib/board.c files are different but have a lot of common code. Is there some scope for starting a common/board.c file which slowly builds up common functionality so that over time we end up with only the architecture-specific code in the arch/lib/xxx/board.c? If so these these two goals could perhaps be progressed together. Regards, Simon

3 8

[U-Boot] [PATCH 3/3 v2] ARM: ARM926EJS - Add cache operations
by Hong Xu 18 Aug '11

18 Aug '11

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file. Signed-off-by: Hong Xu <hong.xu(a)atmel.com> CC: Albert Aribaud <albert.u.boot(a)aribaud.net> --- V2: Fixed a typo when CONFIG_SYS_DCACHE_OFF is defined arch/arm/cpu/arm926ejs/Makefile | 2 +- arch/arm/cpu/arm926ejs/cache.c | 142 +++++++++++++++++++++++++++++++++++++++ include/configs/at91sam9260ek.h | 1 + 3 files changed, 144 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/cache.c diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o START = start.o -COBJS = cpu.o +COBJS = cpu.o cache.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000..fc321f6 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#define FLUSH_CACHE_OP 0 +#define INVALIDATE_CACHE_OP 1 + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * Flush or Invalidate DCache respectively + */ +static void cache_range_op(unsigned long start, unsigned long stop, int op) +{ + int cache_line_len; + unsigned long mva; + char *func_name; + + if (op == FLUSH_CACHE_OP) + func_name = "flush_dcache_range"; + else if (op == INVALIDATE_CACHE_OP) + func_name = "invalidate_dcache_range"; + else { + printf("WARNING: %s - Invalid cache operation!\n", __func__); + return; + } + +#ifdef CONFIG_SYS_CACHELINE_SIZE + cache_line_len = CONFIG_SYS_CACHELINE_SIZE; +#else + /* + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 + * only b'10, aka. 32 bytes cache line len is valid + */ + cache_line_len = 32; +#endif + mva = start; + if ((mva & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - start address 0x%08x not aligned to" + "cache line size(%d bytes)\n", func_name, start, + cache_line_len); + /* Round up starting address */ + mva = (mva | (cache_line_len - 1)) + 1; + } + if ((stop & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - stop address 0x%08x not aligned to" + "cache line size(%d bytes)\n", func_name, stop, + cache_line_len); + /* Round down ending address */ + stop &= ~(cache_line_len - 1); + } + + while (mva < stop) { + if (op == FLUSH_CACHE_OP) + asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva)); + else + asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva)); + + mva += cache_line_len; + } + + /* Drain WB if necessary */ + if (op == FLUSH_CACHE_OP) + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0)); +} + +/* + * The buffer range to be flushed is [start, stop) + */ +void flush_dcache_range(unsigned long start, unsigned long stop) +{ + cache_range_op(start, stop, FLUSH_CACHE_OP); +} + +void flush_dcache_all(void) +{ + /* + * ARM926EJ-S Technical Reference Manual, Chap 2.3.8 + * Clean & Invalidate the entire DCache + */ + asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory"); + /* Drain WB */ + asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0)); +} + +void flush_cache(unsigned long start, unsigned long size) +{ + flush_dcache_range(start, start + size); +} + +/* + * The buffer range to be invalidated is [start, stop) + */ +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + cache_range_op(start, stop, INVALIDATE_CACHE_OP); +} + +void invalidate_dcache_all(void) +{ + asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0)); +} + +#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ + +void flush_cache(unsigned long start, unsigned long size) {} +void flush_dcache_all(void) {} +void flush_dcache_range(unsigned long start, unsigned long stop) {} +void invalidate_dcache_range(unsigned long start, unsigned long stop) {} +void invalidate_dcache_all(void) {} +#endif + +#ifndef CONFIG_SYS_ICACHE_OFF +void invalidate_icache_all(void) +{ + asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0)); +} + +#else /* #ifndef CONFIG_SYS_ICACHE_OFF */ + +void invalidate_icache_all(void) {} +#endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 88578c6..f891d67 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -33,6 +33,7 @@ */ #include <asm/hardware.h> +#define CONFIG_SYS_DCACHE_OFF /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. -- 1.7.6

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[U-Boot] Your Email Won ( £1 ,500,000 GBP)
by Winning Notification 18 Aug '11

18 Aug '11

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Re: [U-Boot] ehci-hcd: Allow cleanups to happen on an EHCI timeout.
by Joel A Fernandes 18 Aug '11

18 Aug '11

Hi Simon, Sorry for the delayed response to your email. I was just trying to prepare a proper response to your email with collating information about similar fixes to the EHCI timeout but never got to completing it. Please excuse me, thanks. I'm following up on your feedback for the patch titled: ehci-hcd: Allow cleanups to happen on an EHCI timeout. [1] > On Sat, Jun 25, 2011 at 12:28 PM, Joel A Fernandes <agnel.joel(a)gmail.com> wrote: >> With this, the EHCI seems to "recover" from a timeout. This is particularly >> observable if you were to ping the wrong IP Address and then ping the correct >> one or if there was a temporary failure during tftp sessions. >> >> All it takes is one timeout to disable it. If you have a noisy network (lot >> of traffic), even if the traffic is not for the board, the timeouts don't occur. >> >> Signed-off-by: Joel A Fernandes <agnel.joel(a)gmail.com> >> --- >> Robert, Could you see if this patch solves the issue you're seeing without >> increasing the timeout? >> Simon, Could this be a fix for a similar issue you were seeing with asix? > > Yes this is better (ASIX can recover from a timeout), but I am > concerned that it carries on without reporting an error. Is that > right? > > Should we disable async schedule and then return an error? Actually, with this patch, the error message is still displayed before disabling async schedule. > > With respect to using a bulk USB stick (some of which take 3s or more > to respond to a submit) this doesn't make any difference for me. It > seems to take a long time to respond the first time, so the 5s timeout > seems prudent. > > Since this sorts out the network side we can probably skip that patch. > Are you suggesting we revert the patch you had submitted [2], instead of deleting the goto line as done in my patch? I think it would be better if we left [2] in and allowed the async disable to happen after a timeout. There are other patches that are reported to fix the issue such as [3] and [4], but I think they appear to be more like workarounds and delay the occurrence of the event of a timeout itself. A timeout which would occur for any other reason such as too many USB devices connected to the hub can trigger the problem, and, not running async schedule and the other code after the timeout seems to make EHCI unrecoverable. Looking forward to your suggestions, Thanks, -Joel [1] http://patchwork.ozlabs.org/patch/102041/ [2] http://lists.denx.de/pipermail/u-boot/2011-February/087043.html [3] http://patchwork.ozlabs.org/patch/100367/ [4] https://github.com/kylemanna/u-boot/commit/a2211d841b5c5b67e1f336a7d8d1e658…

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