August 2011 - U-Boot

[U-Boot] [PATCH] Add flexbus support for Freescale Coldfire 5235
by Jate Sujjavanich 22 Aug '11

22 Aug '11

Add flexbus support for Freescale Coldfire 5235 Signed-off-by Jate Sujjavanich<jate.sujjavanich(a)myfuelmaster.com> --- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h 2011-03-02 11:02:14.000000000 -0500 +++ u-boot/include/asm-m68k/coldfire/flexbus.h 2011-03-25 11:42:46.000000000 -0400 @@ -94,6 +94,12 @@ #endif #define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#ifdef CONFIG_M5235 +#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) +#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) +#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) +#endif + #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) #define FBCS_CSCR_SWS_MASK (0x03FFFFFF) #define FBCS_CSCR_SWSEN (0x00800000)

2 1

[U-Boot] 集客支援izumiと申します。プレゼントを11個用意しました。
by 集客支援＠izumi 22 Aug '11

22 Aug '11

はじめまして、集客支援＠izumiと申します。この度パシフィックインタラクティブ様よりメルマガの譲渡を受けメールを配信させていただいております。このようなメールが不要の際は下記ワンクリックで解除ができます。 http://markteing-support.biz/ms/rm.cgi?m=1111&u=b6238939758f02dc&h=45 集客支援＠izumiのご紹介 ⇒　http://ameblo.jp/izutoshi21/ 読者様に対して、無料もしくは低コストでの集客支援情報などを配信していきたいと思います。お近づきのお示しと致しまして、下記厳選された無料情報をプレゼントさせて頂きます。今後とも宜しくお願い致します。 ◆ダン・ケネディの商品の販売権利　ＮＥＷ！！ http://123direct.info/tracking/af/294836/mhO9CoZS/ ◆7日間無料で10000リスト集めた方法とは！？　ＮＥＷ！！ https://www.viral-manager.com/aff/7984/83/ ◆【ザ・レスポンス】小川忠洋の「実践FREE戦略５つのレッスン」ＮＥＷ！！ http://123direct.info/tracking/af/294836/uglNu3RK/ ◆【書籍】ベストセラー『出稼げば大富豪』　電子版を無料でプレゼント http://123direct.info/tracking/af/378226/6NEOMMTz/ ◆アクセスアップレポート２０１１ http://123direct.info/tracking/af/294836/txsJAPeZ/ ◆ツイッター攻略法 http://123direct.info/tracking/af/318259/VwajP0ni/ ◆フェイスブックの使い方の動画マニュアル http://123direct.info/tracking/af/318259/ppyZ9nKZ/ ◆元ライブドア社長室　渡邉氏の最新Facebook戦略です。 http://sfurl.biz/7gCKO ◆ダンケネディ　３M集客法 http://123direct.info/tracking/af/294836/nMoN1PmA-ZoWNxcny/ ◆ネットショップ集客法 http://123direct.info/tracking/af/294836/jYa427TI/ ◆『不動産投資大百科』１０万円相当⇒無料 http://123direct.info/tracking/af/318259/qwvJsXAH/ 集客支援コンサルタント　izumi 配信担当　松本健一メールアドレス webmaster(a)markteing-support.biz ブログ(読者数４３０名) http://ameblo.jp/izutoshi21/ 所在地大阪府大阪市淀川区十八条２-１６-４６ ■■■■■■■■■■■■■■PR■■■■■■■■■■■■■■■■ 堀江貴文お勧めのパソコン教室　値上げ間近 http://sfurl.biz/BtwPd ■■■■■■■■■■■■■■PR■■■■■■■■■■■■■■■■ 配信を解除する場合は下記URLをクリックしてください。 http://markteing-support.biz/ms/rm.cgi?m=1111&u=b6238939758f02dc&h=45

1 0

[U-Boot] Pull request u-boot-marvell.git
by Prafulla Wadaskar 22 Aug '11

22 Aug '11

Hi Albert Please kindly pull The following changes since commit 043a76397696ca0a77ebee0ffc60bf31bdf37f02: Prafulla Wadaskar (1): Merge branch 'master' of git://git.marvell.com/mirror/denx.de/u-boot-arm into armmaster are available in the git repository at: u-boot-marvell.git master branch. Ajay Bhargav (2): gpio: Add GPIO driver framework for Marvell SoCs gpio: Add GPIO driver for Marvell SoC Armada100 arch/arm/include/asm/arch-armada100/gpio.h | 48 ++++++++++++ drivers/gpio/Makefile | 1 + drivers/gpio/mvgpio.c | 115 ++++++++++++++++++++++++++++ drivers/gpio/mvgpio.h | 74 ++++++++++++++++++ 4 files changed, 238 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h create mode 100644 drivers/gpio/mvgpio.c create mode 100644 drivers/gpio/mvgpio.h Regards.. Prafulla . .

2 8

[U-Boot] [PATCH 3/3] Armada100: Enable 88E3015 PHY support for GplugD
by Ajay Bhargav 22 Aug '11

22 Aug '11

This patch adds support for 88E3015 PHY for Marvell GplugD board. This patch depends on series of patch which adds support for Marvell GuruPlug-Display. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- board/Marvell/gplugd/gplugd.c | 34 +++++++++++++++++++++++++++++++++- include/configs/gplugd.h | 15 ++++++++++++++- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index ac5e35f..fd2e574 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -32,6 +32,8 @@ #include <mvmfp.h> #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#include <asm/gpio.h> +#include <miiphy.h> #ifdef CONFIG_ARMADA100_FEC #include <net.h> @@ -83,6 +85,11 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; /* adress of boot parameters */ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; + /* Assert PHY_RST# */ + gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); + udelay(10); + /* Deassert PHY_RST# */ + gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); return 0; } @@ -97,5 +104,30 @@ int board_eth_init(bd_t *bis) return armada100_fec_initialize(); } -#endif /* CONFIG_ARMADA100_FEC */ +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY chip 88E3015 */ +void reset_phy(void) +{ + u16 phy_adr; + const char *name = "armd-fec0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + /* Set Ethernet LED in TX blink mode */ + miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); + miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); + + /* reset the phy */ + miiphy_reset(name, phy_adr); + printf("88E3015 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ +#endif /* CONFIG_ARMADA100_FEC */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 7fa3020..b63ffd5 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -80,6 +80,20 @@ #define CONFIG_ROOTPATH "/tftpboot" #define CONFIG_SYS_IMG_NAME "uImage" +/* GPIO Support */ +#define CONFIG_MARVELL_GPIO + +/* PHY configuration */ +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_RESET_PHY_R +/* 88E3015 register definition */ +#define PHY_LED_PAR_SEL_REG 22 +#define PHY_LED_MAN_REG 25 +#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ +/* GPIO Configuration for PHY */ +#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -100,4 +114,3 @@ #define CONFIG_ENV_SIZE 0x20000 /* 64k */ #endif /* __CONFIG_GPLUGD_H */ - -- 1.7.0.4

1 0

[U-Boot] [PATCH 2/3] Armada100: Enable Ethernet support for GplugD
by Ajay Bhargav 22 Aug '11

22 Aug '11

This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/mfp.h | 19 ++++++++ board/Marvell/gplugd/gplugd.c | 39 +++++++++++++++ include/configs/gplugd.h | 20 +++++++- 4 files changed, 133 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 3d567eb..849638d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -41,6 +41,10 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_TIMER_BASE 0xD4014000 @@ -85,6 +89,59 @@ struct armd1mpmu_registers { }; /* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* * APB1 Clock Reset/Control Registers * Refer Datasheet Appendix A.10 */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d6e0494..da76b58 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -64,6 +64,25 @@ #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index dc7d89d..ac5e35f 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -33,6 +33,11 @@ #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#ifdef CONFIG_ARMADA100_FEC +#include <net.h> +#include <netdev.h> +#endif /* CONFIG_ARMADA100_FEC */ + DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) @@ -45,6 +50,26 @@ int board_early_init_f(void) /* Enable Console on UART3 */ MFPO8_UART3_TXD, MFPO9_UART3_RXD, + + /* Ethernet PHY Interface */ + MFP086_ETH_TXCLK, + MFP087_ETH_TXEN, + MFP088_ETH_TXDQ3, + MFP089_ETH_TXDQ2, + MFP090_ETH_TXDQ1, + MFP091_ETH_TXDQ0, + MFP092_ETH_CRS, + MFP093_ETH_COL, + MFP094_ETH_RXCLK, + MFP095_ETH_RXER, + MFP096_ETH_RXDQ3, + MFP097_ETH_RXDQ2, + MFP098_ETH_RXDQ1, + MFP099_ETH_RXDQ0, + MFP100_ETH_MDC, + MFP101_ETH_MDIO, + MFP103_ETH_RXDV, + MFP_EOC /*End of configuration*/ }; /* configure MFP's */ @@ -60,3 +85,17 @@ int board_init(void) gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; return 0; } + +#ifdef CONFIG_ARMADA100_FEC +int board_eth_init(bd_t *bis) +{ + struct armd1apmu_registers *apmu_regs = + (struct armd1apmu_registers *) ARMD1_APMU_BASE; + + /* Enable clock of ethernet controller */ + writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); + + return armada100_fec_initialize(); +} +#endif /* CONFIG_ARMADA100_FEC */ + diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index cc14f49..7fa3020 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -62,8 +62,23 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS + +/* Disable DCACHE */ +#define CONFIG_SYS_DCACHE_OFF + +/* Network configuration */ +#define CONFIG_CMD_PING +#define CONFIG_NET_MULTI +#define CONFIG_ARMADA100_FEC + +/* DHCP Support */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_BOOTP_SERVERIP + +/* Default Boot Parameters */ +#define CONFIG_ROOTPATH "/tftpboot" +#define CONFIG_SYS_IMG_NAME "uImage" /* * mv-common.h should be defined after CMD configs since it used them @@ -85,3 +100,4 @@ #define CONFIG_ENV_SIZE 0x20000 /* 64k */ #endif /* __CONFIG_GPLUGD_H */ + -- 1.7.0.4

1 0

[U-Boot] [PATCH 00/09] ColdFire: patches for coldfire to work with current base.
by Jin Zhengxiong-R64188 22 Aug '11

22 Aug '11

The following patches update some ColdFire boards to work with latest u-boot. Those update were tested on following Freescale boards: M54455EVB, M54451EVB, M5475EVB(M5475CFE_config), M5485EVB(M5485HFE_conifg), M5208EVB, M5253DEMO, M52277EVB, M53017EVB, M5373EVB, M5329EVB(M5329BFEE_config) 0001-ColdFire-Fix-the-configuration-broken-for-some-board.patch 0002-ColdFire-Update-compile-flags-for-each-CPUs.patch 0003-ColdFire-Cleanup-for-partial-linking-and-gc-sections.patch 0004-ColdFire-Update-the-timer_init-since-it-was-unified.patch 0005-ColdFire-disable-the-NFS-define-for-52277-board.patch 0006-ColdFire-Update-the-env-settings-for-several-boards.patch 0007-DM9000-Add-a-byte-swap-macro-for-dm9000-io-operation.patch 0008-ColdFire-Define-the-DM9000-byteswap-for-M5253-board.patch 0009-ColdFire-Add-mb-for-5253-dram-initialization.patch

1 0

[U-Boot] [RESEND PATCH 1/9] ColdFire:Fix the configuration broken for some boards.
by Jason Jin 22 Aug '11

22 Aug '11

Some typoes in Makefile and boards.cfg make the M54455 board and M53017 board configuration broken. Signed-off-by: Jason Jin <Jason.jin(a)freescale.com> --- Makefile | 1 + boards.cfg | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 03d80b7..960c046 100644 --- a/Makefile +++ b/Makefile @@ -724,6 +724,7 @@ M54455EVB_stm33_config : unconfig cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \ fi; \ echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ + $(XECHO) "... with $${FREQ}Hz input clock" @$(MKCONFIG) -n $@ -a M54455EVB m68k mcf5445x m54455evb freescale M5475AFE_config \ diff --git a/boards.cfg b/boards.cfg index 6827cf3..8d5076e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -279,7 +279,7 @@ M5271EVB m68k mcf52x2 m5271evb freesca M5272C3 m68k mcf52x2 m5272c3 freescale M5275EVB m68k mcf52x2 m5275evb freescale M5282EVB m68k mcf52x2 m5282evb freescale -M53017EVB m68k mcf52x2 m53017evb freescale +M53017EVB m68k mcf532x m53017evb freescale EP2500 m68k mcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 -- 1.6.4

1 8

[U-Boot] Congratulations Dear Beneficiary
by United Nations Compensation Board 22 Aug '11

22 Aug '11

United Nations Compensation Board Congratulations dear beneficiary, Your email has been selected by the United Nations Compensation Board For a cash grant award of Nine hundred and Fifty Thousand United States Dollars,($950,000.00 USD) for this year 2011 New year Grant Award. Your email address was selected during our random email balloting for the cash grant and if you received this notification, it means that you are a lucky beneficiary of this cash grant award. The United Nations authorities have decided to give this award to 15 beneficiaries from all over the world to help facilitate and improve the standard of living to the Commission. This also includes SCAM VICTIMS, EVERY FOREIGN CONTRACTOR that may have not received their contract sum, and people that have had an unfinished transaction or international businesses that failed due to Government problems etc. We found your contact in our list as one of the lucky beneficiary of the cash grant of Nine hundred and Fifty Thousand United States Dollars, ($950,000.00 USD). This grant is been aided by the United Nations development programme and the United Nations trust funds for human security. Your cash grant pin number is (UNO-154/4456/011). This meeting was first held on the 8th of April 2003. You can view this page for Your perusal: http://www.un.org/News/Press/docs/2003/ik344.doc.htm Assess Code: 8911-89-QDR You are kindly obliged to contact our corresponding UN Payment office (United Nations Trust Funds) in West Africa and they will give details on how your funds would be remitted to you. Do contact our payment office: Payment Officer: Mr. Mark Steven Email: unitednationscompensation(a)live.com Immediately with the following information, below for proper verification and documentation. 1. FULL NAMES OF BENEFICIARY: .................. 2. RESIDENTIAL ADDRESS: ................................. 3. DATE OF BIRTH: ............................. 4. PIN NUMBER: ....................................... 5. PHONE/FAX NUMBERS: ................................... 6. SEX: ................................................. 7. OCCUPATION: .......................................... 8. MARITAL STATUS:. ..................................... 9. COUNTRY:. ........................................... 10. NATIONALITY: ......................................... Note: PLEASE DO NOT RESPOND IF YOU DON'T WISH TO BE COMPENSATED, AS ONLY SERIOUS PERSON'S WILL BE ATTENDED TO YOU AND PAID FULLY. Thank you for your co-operation Regards, Mr. Kofi Anan Former secretary to The UnitedNation. and Mr. Ban Ki-moon. THE NEW UNITED NATIONS SECRETARY GENERAL

1 0

[U-Boot] Attn:
by Douglas J. Flint. 21 Aug '11

21 Aug '11

Attn: This proposal is addressed directly to you as a private obligation that required you and should be treated as utmost Secret. I got your details from my private search after a careful review. I am Mr.Douglas J. Flint the Group Chairman of HSBC Holdings plc. I have a confidential brief for you, I am asking for your partnership in re- profiling some funds. Please get back to me for more information, if you are interested. You can read more about my biography on this link below. http://www.hsbc.com/1/PA_1_1_S5/content/assets/newsroom/media_kit/biogs/110… Regards, Douglas J. Flint. Group Chairman of HSBC Holdings plc.

1 0

[U-Boot] [PATCH] MX35: MX35PDK: support additional RAM on CSD1
by Stefano Babic 21 Aug '11

21 Aug '11

Modules on mx35pdk have additional 128MB memory connected to CSD1. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- board/freescale/mx35pdk/lowlevel_init.S | 9 +++++---- board/freescale/mx35pdk/mx35pdk.c | 17 +++++++++++++++-- include/configs/mx35pdk.h | 6 +++--- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S index 9b0f1b5..9fd04cb 100644 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -193,10 +193,11 @@ mov r2, #0x00 mov r1, #CSD0_BASE_ADDR bl setup_sdram_bank - cmp r3, #0x0 - orreq r5, r5, #1 - eorne r2, r2, #0x1 - blne setup_sdram_bank + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD1_BASE_ADDR + bl setup_sdram_bank mov lr, fp diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index da926e5..a6b5a51 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -52,12 +52,25 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + static void setup_iomux_i2c(void) { int pad; diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 086355b..0d4b733 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -173,11 +173,11 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define iomem_valid_addr(addr, size) \ - (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -- 1.7.1

1 0