August 2011 - U-Boot

Re: [U-Boot] Transfer Offer
by Song Li 18 Aug '11

18 Aug '11

l am a Staff of Hang Seng Bank HongKong, I do not know if we can work together in transferring $19,500,000.USD from my bank to you account. Finally if you are interested I shall provide you with more details. Email: mr_song150(a)yahoo.com.hk

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[U-Boot] [PATCH 1/2] dm3730: enable dpll5
by Eric Bénard 18 Aug '11

18 Aug '11

which is used to provide 120MHz to USB EHCI This allows EHCI to work on BeagleBoard XM Signed-off-by: Eric Bénard <eric(a)eukrea.com> --- arch/arm/cpu/armv7/omap3/clock.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3d38d08..6a9edcf 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -579,6 +579,7 @@ void prcm_init(void) dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); + dpll5_init_34xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); -- 1.7.0.4

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[U-Boot] [PATCH v4] OMAP3: Add DSS driver for OMAP3
by Joel A Fernandes 18 Aug '11

18 Aug '11

From: Syed Mohammed Khasim <khasim(a)ti.com> * Supports dynamic panel configuration * Supports dynamic tv standard selection * Adds support for DSS register access through generic APIs * Incorporated DSS register access using structures. * DSS makefile update Previous discussions are here: http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html --- v2 updates: * Enable panel output for BeagleBoard * BeagleBoard: Update DVI-D orange screen frequencies for xM v3 updates: * Remove non-platform (OMAP3) updates v4 updates: * Addressing fixes for attribution in header: http://lists.denx.de/pipermail/u-boot/2011-August/097976.html Signed-off-by: Syed Mohammed Khasim <khasim(a)ti.com> Signed-off-by: Jason Kridner <jkridner(a)beagleboard.org> Signed-off-by: Joel A Fernandes <agnel.joel(a)gmail.com> --- arch/arm/include/asm/arch-omap3/dss.h | 174 +++++++++++++++++++++++++++++++++ drivers/video/Makefile | 2 + drivers/video/omap3_dss.c | 131 +++++++++++++++++++++++++ 3 files changed, 307 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap3/dss.h create mode 100644 drivers/video/omap3_dss.c diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h new file mode 100644 index 0000000..c09ded8 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef DSS_H +#define DSS_H + +/* + * DSS Base Registers + */ +#define OMAP3_DSS_BASE 0x48050040 +#define OMAP3_DISPC_BASE 0x48050440 +#define OMAP3_VENC_BASE 0x48050C00 + +/* DSS Registers */ +struct dss_regs { + u32 control; /* 0x40 */ + u32 sdi_control; /* 0x44 */ + u32 pll_control; /* 0x48 */ +}; + +/* DISPC Registers */ +struct dispc_regs { + u32 control; /* 0x40 */ + u32 config; /* 0x44 */ + u32 reserve_2; /* 0x48 */ + u32 default_color0; /* 0x4C */ + u32 default_color1; /* 0x50 */ + u32 trans_color0; /* 0x54 */ + u32 trans_color1; /* 0x58 */ + u32 line_status; /* 0x5C */ + u32 line_number; /* 0x60 */ + u32 timing_h; /* 0x64 */ + u32 timing_v; /* 0x68 */ + u32 pol_freq; /* 0x6C */ + u32 divisor; /* 0x70 */ + u32 global_alpha; /* 0x74 */ + u32 size_dig; /* 0x78 */ + u32 size_lcd; /* 0x7C */ +}; + +/* VENC Registers */ +struct venc_regs { + u32 rev_id; /* 0x00 */ + u32 status; /* 0x04 */ + u32 f_control; /* 0x08 */ + u32 reserve_1; /* 0x0C */ + u32 vidout_ctrl; /* 0x10 */ + u32 sync_ctrl; /* 0x14 */ + u32 reserve_2; /* 0x18 */ + u32 llen; /* 0x1C */ + u32 flens; /* 0x20 */ + u32 hfltr_ctrl; /* 0x24 */ + u32 cc_carr_wss_carr; /* 0x28 */ + u32 c_phase; /* 0x2C */ + u32 gain_u; /* 0x30 */ + u32 gain_v; /* 0x34 */ + u32 gain_y; /* 0x38 */ + u32 black_level; /* 0x3C */ + u32 blank_level; /* 0x40 */ + u32 x_color; /* 0x44 */ + u32 m_control; /* 0x48 */ + u32 bstamp_wss_data; /* 0x4C */ + u32 s_carr; /* 0x50 */ + u32 line21; /* 0x54 */ + u32 ln_sel; /* 0x58 */ + u32 l21__wc_ctl; /* 0x5C */ + u32 htrigger_vtrigger; /* 0x60 */ + u32 savid__eavid; /* 0x64 */ + u32 flen__fal; /* 0x68 */ + u32 lal__phase_reset; /* 0x6C */ + u32 hs_int_start_stop_x; /* 0x70 */ + u32 hs_ext_start_stop_x; /* 0x74 */ + u32 vs_int_start_x; /* 0x78 */ + u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ + u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ + u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ + u32 vs_ext_stop_y; /* 0x88 */ + u32 reserve_3; /* 0x8C */ + u32 avid_start_stop_x; /* 0x90 */ + u32 avid_start_stop_y; /* 0x94 */ + u32 reserve_4; /* 0x98 */ + u32 reserve_5; /* 0x9C */ + u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ + u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ + u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ + u32 reserve_6; /* 0xAC */ + u32 tvdetgp_int_start_stop_x; /* 0xB0 */ + u32 tvdetgp_int_start_stop_y; /* 0xB4 */ + u32 gen_ctrl; /* 0xB8 */ + u32 reserve_7; /* 0xBC */ + u32 reserve_8; /* 0xC0 */ + u32 output_control; /* 0xC4 */ + u32 dac_b__dac_c; /* 0xC8 */ + u32 height_width; /* 0xCC */ +}; + +/* Few Register Offsets */ +#define FRAME_MODE_SHIFT 1 +#define TFTSTN_SHIFT 3 +#define DATALINES_SHIFT 8 + +/* Enabling Display controller */ +#define LCD_ENABLE 1 +#define DIG_ENABLE (1 << 1) +#define GO_LCD (1 << 5) +#define GO_DIG (1 << 6) +#define GP_OUT0 (1 << 15) +#define GP_OUT1 (1 << 16) + +#define DISPC_ENABLE (LCD_ENABLE | \ + DIG_ENABLE | \ + GO_LCD | \ + GO_DIG | \ + GP_OUT0| \ + GP_OUT1) + +/* Configure VENC DSS Params */ +#define VENC_CLK_ENABLE (1 << 3) +#define DAC_DEMEN (1 << 4) +#define DAC_POWERDN (1 << 5) +#define VENC_OUT_SEL (1 << 6) +#define DIG_LPP_SHIFT 16 +#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \ + DAC_DEMEN | \ + DAC_POWERDN | \ + VENC_OUT_SEL) +/* + * Panel Configuration + */ +struct panel_config { + u32 timing_h; + u32 timing_v; + u32 pol_freq; + u32 divisor; + u32 lcd_size; + u32 panel_type; + u32 data_lines; + u32 load_mode; + u32 panel_color; +}; + +/* + * Generic DSS Functions + */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width); +void omap3_dss_panel_config(const struct panel_config *panel_cfg); +void omap3_dss_enable(void); + +#endif /* DSS_H */ diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 086dc05..226684a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -41,6 +41,8 @@ COBJS-$(CONFIG_SED156X) += sed156x.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +COBJS-y += videomodes.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c new file mode 100644 index 0000000..6c743d2 --- /dev/null +++ b/drivers/video/omap3_dss.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/dss.h> + +/* + * Configure VENC for a given Mode (NTSC / PAL) + */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width) +{ + struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE; + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + writel(venc_cfg->status, &venc->status); + writel(venc_cfg->f_control, &venc->f_control); + writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl); + writel(venc_cfg->sync_ctrl, &venc->sync_ctrl); + writel(venc_cfg->llen, &venc->llen); + writel(venc_cfg->flens, &venc->flens); + writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl); + writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr); + writel(venc_cfg->c_phase, &venc->c_phase); + writel(venc_cfg->gain_u, &venc->gain_u); + writel(venc_cfg->gain_v, &venc->gain_v); + writel(venc_cfg->gain_y, &venc->gain_y); + writel(venc_cfg->black_level, &venc->black_level); + writel(venc_cfg->blank_level, &venc->blank_level); + writel(venc_cfg->x_color, &venc->x_color); + writel(venc_cfg->m_control, &venc->m_control); + writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data); + writel(venc_cfg->s_carr, &venc->s_carr); + writel(venc_cfg->line21, &venc->line21); + writel(venc_cfg->ln_sel, &venc->ln_sel); + writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl); + writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger); + writel(venc_cfg->savid__eavid, &venc->savid__eavid); + writel(venc_cfg->flen__fal, &venc->flen__fal); + writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset); + writel(venc_cfg->hs_int_start_stop_x, + &venc->hs_int_start_stop_x); + writel(venc_cfg->hs_ext_start_stop_x, + &venc->hs_ext_start_stop_x); + writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x); + writel(venc_cfg->vs_int_stop_x__vs_int_start_y, + &venc->vs_int_stop_x__vs_int_start_y); + writel(venc_cfg->vs_int_stop_y__vs_ext_start_x, + &venc->vs_int_stop_y__vs_ext_start_x); + writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y, + &venc->vs_ext_stop_x__vs_ext_start_y); + writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y); + writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x); + writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y); + writel(venc_cfg->fid_int_start_x__fid_int_start_y, + &venc->fid_int_start_x__fid_int_start_y); + writel(venc_cfg->fid_int_offset_y__fid_ext_start_x, + &venc->fid_int_offset_y__fid_ext_start_x); + writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y, + &venc->fid_ext_start_y__fid_ext_offset_y); + writel(venc_cfg->tvdetgp_int_start_stop_x, + &venc->tvdetgp_int_start_stop_x); + writel(venc_cfg->tvdetgp_int_start_stop_y, + &venc->tvdetgp_int_start_stop_y); + writel(venc_cfg->gen_ctrl, &venc->gen_ctrl); + writel(venc_cfg->output_control, &venc->output_control); + writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c); + + /* Configure DSS for VENC Settings */ + writel(VENC_DSS_CONFIG, &dss->control); + + /* Configure height and width for Digital out */ + writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig); +} + +/* + * Configure Panel Specific Parameters + */ +void omap3_dss_panel_config(const struct panel_config *panel_cfg) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + writel(panel_cfg->timing_h, &dispc->timing_h); + writel(panel_cfg->timing_v, &dispc->timing_v); + writel(panel_cfg->pol_freq, &dispc->pol_freq); + writel(panel_cfg->divisor, &dispc->divisor); + writel(panel_cfg->lcd_size, &dispc->size_lcd); + writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config); + writel(((panel_cfg->panel_type << TFTSTN_SHIFT) | + (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control); + writel(panel_cfg->panel_color, &dispc->default_color0); +} + +/* + * Enable LCD and DIGITAL OUT in DSS + */ +void omap3_dss_enable(void) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + u32 l = 0; + + l = readl(&dispc->control); + l |= DISPC_ENABLE; + writel(l, &dispc->control); +} -- 1.7.1

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[U-Boot] Donation For the work of God
by Mary Williams 17 Aug '11

17 Aug '11

Donation For the work of God PLEASE ENDEAVOUR TO USE IT FOR THE CHILDREN OF GOD.My name is Mrs Mary Williams from SIERRA-LEONE. I am married to Dr.Jonathan Williams who worked with Sierra-Leonian Embassy in South Africa for nine years before he died in the year 2008.We were married for eleven years without a child. He died after a brief illness that lasted for only four days.Before his death we were both born again Christians.Since his death I decided not to re-marry or get a child outside my matrimonial home which the Bible is against.When my late husband was alive he deposited the sum of $8,000,000.00 ( Eight million United State Dollars) with financial institution in Cote d I voire here. Presently, this money is still with the financial institution. Recently, my Doctor told me that I would not last for the next three months due to cancer problem. Though what disturbs me most is my stroke. Having known my condition I decided to donate this fund to church or better still a christian individual that will utilize this money the way I am going to instruct here in. I want a church or individual that will use this to fund churches, orphanages and widows propagating the word of God and to ensure that the house of God is maintained.The Bible made us to understand that Blessed is the hand that giveth. I took this decision because I don't have any child that will inherit this money. I don't want a situation where this money will be used in an ungodly manner, hence the reason for taking this bold decision. I am not afraid of death hence I know where I am going. I know that I am going to be in the bossom of the Lord. Exodus 14 VS 14 says that the lord will fight my case and I shall hold my peace.I don't need any telephone communication in this regard because of my health,and because of the presence of my husband's relatives around me always. I don't want them to know about this development. With God all things are possible. As soon as I receive your reply I shall give you the contact of the Financial institution in Ivory coast.I will also issue you a letter of authority that will empower you as the original- beneficiary of this fund. I want you and the church to always pray for me because the lord is my shephard. My happiness is that I lived a life of a worthy Christian.Who ever that wants to serve the Lord must serve him in spirit and truth. Please always be prayerful all through your life.Any delay in your reply will give me room in sourcing for a church or christian individual for this same purpose. Please assure me that you will act accordingly as I stated herein. Hoping to hear from you soon.Remain blessed in the name of the Lord. Yours in Christ, Mrs Mary William

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[U-Boot] [PATCH] arm: fix bd pointer dereference prior initialization
by Igor Grinberg 17 Aug '11

17 Aug '11

gd->bd pointer has been used prior been initialized. Move the relevant code after the initialization. Signed-off-by: Igor Grinberg <grinberg(a)compulab.co.il> --- arch/arm/lib/board.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index bcbf697..52e90db 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -281,10 +281,6 @@ void board_init_f (ulong bootflag) gd->mon_len = _bss_end_ofs; -#ifdef CONFIG_MACH_TYPE - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ -#endif - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { hang (); @@ -409,6 +405,10 @@ void board_init_f (ulong bootflag) post_run (NULL, POST_ROM | post_bootmode_get(0)); #endif +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + gd->bd->bi_baudrate = gd->baudrate; /* Ram ist board specific, so move it to board code ... */ dram_init_banksize(); -- 1.7.3.4

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[U-Boot] [PATCH] MX: MX35 / MX5: uniform clock command with powerpc
by Stefano Babic 17 Aug '11

17 Aug '11

There was already a command to show the priocessor clocks for PowerPC (clocks). For i.MX, the "clockinfo" command was introduce. The patch sets the same command name used on PowerPC. A nasty and not needed newline is also dropped in the help for the command. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm1136/mx35/generic.c | 4 ++-- arch/arm/cpu/armv7/mx5/clock.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index 5481357..951bccb 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -417,8 +417,8 @@ int do_mx35_showclocks(cmd_tbl_t *cmdtp, } U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, - "display clocks\n", + clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, + "display clocks", "" ); diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 0b04a88..00610a0 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -288,7 +288,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /***************************************************/ U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, - "display clocks\n", + clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, + "display clocks", "" ); -- 1.7.1

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[U-Boot] uboot compilation problem
by Rajeev Rao Battu 17 Aug '11

17 Aug '11

Hi, I am working As R&D engineer. Presently i am compiling u-boot.2011.03 and i am facing bit problem.following is the problem while compiling u-boot. i am using cross compile tool chain. make -C arch/arm/cpu/arm926ejs/at91/ make[1]: Entering directory `/data1/UBOOT/u-boot-2011.03/arch/arm/cpu/arm926ejs/at91' make[1]: Warning: File `.depend' has modification time 1.7e+04 s in the future armv5l-analogics-linux-gnueabi-gcc -D__ASSEMBLY__ -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x23f00000 -I/data1/UBOOT/u-boot-2011.03/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/analogics/at91sam9261_ek/toolchain/bin/../lib/gcc/armv5l-analogics-linux-gnueabi/4.2.4/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5te -o lowlevel_init.o lowlevel_init.S -c armv5l-analogics-linux-gnueabi-gcc -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DCONFIG_SYS_TEXT_BASE=0x23f00000 -I/data1/UBOOT/u-boot-2011.03/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/analogics/at91sam9261_ek/toolchain/bin/../lib/gcc/armv5l-analogics-linux-gnueabi/4.2.4/include -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5te -Wall -Wstrict-prototypes -fno-stack-protector -o clock.o clock.c -c clock.c: In function 'get_cpu_clk_rate': clock.c:30: error: 'gd_t' has no member named 'cpu_clk_rate_hz' clock.c: In function 'get_main_clk_rate': clock.c:35: error: 'gd_t' has no member named 'main_clk_rate_hz' clock.c: In function 'get_mck_clk_rate': clock.c:40: error: 'gd_t' has no member named 'mck_rate_hz' clock.c: In function 'get_plla_clk_rate': clock.c:45: error: 'gd_t' has no member named 'plla_rate_hz' clock.c: In function 'get_pllb_clk_rate': clock.c:50: error: 'gd_t' has no member named 'pllb_rate_hz' clock.c: In function 'get_pllb_init': clock.c:55: error: 'gd_t' has no member named 'at91_pllb_usb_init' clock.c: In function 'at91_css_to_rate': clock.c:64: error: 'gd_t' has no member named 'main_clk_rate_hz' clock.c:66: error: 'gd_t' has no member named 'plla_rate_hz' clock.c:68: error: 'gd_t' has no member named 'pllb_rate_hz' clock.c: In function 'at91_clock_init': clock.c:167: error: 'gd_t' has no member named 'main_clk_rate_hz' clock.c:170: error: 'gd_t' has no member named 'plla_rate_hz' clock.c:179: error: 'gd_t' has no member named 'at91_pllb_usb_init' clock.c:181: error: 'gd_t' has no member named 'pllb_rate_hz' clock.c:181: error: 'gd_t' has no member named 'at91_pllb_usb_init' clock.c:193: error: 'gd_t' has no member named 'mck_rate_hz' clock.c:194: error: 'gd_t' has no member named 'mck_rate_hz' clock.c:212: error: 'gd_t' has no member named 'mck_rate_hz' clock.c:214: error: 'gd_t' has no member named 'cpu_clk_rate_hz' make[1]: *** [clock.o] Error 1 make[1]: Leaving directory `/data1/UBOOT/u-boot-2011.03/arch/arm/cpu/arm926ejs/at91' make: *** [arch/arm/cpu/arm926ejs/at91/libat91.o] Error 2 -- please help me in this regard. thanks in advance Regards, RAJEEV RAO BATTU R&D Engineer, ANALOGICS TECH INDIA LTD. Phone:9985144835. Tel: ++91-40-67355000, 2717 2672/2673/2674. http://www.analogicgroup.com

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[U-Boot] Question about mem parameter in the bootargs
by Carlos Roberto Moratelli 17 Aug '11

17 Aug '11

Hi, Does someone knows what is the smallest step to increase the mem parameter in the bootargs? I am dealing with an embedded system based on an ARM LPC3250 and running linux. I have a very critical memory constraint and I would like to have mem=3584k instead mem=3M or mem=4M. The Linux boot up sucessfull with mem=3M or mem=4M but the kernel crashes with mem=3584k. thank you Moratelli

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[U-Boot] [PATCH v6 1/2] gpio: Add GPIO driver framework for Marvell SoCs
by Ajay Bhargav 17 Aug '11

17 Aug '11

This patch adds generic GPIO driver framework support for Marvell SoCs. To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- Changes for v2: - mvgpio.h removed - function get_gpio_base moved to gpio.h - error messages added Changes for v3: - Added mvgpio.h for common define based on CPU core subversion. Changes for v4: - not changed Changes for v5: - Added change history Changes for v6: - Renamed GPIO level defines (fixes compilation issues thanks to Lei Wen) drivers/gpio/Makefile | 1 + drivers/gpio/mvgpio.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mvgpio.h | 77 +++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mvgpio.c create mode 100644 include/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 62ec97d..beca1da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c new file mode 100644 index 0000000..0cc8ed7 --- /dev/null +++ b/drivers/gpio/mvgpio.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +#ifndef MV_MAX_GPIO +#define MV_MAX_GPIO 128 +#endif + +int gpio_request(int gp, const char *label) +{ + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gp); + return -EINVAL; + } + return 0; +} + +void gpio_free(int gp) +{ +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + return 0; +} + +int gpio_direction_output(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); + gpio_set_value(gp, value); + return 0; +} + +int gpio_get_value(int gp) +{ + struct gpio_reg *gpio_reg_bank; + u32 gp_val; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gp_val = readl(&gpio_reg_bank->gplr); + + return GPIO_VAL(gp, gp_val); +} + +void gpio_set_value(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + else + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); +} diff --git a/include/mvgpio.h b/include/mvgpio.h new file mode 100644 index 0000000..8bc303b --- /dev/null +++ b/include/mvgpio.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MVGPIO_H__ +#define __MVGPIO_H__ + +#include <common.h> + +#define GPIO_LEVEL_SET 1 +#define GPIO_LEVEL_CLR 0 + +#ifdef CONFIG_SHEEVA_88SV331xV5 +/* + * GPIO Register map for SHEEVA 88SV331xV5 + */ +struct gpio_reg { + u32 gplr; /* Pin Level Register - 0x0000 */ + u32 pad0[2]; + u32 gpdr; /* Pin Direction Register - 0x000C */ + u32 pad1[2]; + u32 gpsr; /* Pin Output Set Register - 0x0018 */ + u32 pad2[2]; + u32 gpcr; /* Pin Output Clear Register - 0x0024 */ + u32 pad3[2]; + u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ + u32 pad4[2]; + u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ + u32 pad5[2]; + u32 gedr; /* Edge Detect Status Register - 0x0048 */ + u32 pad6[2]; + u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ + u32 pad7[2]; + u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ + u32 pad8[2]; + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable + Register - 0x006C */ + u32 pad9[2]; + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable + Register - 0x0078 */ + u32 pad10[2]; + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable + Register - 0x0084 */ + u32 pad11[2]; + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable + Register - 0x0090 */ + u32 pad12[2]; + u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ +}; +#else +#error "CPU core subversion not defined" +#endif + +#endif /* __MVGPIO_H__ */ -- 1.7.0.4

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17 Aug '11

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