July 2011 - U-Boot

Re: [U-Boot] [PATCH 1/4] gpio: Adds GPIO driver support for Armada100
by Ajay Bhargav 20 Jul '11

20 Jul '11

Hi Prafulla, > I checked datasheet and for most GPIOs, AF1 is given as GPIO but for few > its not, so adding a glue logic to check for specific GPIOs wont be a good idea. > That's the reason i thought its good to keep MFP out of this. Please give suggestions. correcting my previous message, I meant AF0. adding to this.. I checked Linux kernel source and they are simply validating if gpio number is within max limits so request returns 0. And you told me to use MAX_MFP instead of using ARMD_MAX_GPIO, but MAX_MFP is defined lesser than the actual number of GPIO e.g. in case of armada100 MAX_MFP is defined 117 whereas max GPIOs are around 123. Please give me some suggestion. Regards, Ajay Bhargav

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[U-Boot] [PATCH 1/4] gpio: Adds GPIO driver support for Armada100
by Ajay Bhargav 20 Jul '11

20 Jul '11

This patch adds generic GPIO driver framework support for Armada100 series. To enable GPIO driver define CONFIG_ARMADA100_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. NOTE: This driver assumes proper configuration of MFP register for the GPIO in use. These patches depends on patch series that adds support for Marvell Guruplug-Display [1,2]. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- arch/arm/include/asm/arch-armada100/gpio.h | 130 +++++++++++++++++++ drivers/gpio/Makefile | 1 + drivers/gpio/armada100_gpio.c | 192 ++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h create mode 100644 drivers/gpio/armada100_gpio.c diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h new file mode 100644 index 0000000..9024a2e --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/gpio.h @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2010 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#endif + +#if defined(CONFIG_ARMADA100_GPIO) +#include <asm/arch/armada100.h> + +#define GPIO_LABEL_MAX 20 +#define ARMD_MAX_GPIO 128 + +#define GPIO_TO_REG(gp) (gp >> 5) +#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) +#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) + +#define GPIO_SET 1 +#define GPIO_CLR 0 + +/* + * GPIO register map + * Refer Datasheet Appendix A.36 + */ +struct armdgpio_registers { + u32 gplr0; /* Pin Level Register - 0x0000 */ + u32 gplr1; /* 0x0004 */ + u32 gplr2; /* 0x0008 */ + u32 gpdr0; /* Pin Direction Register - 0x000C */ + u32 gpdr1; /* 0x0010 */ + u32 gpdr2; /* 0x0014 */ + u32 gpsr0; /* Pin Output Set Register - 0x0018 */ + u32 gpsr1; /* 0x001C */ + u32 gpsr2; /* 0x0020 */ + u32 gpcr0; /* Pin Output Clear Register - 0x0024 */ + u32 gpcr1; /* 0x0028 */ + u32 gpcr2; /* 0x002C */ + u32 grer0; /* Rising-Edge Detect Enable Register - 0x0030 */ + u32 grer1; /* 0x0034 */ + u32 grer2; /* 0x0038 */ + u32 gfer0; /* Falling-Edge Detect Enable Register - 0x003C */ + u32 gfer1; /* 0x0040 */ + u32 gfer2; /* 0x0044 */ + u32 gedr0; /* Edge Detect Status Register - 0x0048 */ + u32 gedr1; /* 0x004C */ + u32 gedr2; /* 0x0050 */ + u32 gsdr0; /* Bitwise Set of GPIO Direction Register - 0x0054 */ + u32 gsdr1; /* 0x0058 */ + u32 gsdr2; /* 0x005C */ + u32 gcdr0; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ + u32 gcdr1; /* 0x0064 */ + u32 gcdr2; /* 0x0068 */ + u32 gsrer0; /* Bitwise Set of Rising-Edge Detect Enable + Register - 0x006C */ + u32 gsrer1; /* 0x0070 */ + u32 gsrer2; /* 0x0074 */ + u32 gcrer0; /* Bitwise Clear of Rising-Edge Detect Enable + Register - 0x0078 */ + u32 gcrer1; /* 0x007C */ + u32 gcrer2; /* 0x0080 */ + u32 gsfer0; /* Bitwise Set of Falling-Edge Detect Enable + Register - 0x0084 */ + u32 gsfer1; /* 0x0088 */ + u32 gsfer2; /* 0x008C */ + u32 gcfer0; /* Bitwise Clear of Falling-Edge Detect Enable + Register - 0x0090 */ + u32 gcfer1; /* 0x0094 */ + u32 gcfer2; /* 0x0098 */ + u32 apmask0; /* Bitwise Mask of Edge Detect Register - 0x009C */ + u32 apmask1; /* 0x00A0 */ + u32 apmask2; /* 0x00A4 */ + u8 pad[0x0100 - 0x00A4 - 4]; + u32 gplr3; /* 0x0100 */ + u8 pad1[0x010C - 0x0100 - 4]; + u32 gpdr3; /* 0x010C */ + u8 pad2[0x0118 - 0x010C - 4]; + u32 gpsr3; /* 0x0118 */ + u8 pad3[0x0124 - 0x0118 - 4]; + u32 gpcr3; /* 0x0124 */ + u8 pad4[0x0130 - 0x0124 - 4]; + u32 grer3; /* 0x0130 */ + u8 pad5[0x013C - 0x0130 - 4]; + u32 gfer3; /* 0x013C */ + u8 pad6[0x0148 - 0x013C - 4]; + u32 gedr3; /* 0x0148 */ + u8 pad7[0x0154 - 0x0148 - 4]; + u32 gsdr3; /* 0x0154 */ + u8 pad8[0x0160 - 0x0154 - 4]; + u32 gcdr3; /* 0x0160 */ + u8 pad9[0x016C - 0x0160 - 4]; + u32 gsrer3; /* 0x016C */ + u8 pad10[0x0178 - 0x016C - 4]; + u32 gcrer3; /* 0x0178 */ + u8 pad11[0x0184 - 0x0178 - 4]; + u32 gsfer3; /* 0x0184 */ + u8 pad12[0x0190 - 0x0184 - 4]; + u32 gcfer3; /* 0x0190 */ + u8 pad13[0x019C - 0x0190 - 4]; + u32 apmask3; /* 0x019C */ +}; + +#endif /* CONFIG_ARMADA100_GPIO */ +#endif /* _ASM_ARCH_GPIO_H */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1e3ae11..31b83cd 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o +COBJS-$(CONFIG_ARMADA100_GPIO) += armada100_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o diff --git a/drivers/gpio/armada100_gpio.c b/drivers/gpio/armada100_gpio.c new file mode 100644 index 0000000..578fdac --- /dev/null +++ b/drivers/gpio/armada100_gpio.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2010 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +int gpio_request(int gp, const char *label) +{ + /* + * Assumes corresponding MFP is configured peoperly + * for use as GPIO + */ + return 0; +} + +void gpio_free(int gp) +{ + /* default direction for GPIO is input */ + gpio_direction_input(gp); +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + struct armdgpio_registers *gpio_regs = + (struct armdgpio_registers *)ARMD1_GPIO_BASE; + + if (gp < ARMD_MAX_GPIO) { + switch (GPIO_TO_REG(gp)) { + case 0: + writel(GPIO_TO_BIT(gp), &gpio_regs->gcdr0); + break; + case 1: + writel(GPIO_TO_BIT(gp), &gpio_regs->gcdr1); + break; + case 2: + writel(GPIO_TO_BIT(gp), &gpio_regs->gcdr2); + break; + case 3: + writel(GPIO_TO_BIT(gp), &gpio_regs->gcdr3); + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + return 0; +} + +int gpio_direction_output(int gp, int value) +{ + struct armdgpio_registers *gpio_regs = + (struct armdgpio_registers *)ARMD1_GPIO_BASE; + + if (gp < ARMD_MAX_GPIO) { + switch (GPIO_TO_REG(gp)) { + case 0: + writel(GPIO_TO_BIT(gp), &gpio_regs->gsdr0); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr0); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr0); + break; + case 1: + writel(GPIO_TO_BIT(gp), &gpio_regs->gsdr1); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr1); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr1); + break; + case 2: + writel(GPIO_TO_BIT(gp), &gpio_regs->gsdr2); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr2); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr2); + break; + case 3: + writel(GPIO_TO_BIT(gp), &gpio_regs->gsdr3); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr3); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr3); + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + return 0; +} + +int gpio_get_value(int gp) +{ + struct armdgpio_registers *gpio_regs = + (struct armdgpio_registers *)ARMD1_GPIO_BASE; + u32 gp_val; + + if (gp < ARMD_MAX_GPIO) { + switch (GPIO_TO_REG(gp)) { + case 0: + gp_val = readl(&gpio_regs->gplr0); + break; + case 1: + gp_val = readl(&gpio_regs->gplr1); + break; + case 2: + gp_val = readl(&gpio_regs->gplr2); + break; + case 3: + gp_val = readl(&gpio_regs->gplr3); + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + + return GPIO_VAL(gp, gp_val); +} + +void gpio_set_value(int gp, int value) +{ + struct armdgpio_registers *gpio_regs = + (struct armdgpio_registers *)ARMD1_GPIO_BASE; + + if (gp < ARMD_MAX_GPIO) { + switch (GPIO_TO_REG(gp)) { + case 0: + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr0); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr0); + break; + case 1: + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr1); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr1); + break; + case 2: + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr2); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr2); + break; + case 3: + if (value) + writel(GPIO_TO_BIT(gp), &gpio_regs->gpsr3); + else + writel(GPIO_TO_BIT(gp), &gpio_regs->gpcr3); + break; + default: + panic("Invalid GPIO pin %u\n", gp); + } + } else { + panic("Invalid GPIO pin %u\n", gp); + } +} -- 1.7.0.4

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[U-Boot] No gpio.h file
by Ajay Bhargav 20 Jul '11

20 Jul '11

Dear Wolfgang, There is no "asm/gpio.h" file available in U-Boot 2011.06 release. So generic gpio framework is being created now?? Regards, Ajay Bhargav

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[U-Boot] Please pull u-boot-mmc.git
by Andy Fleming 19 Jul '11

19 Jul '11

are available in the git repository at: git://www.denx.de/git/u-boot-mmc.git master Lei Wen (4): MMC: unify mmc read and write operation MMC: add erase function to both mmc and sd MMC: add sdhci generic framework MMC: add marvell sdhci driver Michael Jones (1): mmc: rescan fails on empty slot Tom Warren (2): mmc: Tegra2: SD/MMC driver for Seaboard - eMMC on SDMMC4, SDIO on SDMMC3 mmc: Tegra2: Enable SD/MMC driver for Seaboard and Harmony Yoshihiro Shimoda (2): mmc: fix the condition for MMC version 4 mmc: sh_mmcif: add support for Renesas MMCIF elen.song (1): AT91:mmc:fix multiple read/write error Łukasz Majewski (1): mmc: Access mode validation for eMMC cards > 2 GiB README | 9 + arch/arm/include/asm/arch-tegra2/clk_rst.h | 5 + arch/arm/include/asm/arch-tegra2/pinmux.h | 6 + board/nvidia/common/board.c | 147 +++++++ board/nvidia/common/board.h | 1 + common/cmd_mmc.c | 89 +++-- drivers/mmc/Makefile | 4 + drivers/mmc/atmel_mci.h | 9 +- drivers/mmc/gen_atmel_mci.c | 4 + drivers/mmc/mmc.c | 121 ++++++- drivers/mmc/mv_sdhci.c | 21 + drivers/mmc/s5p_mmc.c | 2 +- drivers/mmc/sdhci.c | 433 ++++++++++++++++++++ drivers/mmc/sh_mmcif.c | 608 ++++++++++++++++++++++++++++ drivers/mmc/sh_mmcif.h | 238 +++++++++++ drivers/mmc/tegra2_mmc.c | 510 +++++++++++++++++++++++ drivers/mmc/tegra2_mmc.h | 81 ++++ include/configs/harmony.h | 11 + include/configs/seaboard.h | 11 + include/mmc.h | 9 + include/part.h | 3 + include/sdhci.h | 325 +++++++++++++++ 22 files changed, 2606 insertions(+), 41 deletions(-) create mode 100644 drivers/mmc/mv_sdhci.c create mode 100644 drivers/mmc/sdhci.c create mode 100644 drivers/mmc/sh_mmcif.c create mode 100644 drivers/mmc/sh_mmcif.h create mode 100644 drivers/mmc/tegra2_mmc.c create mode 100644 drivers/mmc/tegra2_mmc.h create mode 100644 include/sdhci.h

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[U-Boot] (no subject)
by SURESH FINANCE 19 Jul '11

19 Jul '11

DO YOU NEED A LOAN? IF YES , REPLY US FOR MORE DETAILS.THANKS.

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[U-Boot] Critical Error ***Help Desk*** >>>
by Margaret Hill 19 Jul '11

19 Jul '11

Dear User, You have exceeded the limit of your mailbox set by your IT service provider, you will be unable to receive new emails and sent successfully. Just before this message was sent, you are Currently running on 91624 KB, You have has exceeded the storage limit which is 20GB. To prevent this, please click to reset your account. CLICK HERE<https://spreadsheets.google.com/spreadsheet/viewform?formkey=dHdZbW5LLV9BSV…> Thanks Administrator.

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[U-Boot] NAND onfi detection
by Vipin Kumar 19 Jul '11

19 Jul '11

Hello Scott, The present handling of ONFI devices requires that the device id to be put in "nand_flash_ids" table. I am pasting the code below to ease the discussion In case the dev_id doesn't match with the one's present in the table type->name points to null and an error -ENODEV is returned. detect onfi is never called if (!type) type = nand_flash_ids; for (; type->name != NULL; type++) if (*dev_id == type->id) break; if (!type->name) { /* supress warning if there is no nand */ if (*maf_id != 0x00 && *maf_id != 0xff && *dev_id != 0x00 && *dev_id != 0xff) printk(KERN_INFO "%s: unknown NAND device: " "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", __func__, *maf_id, *dev_id); return ERR_PTR(-ENODEV); } if (!mtd->name) mtd->name = type->name; chip->chipsize = (uint64_t)type->chipsize << 20; chip->onfi_version = 0; ret = nand_flash_detect_onfi(mtd, chip, &busw); if (!ret) nand_flash_detect_non_onfi(mtd, chip, type, &busw); Is the behavior expected ? Am I missing something Regards Vipin

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[U-Boot] [PATCH 4/4] Armada100: Enable Ethernet support for GplugD
by Ajay Bhargav 19 Jul '11

19 Jul '11

This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- arch/arm/include/asm/arch-armada100/armada100.h | 57 +++++++++++++++++++++++ arch/arm/include/asm/arch-armada100/mfp.h | 19 ++++++++ board/Marvell/gplugd/gplugd.c | 38 +++++++++++++++ include/configs/gplugd.h | 19 +++++++- 4 files changed, 131 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index 3d567eb..849638d 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -41,6 +41,10 @@ /* Functional Clock Selection Mask */ #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) +/* Fast Ethernet Controller Clock register definition */ +#define FE_CLK_RST 0x1 +#define FE_CLK_ENA 0x8 + /* Register Base Addresses */ #define ARMD1_DRAM_BASE 0xB0000000 #define ARMD1_TIMER_BASE 0xD4014000 @@ -85,6 +89,59 @@ struct armd1mpmu_registers { }; /* + * Application Subsystem Power Management + * Refer Datasheet Appendix A.9 + */ +struct armd1apmu_registers { + u32 pcr; /* 0x000 */ + u32 ccr; /* 0x004 */ + u32 pad1; + u32 ccsr; /* 0x00C */ + u32 fc_timer; /* 0x010 */ + u32 pad2; + u32 ideal_cfg; /* 0x018 */ + u8 pad3[0x04C - 0x018 - 4]; + u32 lcdcrc; /* 0x04C */ + u32 cciccrc; /* 0x050 */ + u32 sd1crc; /* 0x054 */ + u32 sd2crc; /* 0x058 */ + u32 usbcrc; /* 0x05C */ + u32 nfccrc; /* 0x060 */ + u32 dmacrc; /* 0x064 */ + u32 pad4; + u32 buscrc; /* 0x06C */ + u8 pad5[0x07C - 0x06C - 4]; + u32 wake_clr; /* 0x07C */ + u8 pad6[0x090 - 0x07C - 4]; + u32 core_status; /* 0x090 */ + u32 rfsc; /* 0x094 */ + u32 imr; /* 0x098 */ + u32 irwc; /* 0x09C */ + u32 isr; /* 0x0A0 */ + u8 pad7[0x0B0 - 0x0A0 - 4]; + u32 mhst; /* 0x0B0 */ + u32 msr; /* 0x0B4 */ + u8 pad8[0x0C0 - 0x0B4 - 4]; + u32 msst; /* 0x0C0 */ + u32 pllss; /* 0x0C4 */ + u32 smb; /* 0x0C8 */ + u32 gccrc; /* 0x0CC */ + u8 pad9[0x0D4 - 0x0CC - 4]; + u32 smccrc; /* 0x0D4 */ + u32 pad10; + u32 xdcrc; /* 0x0DC */ + u32 sd3crc; /* 0x0E0 */ + u32 sd4crc; /* 0x0E4 */ + u8 pad11[0x0F0 - 0x0E4 - 4]; + u32 cfcrc; /* 0x0F0 */ + u32 mspcrc; /* 0x0F4 */ + u32 cmucrc; /* 0x0F8 */ + u32 fecrc; /* 0x0FC */ + u32 pciecrc; /* 0x100 */ + u32 epdcrc; /* 0x104 */ +}; + +/* * APB1 Clock Reset/Control Registers * Refer Datasheet Appendix A.10 */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d6e0494..da76b58 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -64,6 +64,25 @@ #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +/* Fast Ethernet */ +#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) +#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) + /* More macros can be defined here... */ #define MFP_PIN_MAX 117 diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index 347a689..f446d92 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -35,6 +35,11 @@ #include <asm/gpio.h> #include <miiphy.h> +#ifdef CONFIG_ARMADA100_FEC +#include <net.h> +#include <netdev.h> +#endif /* CONFIG_ARMADA100_FEC */ + DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) @@ -47,6 +52,26 @@ int board_early_init_f(void) /* Enable Console on UART3 */ MFPO8_UART3_TXD, MFPO9_UART3_RXD, + + /* Ethernet PHY Interface */ + MFP086_ETH_TXCLK, + MFP087_ETH_TXEN, + MFP088_ETH_TXDQ3, + MFP089_ETH_TXDQ2, + MFP090_ETH_TXDQ1, + MFP091_ETH_TXDQ0, + MFP092_ETH_CRS, + MFP093_ETH_COL, + MFP094_ETH_RXCLK, + MFP095_ETH_RXER, + MFP096_ETH_RXDQ3, + MFP097_ETH_RXDQ2, + MFP098_ETH_RXDQ1, + MFP099_ETH_RXDQ0, + MFP100_ETH_MDC, + MFP101_ETH_MDIO, + MFP103_ETH_RXDV, + MFP_EOC /*End of configuration*/ }; /* configure MFP's */ @@ -69,6 +94,19 @@ int board_init(void) return 0; } +#ifdef CONFIG_ARMADA100_FEC +int board_eth_init(bd_t *bis) +{ + struct armd1apmu_registers *apmu_regs = + (struct armd1apmu_registers *) ARMD1_APMU_BASE; + + /* Enable clock of ethernet controller */ + writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); + + return armada100_fec_initialize(); +} +#endif /* CONFIG_ARMADA100_FEC */ + #ifdef CONFIG_RESET_PHY_R /* Configure and initialize PHY chip 88E3015 */ void reset_phy(void) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 412c959..aa8fda1 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -62,12 +62,13 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS /* GPIO Support */ #define CONFIG_ARMADA100_GPIO +/* Disable DCACHE */ +#define CONFIG_SYS_DCACHE_OFF + /* PHY configuration */ #define CONFIG_MII #define CONFIG_CMD_MII @@ -79,6 +80,20 @@ /* GPIO Configuration for PHY */ #define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ +/* Network configuration */ +#define CONFIG_CMD_PING +#define CONFIG_NET_MULTI +#define CONFIG_ARMADA100_FEC + +/* DHCP Support */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_BOOTP_SERVERIP + +/* Default Boot Parameters */ +#define CONFIG_ROOTPATH "/tftpboot" +#define CONFIG_SYS_IMG_NAME "uImage" + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 1.7.0.4

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[U-Boot] [PATCH 3/4] Armada100: Enable 88E3015 PHY support for GplugD
by Ajay Bhargav 19 Jul '11

19 Jul '11

This patch adds support for 88E3015 PHY for Marvell GplugD board. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- board/Marvell/gplugd/gplugd.c | 35 +++++++++++++++++++++++++++++++++++ include/configs/gplugd.h | 14 ++++++++++++++ 2 files changed, 49 insertions(+), 0 deletions(-) diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index dc7d89d..347a689 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -32,6 +32,8 @@ #include <mvmfp.h> #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> +#include <asm/gpio.h> +#include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,6 +51,7 @@ int board_early_init_f(void) }; /* configure MFP's */ mfp_config(mfp_cfg); + return 0; } @@ -58,5 +61,37 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; /* adress of boot parameters */ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; + /* Assert PHY_RST# */ + gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_CLR); + udelay(10); + /* Deassert PHY_RST# */ + gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_SET); return 0; } + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY chip 88E3015 */ +void reset_phy(void) +{ + u16 phy_adr; + const char *name = "armd-fec0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* Set Ethernet LED in TX blink mode */ + miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); + miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); + + /* reset the phy */ + miiphy_reset(name, phy_adr); + printf("88E3015 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index cc14f49..412c959 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -65,6 +65,20 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +/* GPIO Support */ +#define CONFIG_ARMADA100_GPIO + +/* PHY configuration */ +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_RESET_PHY_R +/* 88E3015 register definition */ +#define PHY_LED_PAR_SEL_REG 22 +#define PHY_LED_MAN_REG 25 +#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ +/* GPIO Configuration for PHY */ +#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 1.7.0.4

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[U-Boot] Greeting From Miss Sarah Kipkalya!!
by Sarah Kipkalya 19 Jul '11

19 Jul '11

Greeting From Miss Sarah Kipkalya!! My Dearest One, I am writing this mail to you with tears and sorrow from my heart. With due respect, trust and humanity, i appeal to you to exercise a little patience and read through my letter, I wish to contact you personally for a long term business relationship and investment assistance in your Country so i feel quite safe dealing with you in this important business having gone through your remarkable profile, honestly i am writing this email to you with pains, tears and sorrow from my heart, i will really like to have a good relationship with you and i have a special reason why i decided to contact you, i decided to contact you due to the urgency of my situation, My name is Miss Sarah Kipkalya Kones, 23yrs old female and I held from Kenya in East Africa. My father was the former Kenyan road Minister. He and Assistant Minister of Home Affairs Lorna Laboso had been on board the Cessna 210, which was headed to Kericho and crashed in a remote area called Kajong'a, in western Kenya. The plane crashed on the Tuesday 10th, June, 2008. You can read more about the crash through the below site: http://edition.cnn.com/2008/WORLD/africa/06/10/kenya.crash/index.html After the burial of my father, my stepmother and uncle conspired and sold my father's property to an Italian Expert rate which the shared the money among themselves and live nothing for me. I am constrained to contact you because of the abuse I am receiving from my wicked stepmother and uncle. They planned to take away all my late father's treasury and properties from me since the unexpected death of my beloved Father. Meanwhile i wanted to escape to the USA but they hide away my international passport and other valuable travelling documents. Luckily they did not discover where i kept my fathers File which contains important documents. So I decided to run to the refugee camp where i am presently seeking asylum under the United Nations High Commission for the Refugee here in Ouagadougou, Republic of Burkina Faso. One faithful morning, I opened my father's briefcase and found out the documents which he has deposited huge amount of money in bank in Burkina Faso with my name as the next of kin. I travelled to Burkina Faso to withdraw the money for a better life so that I can take care of myself and start a new life, on my arrival, the Bank Director whom I met in person told me that my father's instruction/will to the bank is that the money would only be release to me when I am married or present a trustee who will help me and invest the money overseas. I am in search of an honest and reliable person who will help me and stand as my trustee so that I will present him to the Bank for transfer of the money to his bank account overseas. I have chosen to contact you after my prayers and I believe that you will not betray my trust. But rather take me as your own sister. Although, you may wonder why I am so soon revealing myself to you without knowing you, well I will say that my mind convince Ed me that you may be the true person to help me. More so, my father of blessed memory deposited the sum of (US$11.500, 000) Dollars in Bank with my name as the next of kin. However, I shall forward you with the necessary documents on confirmation of your acceptance to assist me for the transfer and statement of the fund in your country. As you will help me in an investment, and i will like to complete my studies, as i was in my 1year in the university when my beloved father died. It is my intention to compensate you with 30% of the total money for your services and the balance shall be my capital in your establishment. As soon as I receive your positive response showing your interest I will put things into action immediately. In the light of the above. I shall appreciate an urgent message indicating your ability and willingness to handle this transaction sincerely. AWAITING YOUR URGENT AND POSITIVE RESPONSE, Please do keep this only to your self for now un till the bank will transfer the fund. I beg you not to disclose it till i come over because I am afraid of my wicked stepmother who has threatened to kill me and have the money alone ,I thank God Today that am out from my country (KENYA) but now In (Burkina Faso) where my father deposited these money with my name as the next of Kin. I have the documents for the claims. Yours Sincerely Miss Sarah Kipkalya Kones.

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