July 2011 - U-Boot

[U-Boot] [PATCH 2/2] [v3] powerpc/85xx: add support the ePAPR "phandle" property
by Timur Tabi 22 Jul '11

22 Jul '11

The ePAPR specification says that phandle properties should be called "phandle", and not "linux,phandle". To facilitate the migration from "linux,phandle" to "phandle", we update fdt_qportal() to use the new function, fdt_create_phandle(). This function abstracts the creation of phandle properties. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/portals.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index c014163..ecaa30d 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -151,8 +151,10 @@ static int fdt_qportal(void *blob, int off, int id, char *name, dev_handle = fdt_get_phandle(blob, dev_off); if (dev_handle <= 0) { dev_handle = fdt_alloc_phandle(blob); - fdt_setprop_cell(blob, dev_off, - "linux,phandle", dev_handle); + ret = fdt_create_phandle(blob, dev_off, + dev_handle); + if (ret < 0) + return ret; } ret = fdt_setprop(blob, childoff, "dev-handle", -- 1.7.3.4

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[U-Boot] [PATCH 1/2] fdt: add prototype for fdt_increase_size()
by Timur Tabi 22 Jul '11

22 Jul '11

Add a prototype for fdt_increase_size() so that anyone can call it. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/fdt_support.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/fdt_support.h b/include/fdt_support.h index ce6817b..7333c0c 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -79,6 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd); void set_working_fdt_addr(void *addr); int fdt_resize(void *blob); +int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); -- 1.7.3.4

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[U-Boot] [PATCH 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
by Ajay Bhargav 22 Jul '11

22 Jul '11

This patch adds support for generic GPIO driver framework for Marvell SoC Armada100. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- arch/arm/include/asm/arch-armada100/gpio.h | 71 ++++++++++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h new file mode 100644 index 0000000..4dd0179 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/gpio.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +#include <mvgpio.h> + +/* + * GPIO register map + * Refer Datasheet Appendix A.36 + */ +struct gpio_reg { + u32 gplr; /* Pin Level Register */ + u32 pad0[2]; + u32 gpdr; /* Pin Direction Register */ + u32 pad1[2]; + u32 gpsr; /* Pin Output Set Register */ + u32 pad2[2]; + u32 gpcr; /* Pin Output Clear Register */ + u32 pad3[2]; + u32 grer; /* Rising-Edge Detect Enable Register */ + u32 pad4[2]; + u32 gfer; /* Falling-Edge Detect Enable Register */ + u32 pad5[2]; + u32 gedr; /* Edge Detect Status Register */ + u32 pad6[2]; + u32 gsdr; /* Bitwise Set of GPIO Direction Register */ + u32 pad7[2]; + u32 gcdr; /* Bitwise Clear of GPIO Direction Register */ + u32 pad8[2]; + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable + Register */ + u32 pad9[2]; + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable + Register */ + u32 pad10[2]; + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable + Register */ + u32 pad11[2]; + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable + Register */ + u32 pad12[2]; + u32 apmask; /* Bitwise Mask of Edge Detect Register */ +}; + +#endif /* _ASM_ARCH_GPIO_H */ -- 1.7.0.4

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Re: [U-Boot] No gpio.h file
by Ajay Bhargav 22 Jul '11

22 Jul '11

----- "Prafulla Wadaskar" <prafulla(a)marvell.com> wrote: > Done.. > Please re-sync you patches to latest u-boot-marvell.git master > branch. > > Regards.. > Prafulla . . > Hi Prafulla, Thanks for update. I do not see the first set of patches that adds support for gplugD. Regards, Ajay Bhargav

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[U-Boot] [PATCH] ppc460: read get_sys_info from CPR registers instead of STRP registers
by Mike Williams 21 Jul '11

21 Jul '11

This code has been changed to read the CPU speed information from the CPR registers rather than the bootstrap registers. This is useful when changing the clock speed to something other than the default on boot. Signed-off-by: Mike Williams <mike(a)mikebwilliams.com> --- arch/powerpc/cpu/ppc4xx/speed.c | 33 +++++++++++++------------------ arch/powerpc/include/asm/ppc460ex_gt.h | 15 +++++++++++++- 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 09d6671..2643fc0 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -328,38 +328,33 @@ void get_sys_info(sys_info_t *sysInfo) */ void get_sys_info (sys_info_t * sysInfo) { - unsigned long strp0; - unsigned long strp1; + unsigned long pllc, plld, plbed, opbd, perd; unsigned long temp; unsigned long m; unsigned long plbedv0; /* Extract configured divisors */ - mfsdr(SDR0_SDSTP0, strp0); - mfsdr(SDR0_SDSTP1, strp1); - - temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK); - sysInfo->pllFwdDivB = get_cpr0_fwdv(temp); - temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8; - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + mfcpr(CPR0_PLLD, plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv((plld & PLLD_FWDVA_MASK) >> 16); + sysInfo->pllFwdDivB = get_cpr0_fwdv((plld & PLLD_FWDVB_MASK) >> 8); + sysInfo->pllFbkDiv = get_cpr0_fbdv((plld & PLLD_FBDV_MASK) >> 24); - temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26; + mfcpr(CPR0_OPBD0, opbd); + temp = ((opbd & OPBDV_MASK) >> 24); sysInfo->pllOpbDiv = temp ? temp : 4; - /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */ - temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24; + mfcpr(CPR0_PERD, perd); + temp = ((perd & PERDV_MASK) >> 24); sysInfo->pllExtBusDiv = temp ? temp : 4; - temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29; - plbedv0 = temp ? temp: 8; + mfcpr(CPR0_PLBED, plbed); + temp = ((plbed & PLBEDDV_MASK) >> 24); + plbedv0 = temp ? temp : 8; /* Calculate 'M' based on feedback source */ - temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; - if (temp == 0) { + mfcpr(CPR0_PLLC, pllc); + if (((pllc & PLLC_FBSEL_MASK) >> 24) == 0) { /* PLL internal feedback */ m = sysInfo->pllFbkDiv; } else { diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index 732fcac..25954b9 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -211,11 +211,24 @@ #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ -#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_PLBED 0x00000080 /* PLL PLB Ealry Clock Divider */ + +#define CPR0_ICFG_RLI_MASK 0x80000000 /* CPR Reset Load Inhibit */ #define CPR0_PLLC_RST 0x80000000 #define CPR0_PLLC_ENG 0x40000000 +#define PLLC_FBSEL_MASK 0x03000000 /* PLLC Feedback Selection */ + +#define PLLD_FBDV_MASK 0xff000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ + +#define PLBEDDV_MASK 0x07000000 /* PLB Early Divisor */ +#define OPBDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x03000000 /* Periferal Clock Divisor */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) -- 1.7.3.4

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[U-Boot] hello dear
by Jenefer Odily 21 Jul '11

21 Jul '11

Hello I am called jenefer I saw your profile today and found you worthy to be mine as some one whom i can lay on his arms as long as love is concern, caring and teassing you all the night long, If you are interested in knowing more about and for me to send you some pictures of mine my contact thus:(jeneferodily20082@yahoo.com)awaiting to hear from you. please contact through my email address because i don't have full access to this site.Loving you forver Jenefer

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[U-Boot] Highly Confidential For You...
by MRS.ASEHUI YU-PING 21 Jul '11

21 Jul '11

-- Dear Friend, its about a customer that came to S.C.Bank to engage in Private Banking services,the customer had a financial portfolio of $21.5m USD and this I help turned over in the purchase of securities in the capital markets.I was the bank adviser assisting the customer in the management of the funds. I have proposal for you as a matter of urgency to late Mr.Eric Morgan from United Kingdom,who died along side with his wife and their only daughter in the event,Terrorist Attack on 11th September,2001 in the world trade center.My proposition is that,I am prepared to place you in a position and instruct my Bank to release the deposit to you as the closest surviving relation.If you find yourself able to work with me in this transaction,do contact my private.E-mail:aud_asehui.yuping_01@hotmail.com If you give me positive signals,I will initiate this process towards conclusion. Regards, Mrs.Yu-ping.

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[U-Boot] Your Batch No: 2011/19803/CMT
by Microsoft Corporations 21 Jul '11

21 Jul '11

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Re: [U-Boot] [PATCH 1/2] gpio: Add GPIO driver framework for Marvell SoCs
by Ajay Bhargav 21 Jul '11

21 Jul '11

Hi Lei, > Please put this get_gpio_base into arch's self directory, since > different soc may have > different number of banks. For example, mmp3 has 6 banks. > Can I declare get_gpio_base in arch's gpio.h file as static inline? so other archs can have their own version in their respective gpio.h file. Regards, Ajay Bhargav

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[U-Boot] [PATCH] a/a/c/arm920t/at91/reset.c: drop obsolete CONFIG_AT91RM9200_USART
by Andreas Bießmann 21 Jul '11

21 Jul '11

The CONFIG_AT91RM9200_USART is an remnant of 18ed5e9550810e2fc5bf2c757aee47774609651c which deleted the at91rm9200_usart driver. Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- arch/arm/cpu/arm920t/at91/reset.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c index 4fa0f98..cd9c9f3 100644 --- a/arch/arm/cpu/arm920t/at91/reset.c +++ b/arch/arm/cpu/arm920t/at91/reset.c @@ -43,10 +43,6 @@ void __attribute__((weak)) board_reset(void) void reset_cpu(ulong ignored) { at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST; -#if defined(CONFIG_AT91RM9200_USART) - /*shutdown the console to avoid strange chars during reset */ - serial_exit(); -#endif board_reset(); -- 1.7.6

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