April 2011 - U-Boot

[U-Boot] I never forget you
by Ahmed Zongrana 09 Apr '11

09 Apr '11

I never forget you Contact my secretary for your compensation sum of 500,000.00Euro here is his email id mariamphiliip1(a)voila.fr Mr. Ahmed Zongrana

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Re: [U-Boot] [PATCH] arm/km: change default settings for egiga on mgcoge3un
by Prafulla Wadaskar 09 Apr '11

09 Apr '11

> -----Original Message----- > From: Valentin Longchamp [mailto:valentin.longchamp@keymile.com] > Sent: Friday, April 08, 2011 6:18 PM > To: u-boot(a)lists.denx.de > Cc: holger.brunck(a)keymile.com; hs(a)denx.de; Wolfgang Denk; Detlev Zundel; > Prafulla Wadaskar; Valentin Longchamp > Subject: [PATCH] arm/km: change default settings for egiga on mgcoge3un > > From: Holger Brunck <holger.brunck(a)keymile.com> > > The reason we need this is that we have the gig port on mgcoge3un > connected using a back-to-back pair of PHYs. There are no magnetics and > because of that the port has to be run with a fixd configuration and > auto-negotiation must be disabled. In the default mode the egiga driver > uses autoneg to determine port speed - which defaults to 1G (we need > 100M full duplex). > > Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> > Acked-by: Heiko Schocher <hs(a)denx.de> > cc: Wolfgang Denk <wd(a)denx.de> > cc: Detlev Zundel <dzu(a)denx.de> > cc: Prafulla Wadaskar <prafulla(a)marvell.com> > cc: Valentin Longchamp <valentin.longchamp(a)keymile.com> > Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> > --- > drivers/net/mvgbe.h | 2 ++ > include/configs/mgcoge3un.h | 25 +++++++++++++++++++++++++ > 2 files changed, 27 insertions(+), 0 deletions(-) > > diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h > index 3de98d0..d8a5429 100644 > --- a/drivers/net/mvgbe.h > +++ b/drivers/net/mvgbe.h > @@ -84,6 +84,7 @@ > MVGBE_TX_BURST_SIZE_16_64BIT) > > /* Default port serial control value */ > +#ifndef PORT_SERIAL_CONTROL_VALUE > #define PORT_SERIAL_CONTROL_VALUE ( \ > MVGBE_FORCE_LINK_PASS | \ > MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ > @@ -101,6 +102,7 @@ > MVGBE_CLR_EXT_LOOPBACK | \ > MVGBE_SET_FULL_DUPLEX_MODE | \ > MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) > +#endif > > /* Tx WRR confoguration macros */ > #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ > diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h > index da5935b..c7f9056 100644 > --- a/include/configs/mgcoge3un.h > +++ b/include/configs/mgcoge3un.h > @@ -48,6 +48,31 @@ > #define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ > > /* > + * mgcoge3un has a fixed link to the marvell switch > + * with 100MB full duplex and autoneg off, for this > + * reason we have to change the default settings > + */ > +#define PORT_SERIAL_CONTROL_VALUE ( \ > + MVGBE_FORCE_LINK_PASS | \ > + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ > + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ > + MVGBE_ADV_NO_FLOW_CTRL | \ > + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ > + MVGBE_FORCE_BP_MODE_NO_JAM | \ > + (1 << 9) /* Reserved bit has to be 1 */ | \ > + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ > + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ > + MVGBE_DTE_ADV_0 | \ > + MVGBE_MIIPHY_MAC_MODE | \ > + MVGBE_AUTO_NEG_NO_CHANGE | \ > + MVGBE_MAX_RX_PACKET_1552BYTE | \ > + MVGBE_CLR_EXT_LOOPBACK | \ > + MVGBE_SET_FULL_DUPLEX_MODE | \ > + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ > + MVGBE_SET_GMII_SPEED_TO_10_100 |\ > + MVGBE_SET_MII_SPEED_TO_100) > + > +/* > * Default environment variables > */ > #define CONFIG_EXTRA_ENV_SETTINGS Acked-by: Prafulla Wadaskar <Prafulla(a)marvell.com> Regards.. Prafulla . . \ > -- > 1.7.0.5

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[U-Boot] "YOUR EMAIL I ,D WON £1,000,000.00.GBP"
by Mrs.Elizabeth James 09 Apr '11

09 Apr '11

ATTENTION WINNER, Contact Mr.James Richard Esq,For the sum of £1,000,000.00.GBP in EuroMillions Lottery Promo Award 2011. Cliams Information 1.Full Names: 2.Sex: 3.Age: 4Address: 5.Telephone Number

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[U-Boot] u-boot and 2nd level usb hub
by Kallol Biswas 08 Apr '11

08 Apr '11

Hi, We have a system with a 2nd level USB hub. It seems that uboot does not discover devices beyond 1st level hub. If this is true, is there any patch that will discover devices behind multiple levels of hub? The linux kernel is able to detect and configure devices that are behind 2nd level hub. Kallol

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[U-Boot] [RFC] mpc83xx: add config options to spd_sdram
by Andre Schwarz 08 Apr '11

08 Apr '11

Kim, I have made some mods to spd_sdram.c for various reason: 1. use SPD setup also for soldered RAM. This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing. 2. read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage. Due to HRCW being being located at offset 0 we need an SPD data offset. 3. for optimized signal integrity and power consumption we need more influence on the on-die termination. Although the assumed default values are working they are far from ideal. 4. CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific. I have taken care not to increase code size and not to break existing boards. Any comments from your side ? Is this something you might ACK ? Regards, André diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 44aaa9a..7d10c8c 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -68,6 +68,12 @@ void board_add_ram_info(int use_default) #ifndef CONFIG_SYS_READ_SPD #define CONFIG_SYS_READ_SPD i2c_read #endif +#ifndef SPD_EEPROM_OFFSET +#define SPD_EEPROM_OFFSET 0 +#endif +#ifndef SPD_EEPROM_ADDR_LEN +#define SPD_EEPROM_ADDR_LEN 1 +#endif /* * Convert picoseconds into clock cycles (rounding up if needed). @@ -160,7 +166,8 @@ long int spd_sdram() isync(); /* Read SPD parameters with I2C */ - CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, + SPD_EEPROM_ADDR_LEN, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif @@ -562,6 +569,9 @@ long int spd_sdram() * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. */ wr_data_delay = 2; +#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY + wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY; +#endif /* * Write Latency @@ -601,6 +611,9 @@ long int spd_sdram() */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { +#ifdef CONFIG_SYS_DDR_CPO + cpo = CONFIG_SYS_DDR_CPO; +#else if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ } else if (effective_data_rate == 333) { @@ -611,6 +624,7 @@ long int spd_sdram() /* Automatic calibration */ cpo = 0x1f; } +#endif } ddr->timing_cfg_2 = (0 @@ -673,12 +687,23 @@ long int spd_sdram() * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. */ +#if defined(CONFIG_SYS_DDR_MODE_ODT_OFF) + mode_odt_enable = 0x00; /* disabled */ +#elif defined(CONFIG_SYS_DDR_MODE_ODT_50) + mode_odt_enable = 0x44; /* 50 Ohm */ +#elif defined(CONFIG_SYS_DDR_MODE_ODT_75) + mode_odt_enable = 0x04; /* 75 Ohm */ +#else mode_odt_enable = 0x40; /* 150 Ohm */ +#endif } ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ +#ifdef CONFIG_SYS_DDR_MODE_WEAK + | (1 << (16 + 1)) /* weak driver (~60%) */ +#endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ @@ -740,6 +765,9 @@ long int spd_sdram() odt_cfg = 0x2; /* ODT to IOs during reads */ } #endif +#ifdef CONFIG_ALWAYS_ASSERT_ODT_TO_CPU + odt_cfg = 0x3; /* ODT always on */ +#endif if (spd.mem_type == SPD_MEMTYPE_DDR2) { ddr->sdram_cfg2 = (0 | (0 << 26) /* True DQS */ @@ -779,10 +807,12 @@ long int spd_sdram() sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2; sdram_cfg = (0 - | SDRAM_CFG_MEM_EN /* DDR enable */ | SDRAM_CFG_SREN /* Self refresh */ | sdram_type /* SDRAM type */ ); +#ifdef CONFIG_DDR_HALF_STRENGTH + sdram_cfg |= SDRAM_CFG_HSE; +#endif /* sdram_cfg[3] = RD_EN - registered DIMM enable */ if (spd.mod_attr & 0x02) @@ -822,6 +852,7 @@ long int spd_sdram() */ sdram_cfg |= SDRAM_CFG_2T_EN; #endif + sdram_cfg |= SDRAM_CFG_MEM_EN; /* Enable controller, and GO! */ ddr->sdram_cfg = sdram_cfg; asm("sync;isync"); MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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[U-Boot] get ram size/end in env var
by Fabian Cenedese 08 Apr '11

08 Apr '11

Hi I want to add in my board's config header an environment command that needs the ram end address (or ram size as ram starts at 0). As the sdram size can differ I'd like to get it at runtime and then jump there with the "go" command (minus some offset). How could I do that? Thanks bye Fabi

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[U-Boot] [PATCH v2 0/6] Universal PHY Infrastructure
by Andy Fleming 08 Apr '11

08 Apr '11

Or PHY Lib for U-Boot. This sequence of patches adds infrastructure for universally-available PHY drivers (and MDIO drivers). It piggy-backs on the existing miiphy code, for backwards compatibility, but it also creates a new set of APIs. This was necessary partly to provide cleaner interfaces for more robust driver support, and partly because one goal was to support 10G (802.3 Clause 45) MDIO buses, which has an extra argument for addressing PHY registers. The first three patches clear the way, and are in this sequence mostly because the tsec changes depend on them. Special thanks goes to Mingkai Hu, who did a substantial amount of work up front to convert the tsec PHY code into something more usable, which I have mostly copied for the purposes of PHY Lib. As the subject says, these are submitted here for comment. I hope they will go in for the presumptive June release. This second version cleans up all checkpatch errors that I reasonably could, and addresses most of the comments from the first round of reviews. I have removed the mdio command patch, as I want to rework it a bit, and it's not currently necessary unless you want to interact with a 10G PHY from the command line. I should submit a new version of that, soon. I also got Kumar to remove the tsec patches I reworked slightly from his tree, so that these can go in without conflict. Andy Fleming (4): Remove instances of phy_read/write Create PHY Lib for U-Boot phylib: Add a bunch of PHY drivers from tsec tsec: Convert tsec to use PHY Lib Mingkai Hu (2): tsec: use IO accessors for IO accesses tsec: arrange the code to avoid useless function declaration arch/powerpc/include/asm/config.h | 7 + arch/powerpc/include/asm/fsl_enet.h | 10 + board/freescale/mpc837xemds/mpc837xemds.c | 7 + board/freescale/mpc8536ds/mpc8536ds.c | 6 + board/freescale/mpc8544ds/mpc8544ds.c | 30 + board/freescale/mpc8572ds/mpc8572ds.c | 6 + board/freescale/p1022ds/p1022ds.c | 6 + board/freescale/p1_p2_rdb/p1_p2_rdb.c | 6 + board/freescale/p2020ds/p2020ds.c | 7 + common/Makefile | 1 + common/miiphyutil.c | 308 +++-- drivers/net/Makefile | 2 +- drivers/net/dm9000x.c | 18 +- drivers/net/enc28j60.c | 24 +- drivers/net/fsl_mdio.c | 120 ++ drivers/net/phy/Makefile | 12 + drivers/net/phy/atheros.c | 48 + drivers/net/phy/broadcom.c | 286 +++++ drivers/net/phy/davicom.c | 98 ++ drivers/net/phy/lxt.c | 87 ++ drivers/net/phy/marvell.c | 376 ++++++ drivers/net/phy/micrel.c | 40 + drivers/net/phy/natsemi.c | 96 ++ drivers/net/phy/phy.c | 750 +++++++++++ drivers/net/phy/realtek.c | 130 ++ drivers/net/phy/teranetics.c | 54 + drivers/net/phy/vitesse.c | 242 ++++ drivers/net/tsec.c | 1992 ++++------------------------- drivers/net/uli526x.c | 24 +- drivers/qe/uec.c | 3 - drivers/qe/uec_phy.c | 145 ++- include/fsl_mdio.h | 62 + include/miiphy.h | 67 +- include/phy.h | 500 ++++++++ include/phylib_all_drivers.h | 25 + include/tsec.h | 302 +---- net/eth.c | 6 + 37 files changed, 3693 insertions(+), 2210 deletions(-) create mode 100644 drivers/net/fsl_mdio.c create mode 100644 drivers/net/phy/atheros.c create mode 100644 drivers/net/phy/broadcom.c create mode 100644 drivers/net/phy/davicom.c create mode 100644 drivers/net/phy/lxt.c create mode 100644 drivers/net/phy/marvell.c create mode 100644 drivers/net/phy/micrel.c create mode 100644 drivers/net/phy/natsemi.c create mode 100644 drivers/net/phy/phy.c create mode 100644 drivers/net/phy/realtek.c create mode 100644 drivers/net/phy/teranetics.c create mode 100644 drivers/net/phy/vitesse.c create mode 100644 include/fsl_mdio.h create mode 100644 include/phy.h create mode 100644 include/phylib_all_drivers.h

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[U-Boot] [PATCH] powerpc/85xx: Drop CONFIG_VIDEO support on corenet_ds boards
by Kumar Gala 08 Apr '11

08 Apr '11

We don't really ever use Video cards on corenet_ds style boards and its bloating our image which is close the its max size. Drop support and also kill some defines for non-PNP PCI which we never use. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/configs/corenet_ds.h | 23 ----------------------- 1 files changed, 0 insertions(+), 23 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f4c3fcd..7c77973 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -458,33 +458,10 @@ #endif #ifdef CONFIG_PCI - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT - -/* video */ -#define CONFIG_VIDEO - -#ifdef CONFIG_VIDEO -#define CONFIG_BIOSEMU -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 -#ifndef CONFIG_PCI_PNP -#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS -#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ -- 1.7.3.4

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[U-Boot] DSN: failed (MESSAGE COULD NOT BE DELIVERED)
by Mailbot for etexusa.com 08 Apr '11

08 Apr '11

This is a Delivery Status Notification (DSN). I was unable to deliver your message to servers(a)akam.net. The error was; Domain "akam.net" can't receive email

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[U-Boot] DSN: failed (Delivery reports about your e-mail)
by Mailbot for etexusa.com 08 Apr '11

08 Apr '11

This is a Delivery Status Notification (DSN). I was unable to deliver your message to episr(a)comcast.net. I said RCPT TO:<episr(a)comcast.net> And they gave me the error; 550 5.1.1 Not our Customer

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