April 2011 - U-Boot

[U-Boot] [Nios] Pull Request
by Scott McNutt 10 Apr '11

10 Apr '11

Dear Wolfgang, The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://git.denx.de/u-boot-nios.git next Thomas Chou (1): nios2: reset cfi flash before reading env board/altera/nios2-generic/nios2-generic.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)

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[U-Boot] [PATCH 00/34] Blackfin updates for 2011.06
by Mike Frysinger 10 Apr '11

10 Apr '11

Andreas Schallenberg (1): Blackfin: dnp5370: new board port Chong Huang (1): Blackfin: bf525-ucr2: new board port Cliff Cai (1): Blackfin: bfin_sdh: set all timer bits before transfer Kyle Moffett (1): Blackfin: replace "bfin_reset_or_hang()" with "panic()" Mike Frysinger (29): Blackfin: bf518f-ezbrd: don't require SPI logic all the time Blackfin: skip RAM display for 0 mem systems Blackfin: drop CONFIG_SYS_TEXT_BASE from boards Blackfin: unify bootmode based LDR_FLAGS setup Blackfin: move CONFIG_BFIN_CPU back to board config.h Blackfin: bf527-sdp: update custom CFLAGS paths Blackfin: bf537-pnav/blackstamp/blackvme: drop empty config.mk files Blackfin: serial: clean up muxing a bit Blackfin: bf537-minotaur/bf537-srv1: undefine nfs when net is disabled Blackfin: bf537: fix L1 data defines Blackfin: bf561-ezkit/ibf-dsp561: invert env offset/addr logic Blackfin: fix bd_t handling Blackfin: BF50x: new processor port Blackfin: drop duplicate system mmr and L1 scratch defines Blackfin: BF52x: unify duplicated headers Blackfin: BF537: unify duplicated headers Blackfin: only check for os log when we have external memory Blackfin: turn off caches when self initializing Blackfin: default to L1 bank A when L1 bank B does not exist Blackfin: bf506f-ezkit: new board port Blackfin: adi boards: drop old ELF define Blackfin: bootrom.h: sync with toolchain Blackfin: bootldr: use common defines Blackfin: ldrinfo: new command Blackfin: adi boards: enable ldrinfo Blackfin: adi boards: enable CONFIG_MONITOR_IS_IN_RAM Blackfin: bf548-ezkit: move env sector Blackfin: bf518f-ezbrd: get MAC from flash Blackfin: bf526-ezbrd: get MAC from flash Sonic Zhang (1): Blackfin: bfin_sdh: add support for multiblock operations MAINTAINERS | 10 + README | 1 + arch/blackfin/config.mk | 15 +- arch/blackfin/cpu/cpu.h | 1 - arch/blackfin/cpu/gpio.c | 8 +- arch/blackfin/cpu/initcode.c | 25 +- arch/blackfin/cpu/reset.c | 18 +- arch/blackfin/cpu/serial.h | 72 +- arch/blackfin/cpu/start.S | 45 +- arch/blackfin/cpu/traps.c | 2 +- arch/blackfin/include/asm/blackfin_cdef.h | 6 + arch/blackfin/include/asm/blackfin_def.h | 10 + arch/blackfin/include/asm/config.h | 10 +- arch/blackfin/include/asm/mach-bf506/BF504_cdef.h | 1782 ++++++++++++++++++++ arch/blackfin/include/asm/mach-bf506/BF504_def.h | 944 +++++++++++ arch/blackfin/include/asm/mach-bf506/BF506_cdef.h | 11 + arch/blackfin/include/asm/mach-bf506/BF506_def.h | 11 + arch/blackfin/include/asm/mach-bf506/anomaly.h | 128 ++ arch/blackfin/include/asm/mach-bf506/def_local.h | 5 + arch/blackfin/include/asm/mach-bf506/gpio.h | 52 + arch/blackfin/include/asm/mach-bf506/portmux.h | 148 ++ arch/blackfin/include/asm/mach-bf506/ports.h | 59 + arch/blackfin/include/asm/mach-bf518/BF512_def.h | 6 - .../asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 994 ----------- .../asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h | 503 ------ arch/blackfin/include/asm/mach-bf527/BF522_cdef.h | 986 +++++++++++- arch/blackfin/include/asm/mach-bf527/BF522_def.h | 495 ++++++- arch/blackfin/include/asm/mach-bf527/BF524_cdef.h | 20 +- arch/blackfin/include/asm/mach-bf527/BF524_def.h | 12 +- arch/blackfin/include/asm/mach-bf527/BF526_cdef.h | 358 +---- arch/blackfin/include/asm/mach-bf527/BF526_def.h | 181 +-- arch/blackfin/include/asm/mach-bf533/BF531_def.h | 6 - arch/blackfin/include/asm/mach-bf533/BF532_def.h | 6 - arch/blackfin/include/asm/mach-bf533/BF533_def.h | 6 - .../asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 1624 ------------------ .../asm/mach-bf537/ADSP-EDN-BF534-extended_def.h | 819 --------- arch/blackfin/include/asm/mach-bf537/BF534_cdef.h | 1614 ++++++++++++++++++- arch/blackfin/include/asm/mach-bf537/BF534_def.h | 816 +++++++++- arch/blackfin/include/asm/mach-bf538/BF538_def.h | 6 - arch/blackfin/include/asm/mach-bf561/BF561_def.h | 7 +- .../include/asm/mach-common/bits/bootrom.h | 86 +- arch/blackfin/lib/board.c | 21 +- arch/blackfin/lib/u-boot.lds.S | 10 +- board/bct-brettl2/config.mk | 8 - board/bf506f-ezkit/Makefile | 54 + board/bf506f-ezkit/bf506f-ezkit.c | 27 + board/bf518f-ezbrd/bf518f-ezbrd.c | 61 +- board/bf518f-ezbrd/config.mk | 8 - board/bf525-ucr2/Makefile | 54 + board/bf525-ucr2/bf525-ucr2.c | 16 + board/bf526-ezbrd/bf526-ezbrd.c | 29 +- board/bf526-ezbrd/config.mk | 8 - board/bf527-ad7160-eval/config.mk | 8 - board/bf527-ezkit/config.mk | 8 - board/bf527-sdp/config.mk | 10 +- board/bf533-ezkit/config.mk | 6 - board/bf533-stamp/config.mk | 6 - board/bf537-minotaur/config.mk | 8 +- board/bf537-pnav/config.mk | 32 - board/bf537-srv1/config.mk | 8 +- board/bf537-stamp/config.mk | 6 - board/bf538f-ezkit/config.mk | 6 - board/bf548-ezkit/config.mk | 6 - board/bf561-acvilon/config.mk | 6 - board/bf561-ezkit/config.mk | 6 - board/blackstamp/config.mk | 32 - board/blackvme/config.mk | 32 - board/cm-bf527/config.mk | 8 - board/cm-bf533/config.mk | 6 - board/cm-bf537e/config.mk | 6 - board/cm-bf537u/config.mk | 6 - board/cm-bf548/config.mk | 6 - board/cm-bf561/config.mk | 6 - board/dnp5370/Makefile | 54 + board/dnp5370/dnp5370.c | 104 ++ board/ibf-dsp561/config.mk | 6 - board/ip04/config.mk | 6 - board/tcm-bf518/config.mk | 8 - board/tcm-bf537/config.mk | 6 - boards.cfg | 3 + common/Makefile | 1 + common/cmd_bootldr.c | 21 +- common/cmd_ldrinfo.c | 192 +++ doc/README.dnp5370 | 67 + drivers/mmc/bfin_sdh.c | 13 +- drivers/spi/bfin_spi.c | 2 + include/configs/bct-brettl2.h | 3 +- include/configs/bf506f-ezkit.h | 103 ++ include/configs/bf518f-ezbrd.h | 1 + include/configs/bf525-ucr2.h | 102 ++ include/configs/bf526-ezbrd.h | 1 + include/configs/bf527-ad7160-eval.h | 1 + include/configs/bf527-ezkit.h | 1 + include/configs/bf527-sdp.h | 1 + include/configs/bf533-ezkit.h | 1 + include/configs/bf533-stamp.h | 1 + include/configs/bf537-minotaur.h | 2 + include/configs/bf537-pnav.h | 1 + include/configs/bf537-srv1.h | 2 + include/configs/bf537-stamp.h | 1 + include/configs/bf538f-ezkit.h | 1 + include/configs/bf548-ezkit.h | 3 +- include/configs/bf561-acvilon.h | 3 +- include/configs/bf561-ezkit.h | 5 +- include/configs/bfin_adi_common.h | 3 +- include/configs/blackstamp.h | 1 + include/configs/blackvme.h | 3 +- include/configs/cm-bf527.h | 1 + include/configs/cm-bf533.h | 1 + include/configs/cm-bf537e.h | 1 + include/configs/cm-bf537u.h | 1 + include/configs/cm-bf548.h | 1 + include/configs/cm-bf561.h | 1 + include/configs/dnp5370.h | 128 ++ include/configs/ibf-dsp561.h | 5 +- include/configs/ip04.h | 1 + include/configs/tcm-bf518.h | 1 + include/configs/tcm-bf537.h | 1 + 118 files changed, 8280 insertions(+), 5007 deletions(-) create mode 100644 arch/blackfin/include/asm/mach-bf506/BF504_cdef.h create mode 100644 arch/blackfin/include/asm/mach-bf506/BF504_def.h create mode 100644 arch/blackfin/include/asm/mach-bf506/BF506_cdef.h create mode 100644 arch/blackfin/include/asm/mach-bf506/BF506_def.h create mode 100644 arch/blackfin/include/asm/mach-bf506/anomaly.h create mode 100644 arch/blackfin/include/asm/mach-bf506/def_local.h create mode 100644 arch/blackfin/include/asm/mach-bf506/gpio.h create mode 100644 arch/blackfin/include/asm/mach-bf506/portmux.h create mode 100644 arch/blackfin/include/asm/mach-bf506/ports.h delete mode 100644 arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h delete mode 100644 arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h delete mode 100644 arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h delete mode 100644 arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h create mode 100644 board/bf506f-ezkit/Makefile create mode 100644 board/bf506f-ezkit/bf506f-ezkit.c create mode 100644 board/bf525-ucr2/Makefile create mode 100644 board/bf525-ucr2/bf525-ucr2.c delete mode 100644 board/bf537-pnav/config.mk delete mode 100644 board/blackstamp/config.mk delete mode 100644 board/blackvme/config.mk create mode 100644 board/dnp5370/Makefile create mode 100644 board/dnp5370/dnp5370.c create mode 100644 common/cmd_ldrinfo.c create mode 100644 doc/README.dnp5370 create mode 100644 include/configs/bf506f-ezkit.h create mode 100644 include/configs/bf525-ucr2.h create mode 100644 include/configs/dnp5370.h -- 1.7.4.1

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[U-Boot] Please pull u-boot-cfi-flash
by Stefan Roese 10 Apr '11

10 Apr '11

Hi Wolfgang, please pull the following changes: The following changes since commit 4db2fa7f9446d0f2fe8db3d62184b1212fe22707: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2011-04-05 12:24:20 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Heiko Schocher (1): mtd, cfi: introduce void flash_protect_default(void) Mario Schuknecht (1): cfi_flash: use AMD fixups for AMIC (e.g. A29L160A series) too drivers/mtd/cfi_flash.c | 80 +++++++++++++++++++++++++--------------------- include/flash.h | 1 + 2 files changed, 44 insertions(+), 37 deletions(-)

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[U-Boot] [PATCH] Removed clearing of L2-as-SRAM
by Fabian Cenedese 10 Apr '11

10 Apr '11

Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by: Fabian Cenedese <cenedese(a)indel.ch> Cc: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 7 ------- 1 files changed, 0 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 8fb27ab..1c42a0b 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -42,8 +42,6 @@ void cpu_init_f(void) #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - char *l2srbar; - int i; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); @@ -54,10 +52,5 @@ void cpu_init_f(void) /* set L2E=1 & L2SRAM=001 */ out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); - - /* Initialize L2 SRAM to zero */ - l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; - for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) - l2srbar[i] = 0; #endif } -- 1.7.3.1.msysgit.0

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[U-Boot] [PATCH] fsl_esdhc: Deal with watermark level register related changes
by Kumar Gala 10 Apr '11

10 Apr '11

From: Priyanka Jain <Priyanka.Jain(a)freescale.com> P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/mmc/fsl_esdhc.c | 8 ++++---- include/fsl_esdhc.h | 15 ++++++++++++++- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0b5f78a..1f4dee4 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -88,6 +88,7 @@ #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -131,6 +132,7 @@ #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0962ac4..4f1b515 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -178,14 +178,14 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) wml_value = data->blocksize/4; if (data->flags & MMC_DATA_READ) { - if (wml_value > 0x10) - wml_value = 0x10; + if (wml_value > WML_RD_WML_MAX) + wml_value = WML_RD_WML_MAX_VAL; esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value); esdhc_write32(&regs->dsaddr, (u32)data->dest); } else { - if (wml_value > 0x80) - wml_value = 0x80; + if (wml_value > WML_WR_WML_MAX) + wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) { printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return TIMEOUT; diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 477bbd7..8418bf7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -2,7 +2,7 @@ * FSL SD/MMC Defines *------------------------------------------------------------------- * - * Copyright 2007-2008,2010 Freescale Semiconductor, Inc + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -135,8 +135,21 @@ #define WML 0x2e044 #define WML_WRITE 0x00010000 +#ifdef CONFIG_FSL_SDHC_V2_3 +#define WML_RD_WML_MAX 0x80 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x0 +#define WML_WR_WML_MAX_VAL 0x0 +#define WML_RD_WML_MASK 0x7f +#define WML_WR_WML_MASK 0x7f0000 +#else +#define WML_RD_WML_MAX 0x10 +#define WML_WR_WML_MAX 0x80 +#define WML_RD_WML_MAX_VAL 0x10 +#define WML_WR_WML_MAX_VAL 0x80 #define WML_RD_WML_MASK 0xff #define WML_WR_WML_MASK 0xff0000 +#endif #define BLKATTR 0x2e004 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) -- 1.7.2.3

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[U-Boot] Your Payment !!!
by Western union payment office 09 Apr '11

09 Apr '11

Good Day, We have sent $5,000USD already through western union,as we are mandated to transfer you the total sum of $8,000,000USD through Western Union by the United Nations,(ECOWAS).Send Your Names,Address,Phone number,Processing your first payment of $5,000USD to collect SENDER'S NAME: James Bill MTCN: 916-137-2892 COUNTRY:Nigeria AMOUNT: $5,000 USD TEST QUESTION: Honest TEST ANSWER: Trust You can reach our international agent for further details with the information's as stated below. Contact Manager: Mr. Frank Amos. Direct Telephone: +2347054364131 Email: wumt19(a)hotmail.com Thanks Western union Online Announcer: Rita David.

1 0

[U-Boot] [PATCH 1/6] powerpc/85xx: Add 36-bit address map support to P1022DS
by Kumar Gala 09 Apr '11

09 Apr '11

From: Jiang Yutang <b14898(a)freescale.com> Signed-off-by: Jiang Yutang <b14898(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/p1022ds/p1022ds.c | 3 ++ boards.cfg | 1 + include/configs/P1022DS.h | 46 ++++++++++++++++++++++++++++++++++++- 3 files changed, 49 insertions(+), 1 deletions(-) diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 62beafa..6f20dc3 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -53,6 +53,9 @@ int checkboard(void) u8 sw; puts("Board: P1022DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); diff --git a/boards.cfg b/boards.cfg index 263c1e6..2622f78 100644 --- a/boards.cfg +++ b/boards.cfg @@ -523,6 +523,7 @@ P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5f47d1a..c15cb8d 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -14,6 +14,10 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -39,10 +43,11 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PHYS_64BIT +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -65,7 +70,11 @@ */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* DDR Setup */ @@ -111,7 +120,11 @@ * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) @@ -145,7 +158,11 @@ #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) @@ -241,32 +258,59 @@ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI -- 1.7.2.3

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[U-Boot] [PATCH 1/2] P4080/PBL: add support for boot from SPI flash.
by Shaohui Xie 09 Apr '11

09 Apr '11

PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806(a)freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> Signed-off-by: Shaohui Xie <b21989(a)freescale.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++++++++++++++++++ board/freescale/corenet_ds/tlb.c | 12 +++++++++++- boards.cfg | 1 + include/configs/corenet_ds.h | 27 ++++++++++++++++++++++++++- 4 files changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8ece970..a977000 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -141,6 +141,22 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_RAMBOOT_PBL + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); @@ -164,6 +180,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 1ae0416..fe77e79 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. @@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/boards.cfg b/boards.cfg index 45c3102..f19cc34 100644 --- a/boards.cfg +++ b/boards.cfg @@ -529,6 +529,7 @@ P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale +P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000 mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bff212e..8d10862 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -28,6 +28,11 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -63,12 +68,17 @@ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ +#endif + #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ @@ -100,6 +110,18 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -192,6 +214,10 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -461,7 +487,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -- 1.6.4

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[U-Boot] Dear Email Account Owner Notice‏‏!!!
by Hines-Smith, Sharon 09 Apr '11

09 Apr '11

Your MailBox Has Exceeded It Quota/Limit As Set By Your Administrator, And You Will Not Be Able To Receive Or Send New Mails Until You Re-Validate. To Re-Validate CLICK HERE<http://pne.cc/?312c7b>

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[U-Boot] Winner
by Honda Car Board 09 Apr '11

09 Apr '11

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