November 2011 - U-Boot

[U-Boot] Hello Friend
by Rebeca Majer 09 Nov '11

09 Nov '11

Těší mě, Jsem slečna Rebeca, zájem o vás, a přejí si, že jste jako můj přítel, pro přítele je především o respekt, obdiv a lásku i vášeň Přátelství se skládá ze sdílení nápadů a plánování společně, Chci, aby vám moje fotografie pro vás, pokud jste odpovězte mi. poděkování od Rebeca. Nice to meet you, Am miss Rebeca ,interested in you, and wish to have you as my friend, for a friend is all about Respect,Admiration and love passion also friendship is consist of sharing of ideas and planing together, i intend to send you my picture for you,if you reply me. thanks from Rebeca.

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[U-Boot] Business Proposal..
by Mr. Wen Lee 09 Nov '11

09 Nov '11

I am Mr. Wen Lee director of operations of the Bank Of Taipei Taiwan. I have an obscured business proposal for you. Reply if interested.

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[U-Boot] Business Proposal..
by Mr. Wen Lee 09 Nov '11

09 Nov '11

I am Mr. Wen Lee director of operations of the Bank Of Taipei Taiwan. I have an obscured business proposal for you. Reply if interested.

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[U-Boot] OPEN THE ATTACHED FILE AND VIEW THE INHERITANCE CLAIMS.
by NEXT OF KIN CLAIMS DEPT 09 Nov '11

09 Nov '11

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[U-Boot] [PATCH] arm, davinci: add DAVINCI_SYSCFG_SUSPSRC_UART2
by Heiko Schocher 09 Nov '11

09 Nov '11

commit f9fc237f1f07d4e5ff7c9c2da39cabc8d3d7b339 Author: Bastian Ruppert <Bastian.Ruppert(a)Sewerin.de> Date: Tue Oct 4 23:43:28 2011 +0000 Davinci: ea20: set console on UART0 replaced DAVINCI_SYSCFG_SUSPSRC_UART2 with DAVINCI_SYSCFG_SUSPSRC_UART0 but DAVINCI_SYSCFG_SUSPSRC_UART2 is needed on the enbw_cmc board, see patches: http://lists.denx.de/pipermail/u-boot/2011-October/104399.html Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Bastian Ruppert <Bastian.Ruppert(a)Sewerin.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> --- arch/arm/include/asm/arch-davinci/hardware.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 8e7d97e..aba517e 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -469,6 +469,7 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) struct davinci_syscfg1_regs { -- 1.7.6.4

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[U-Boot] [PATCH 00/15 V2] Support for the DENX M28 SoM
by Marek Vasut 09 Nov '11

09 Nov '11

This series adds support for DENX M28 SoM and M28EVK kit. This series depends on previous series: * Support for both FEC interfaces on i.MX28 * Random NAND fixes and improvements * SPL modifications V2: * Convert to SPL framework * Squash patches together * Fix pointed out issues Marek Vasut (15): iMX28: Initial support for iMX28 CPU iMX28: Add SSP MMC driver FEC: Add support for iMX28 quirks iMX28: Add PINMUX control iMX28: Add I2C bus driver iMX28: Add GPIO control iMX28: Add SPI driver iMX28: Add APBH DMA driver iMX28: Add GPMI NAND driver iMX28: Add driver for internal RTC iMX28: Add image header generator tool iMX28: Add u-boot.sb target to Makefile iMX28: Add support for DENX M28EVK board M28: Add MMC SPL M28: Add doc/README.m28 documentation MAINTAINERS | 1 + Makefile | 5 + arch/arm/cpu/arm926ejs/mx28/Makefile | 46 + arch/arm/cpu/arm926ejs/mx28/clock.c | 355 +++++++ arch/arm/cpu/arm926ejs/mx28/iomux.c | 109 +++ arch/arm/cpu/arm926ejs/mx28/mx28.c | 200 ++++ arch/arm/cpu/arm926ejs/mx28/timer.c | 141 +++ arch/arm/include/asm/arch-mx28/clock.h | 61 ++ arch/arm/include/asm/arch-mx28/dma.h | 170 ++++ arch/arm/include/asm/arch-mx28/gpio.h | 32 + arch/arm/include/asm/arch-mx28/imx-regs.h | 39 + arch/arm/include/asm/arch-mx28/iomux-mx28.h | 537 +++++++++++ arch/arm/include/asm/arch-mx28/iomux.h | 168 ++++ arch/arm/include/asm/arch-mx28/regs-apbh.h | 466 +++++++++ arch/arm/include/asm/arch-mx28/regs-base.h | 88 ++ arch/arm/include/asm/arch-mx28/regs-bch.h | 230 +++++ arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 312 ++++++ arch/arm/include/asm/arch-mx28/regs-common.h | 66 ++ arch/arm/include/asm/arch-mx28/regs-gpmi.h | 222 +++++ arch/arm/include/asm/arch-mx28/regs-i2c.h | 207 ++++ arch/arm/include/asm/arch-mx28/regs-ocotp.h | 173 ++++ arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 1284 +++++++++++++++++++++++++ arch/arm/include/asm/arch-mx28/regs-power.h | 413 ++++++++ arch/arm/include/asm/arch-mx28/regs-rtc.h | 147 +++ arch/arm/include/asm/arch-mx28/regs-ssp.h | 349 +++++++ arch/arm/include/asm/arch-mx28/regs-timrot.h | 171 ++++ arch/arm/include/asm/arch-mx28/sys_proto.h | 32 + board/denx/m28evk/Makefile | 57 ++ board/denx/m28evk/m28_init.h | 36 + board/denx/m28evk/m28evk.c | 195 ++++ board/denx/m28evk/mem_init.c | 213 ++++ board/denx/m28evk/mmc_boot.c | 273 ++++++ board/denx/m28evk/power_init.c | 911 ++++++++++++++++++ board/denx/m28evk/start.S | 396 ++++++++ board/denx/m28evk/u-boot-spl.lds | 87 ++ board/denx/m28evk/u-boot.bd | 14 + boards.cfg | 1 + doc/README.m28 | 223 +++++ drivers/dma/Makefile | 1 + drivers/dma/apbh_dma.c | 691 +++++++++++++ drivers/gpio/Makefile | 1 + drivers/gpio/mxs_gpio.c | 136 +++ drivers/i2c/Makefile | 1 + drivers/i2c/mxs_i2c.c | 240 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/mxsmmc.c | 351 +++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand.c | 1159 ++++++++++++++++++++++ drivers/net/fec_mxc.c | 44 +- drivers/rtc/Makefile | 1 + drivers/rtc/mxsrtc.c | 86 ++ drivers/spi/Makefile | 1 + drivers/spi/mxs_spi.c | 172 ++++ include/configs/m28evk.h | 289 ++++++ tools/Makefile | 6 + tools/mxsboot.c | 687 +++++++++++++ 56 files changed, 12296 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/mx28/Makefile create mode 100644 arch/arm/cpu/arm926ejs/mx28/clock.c create mode 100644 arch/arm/cpu/arm926ejs/mx28/iomux.c create mode 100644 arch/arm/cpu/arm926ejs/mx28/mx28.c create mode 100644 arch/arm/cpu/arm926ejs/mx28/timer.c create mode 100644 arch/arm/include/asm/arch-mx28/clock.h create mode 100644 arch/arm/include/asm/arch-mx28/dma.h create mode 100644 arch/arm/include/asm/arch-mx28/gpio.h create mode 100644 arch/arm/include/asm/arch-mx28/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx28/iomux-mx28.h create mode 100644 arch/arm/include/asm/arch-mx28/iomux.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-apbh.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-base.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-bch.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-clkctrl.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-common.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-gpmi.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-i2c.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-ocotp.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-pinctrl.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-power.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-rtc.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-ssp.h create mode 100644 arch/arm/include/asm/arch-mx28/regs-timrot.h create mode 100644 arch/arm/include/asm/arch-mx28/sys_proto.h create mode 100644 board/denx/m28evk/Makefile create mode 100644 board/denx/m28evk/m28_init.h create mode 100644 board/denx/m28evk/m28evk.c create mode 100644 board/denx/m28evk/mem_init.c create mode 100644 board/denx/m28evk/mmc_boot.c create mode 100644 board/denx/m28evk/power_init.c create mode 100644 board/denx/m28evk/start.S create mode 100644 board/denx/m28evk/u-boot-spl.lds create mode 100644 board/denx/m28evk/u-boot.bd create mode 100644 doc/README.m28 create mode 100644 drivers/dma/apbh_dma.c create mode 100644 drivers/gpio/mxs_gpio.c create mode 100644 drivers/i2c/mxs_i2c.c create mode 100644 drivers/mmc/mxsmmc.c create mode 100644 drivers/mtd/nand/mxs_nand.c create mode 100644 drivers/rtc/mxsrtc.c create mode 100644 drivers/spi/mxs_spi.c create mode 100644 include/configs/m28evk.h create mode 100644 tools/mxsboot.c -- 1.7.5.4

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[U-Boot] [PATCH] devkit8000: Fix NAND SPL on boards with 256MB NAND
by Tom Rini 09 Nov '11

09 Nov '11

The devkit8000 ships with either a 128MB or 256MB NAND chip. In order for SPL to work with 256MB NAND CONFIG_SYS_NAND_5_ADDR_CYCLE needs to be set. After talking with Scott Wood this should be safe to set even for smaller NAND chips. Cc: Scott Wood <scottwood(a)freescale.com> Cc: Frederik Kriewitz <frederik(a)kriewitz.eu> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Signed-off-by: Tom Rini <trini(a)ti.com> --- include/configs/devkit8000.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index ba0d23e..1856aa9 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -332,6 +332,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -- 1.7.0.4

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[U-Boot] [PATCH] nds32: fix data section of linker script
by Macpaul Lin 09 Nov '11

09 Nov '11

Make linker script handles .data.rel sections. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> Tested-by: Macpaul Lin <macpaul(a)gmail.com> Cc: Mike Frysinger <vapier(a)gentoo.org> --- arch/nds32/cpu/n1213/u-boot.lds | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 45221ee..1903420 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -41,7 +41,7 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { *(.data*) } . = ALIGN(4); -- 1.7.3.5

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[U-Boot] [PATCH] andes_pcu.h: header file of andes_pcu power control unit
by Macpaul Lin 09 Nov '11

09 Nov '11

header file of andes_pcu power control unit Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- include/andestech/andes_pcu.h | 367 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 367 insertions(+), 0 deletions(-) create mode 100644 include/andestech/andes_pcu.h diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h new file mode 100644 index 0000000..b4dbd71 --- /dev/null +++ b/include/andestech/andes_pcu.h @@ -0,0 +1,367 @@ +/* + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Andes Power Control Unit + */ +#ifndef __ANDES_PCU_H +#define __ANDES_PCU_H + +#ifndef __ASSEMBLY__ + +struct pcs { + unsigned int cr; /* PCSx Configuration (clock scaling) */ + unsigned int parm; /* PCSx Parameter*/ + unsigned int stat1; /* PCSx Status 1 */ + unsigned int stat2; /* PCSx Stusts 2 */ + unsigned int pdd; /* PCSx PDD */ +}; + +struct andes_pcu { + unsigned int rev; /* 0x00 - PCU Revision */ + unsigned int spinfo; /* 0x04 - Scratch Pad Info */ + unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ + unsigned int soc_id; /* 0x10 - SoC ID */ + unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ + unsigned int soc_apb; /* 0x18 - SoC APB configuration */ + unsigned int rsvd2; /* 0x1C */ + unsigned int dcsrcr0; /* 0x20 - Driving Capability + and Slew Rate Control 0 */ + unsigned int dcsrcr1; /* 0x24 - Driving Capability + and Slew Rate Control 1 */ + unsigned int dcsrcr2; /* 0x28 - Driving Capability + and Slew Rate Control 2 */ + unsigned int rsvd3; /* 0x2C */ + unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ + unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ + unsigned int dmaes; /* 0x38 - DMA Engine Selection */ + unsigned int rsvd4; /* 0x3C */ + unsigned int oscc; /* 0x40 - OSC Control */ + unsigned int pwmcd; /* 0x44 - PWM Clock divider */ + unsigned int socmisc; /* 0x48 - SoC Misc. */ + unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ + unsigned int bsmcr; /* 0x80 - BSM Controrl */ + unsigned int bsmst; /* 0x84 - BSM Status */ + unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ + unsigned int west; /* 0x8C - Wakeup Event Status */ + unsigned int rsttiming; /* 0x90 - Reset Timing */ + unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ + unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ + struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ + unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ + struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ + unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ + struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ + unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ + struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ + unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ + struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ + unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ + struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ + unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ + struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ + unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ + struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ + unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ + struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ + unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ + unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager + Scratch Pad Memory 0 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * PCU Revision Register (ro) + */ +#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) + +/* + * Scratch Pad Info Register (ro) + */ +#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) +#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) + +/* + * SoC ID Register (ro) + */ +#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) +#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) +#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) + +/* + * SoC AHB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) +#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) +#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) +#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) +#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) +#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) +#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) +#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) +#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) +#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) +#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) +#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) +#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) +#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) +#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) +#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) +#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) +#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) +#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) +#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) +#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) + +/* + * SoC APB Configuration Register (ro) + */ +#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) +#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) +#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) +#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) +#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) +#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) +#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) +#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) +#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) +#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) +#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) +#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) +#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) + +/* + * Driving Capability and Slew Rate Control Register 0 (rw) + */ +#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) +#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) + +/* + * Driving Capability and Slew Rate Control Register 1 (rw) + */ +#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) + +/* + * Driving Capability and Slew Rate Control Register 2 (rw) + */ +#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) +#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) +#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) +#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) +#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) +#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) +#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) +#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) + +/* + * Multi-function Port Setting Register 0 (rw) + */ +#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) +#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) +#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) +#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) +#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) +#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) +#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) + +/* + * Multi-function Port Setting Register 1 (rw) + */ +#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) +#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) +#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) +#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) +#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) +#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) +#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) +#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) +#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) +#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) +#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) +#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) +#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) +#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) +#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) +#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) + +/* + * DMA Engine Selection Register (rw) + */ +#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) +#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) +#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) +#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) +#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) +#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) +#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) +#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) + +/* + * OSC Control Register (rw) + */ +#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) +#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) +#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) +#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) +#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) +#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) + +/* + * PWM Clock Divider Register (rw) + */ +#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) + +/* + * SoC Misc. Register (rw) + */ +#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) +#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) +#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) +#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) +#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) +#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) +#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) +#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) +#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) +#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) +#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) +#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) +#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) +#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) +#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) +#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) +#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) +#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) +#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) +#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) +#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) +#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) +#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) +#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) +#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) +#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) +#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) +#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) +#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) +#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) + +/* + * BSM Control Register (rw) + */ +#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) + +/* + * BSM Status Register + */ +#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) +#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) +#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) + +/* + * Wakeup Event Sensitivity Register (rw) + */ +#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) + +/* + * Wakeup Event Status Register (ro) + */ +#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) + +/* + * Reset Timing Register + */ +#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) +#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) +#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) +#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) + +/* + * PCU Interrupt Status Register + */ +#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) +#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) +#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) +#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) +#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) +#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) +#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) +#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) +#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) +#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) + +/* + * PCSx Configuration Register + */ +#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) +#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) +#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ + +/* + * PCSx Parameter Register (rw) + */ +#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) +#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) +#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) + +/* + * PCSx Status Register 1 + */ +#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) +#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) + +/* + * PCSx Status Register 2 + */ +#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) +#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) + +/* + * PCSx PDD Register + * This is reserved for PCS(1-7) + */ +#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) +#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) +#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) +#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) + +#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) +#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) +#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) +#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) +#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) +#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) +#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) +#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) +#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) + +#endif /* __ANDES_PCU_H */ -- 1.7.3.5

2 1

[U-Boot] [PATCH] dwcddr21mctl: Synopsys DWC DDR2/1 Memory Controller
by Macpaul Lin 09 Nov '11

09 Nov '11

Header definitions of Synopsys DWC DDR2/1 Memory Controller. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- include/synopsys/dwcddr21mctl.h | 337 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 337 insertions(+), 0 deletions(-) create mode 100644 include/synopsys/dwcddr21mctl.h diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h new file mode 100644 index 0000000..a33b122 --- /dev/null +++ b/include/synopsys/dwcddr21mctl.h @@ -0,0 +1,337 @@ +/* + * (C) Copyright 2011 Andes Technology Corp + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller + */ +#ifndef __DWCDDR21MCTL_H +#define __DWCDDR21MCTL_H + +#ifndef __ASSEMBLY__ +struct dwcddr21mctl { + unsigned int ccr; /* Controller Configuration */ + unsigned int dcr; /* DRAM Configuration */ + unsigned int iocr; /* I/O Configuration */ + unsigned int csr; /* Controller Status */ + unsigned int drr; /* DRAM refresh */ + unsigned int tpr0; /* SDRAM Timing Parameters 0 */ + unsigned int tpr1; /* SDRAM Timing Parameters 1 */ + unsigned int tpr2; /* SDRAM Timing Parameters 2 */ + unsigned int gdllcr; /* Global DLL Control */ + unsigned int dllcr[10]; /* DLL Control */ + unsigned int rslr[4]; /* Rank System Lantency */ + unsigned int rdgr[4]; /* Rank DQS Gating */ + unsigned int dqtr[9]; /* DQ Timing */ + unsigned int dqstr; /* DQS Timing */ + unsigned int dqsbtr; /* DQS_b Timing */ + unsigned int odtcr; /* ODT Configuration */ + unsigned int dtr[2]; /* Data Training */ + unsigned int dtar; /* Data Training Address */ + unsigned int rsved[82]; /* Reserved */ + unsigned int mr; /* Mode Register */ + unsigned int emr; /* Extended Mode Register */ + unsigned int emr2; /* Extended Mode Register 2 */ + unsigned int emr3; /* Extended Mode Register 3 */ + unsigned int hpcr[32]; /* Host Port Configurarion */ + unsigned int pqcr[8]; /* Priority Queue Configuration */ + unsigned int mmgcr; /* Memory Manager General Config */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * Control Configuration Register + */ +#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) +#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) +#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) +#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) +#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) +#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) +#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) +#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) +#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) +#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) +#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28) +#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) +#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) +#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) + +/* + * DRAM Configuration Register + */ +#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) +#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1) +#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) +#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12) +#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13) +#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25) +#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27) +#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31) + +/* + * I/O Configuration Register + */ +#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8) +#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26) +#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29) +#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30) +#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31) + +/* + * Controller Status Register + */ +#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0) +#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18) +#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19) +#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20) +#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21) +#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22) + +/* + * DRAM Refresh Register + */ +#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0) +#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8) +#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 0 + */ +#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2) +#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5) +#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16) +#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21) +#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25) +#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 1 + */ +#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2) +#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3) +#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14) +#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23) +#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27) +#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31) + +/* + * SDRAM Timing Parameters Register 2 + */ +#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0) +#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10) +#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15) + +/* + * Global DLL Control Register + */ +#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2) +#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5) +#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9) +#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11) +#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12) +#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20) +#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29) + +/* + * DLL Control Register 0-9 + */ +#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14) +#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18) +#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19) +#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31) + +/* + * Rank System Lantency Register + */ +#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24) + +/* + * Rank DQS Gating Register + */ +#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0) +#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2) +#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4) +#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6) +#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8) +#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12) +#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14) +#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16) + +/* + * DQ Timing Register + */ +#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16) +#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20) +#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28) + +/* + * DQS Timing Register + */ +#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24) + +/* + * DQS_b (DQSBTR) Timing Register + */ +#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6) +#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12) +#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15) +#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18) +#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21) +#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24) + +/* + * ODT Configuration Register + */ +#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4) +#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8) +#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12) +#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16) +#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20) +#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24) +#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28) + +/* + * Data Training Register + */ +#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */ +#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */ +#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */ +#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */ + +#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */ +#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */ +#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */ +#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */ + +/* + * Data Training Address Register + */ +#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0) +#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12) +#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28) + +/* + * Mode Register + */ +#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_MR_BT(x) ((x) << 3) +#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4) +#define DWCDDR21MCTL_MR_TM(x) ((x) << 7) +#define DWCDDR21MCTL_MR_DR(x) ((x) << 8) +#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9) +#define DWCDDR21MCTL_MR_PD(x) ((x) << 12) + +/* + * Extended Mode register + */ +#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0) +#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1) +#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2) +#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3) +#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6) +#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7) +#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10) +#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11) +#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12) + +#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x) +#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x) + +#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0)) +#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1)) +#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0)) +#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1)) + +/* + * Extended Mode register 2 + */ +#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0) +#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3) +#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7) + +/* + * Extended Mode register 3: [15:0] reserved for JEDEC. + */ + +/* + * Host port Configuration register 0-31 + */ +#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0) + +/* + * Priority Queue Configuration register 0-7 + */ +#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0) +#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8) +#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10) +#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12) +#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20) +#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25) +#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28) + +/* + * Memory Manager General Configuration register + */ +#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0) + +#endif /* __DWCDDR21MCTL_H */ -- 1.7.3.5

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