September 2010 - U-Boot

[U-Boot] [PATCH] Link the correct libgcc.a on ARMv4T architecture
by Paul Hsu 08 Sep '10

08 Sep '10

If we use $(CC -print-libgcc-file-name) without option -march=armv4t, we will link the wrong version libgcc.a(for ARMv5). That causes cpu core raising excptions when u-boot running on the board. Signed-off-by:Paul Hsu <pochun.hsu(a)gmail.com> --- Makefile | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 4f1cb1b..978c9cd 100644 --- a/Makefile +++ b/Makefile @@ -259,6 +259,17 @@ LIBS := $(addprefix $(obj),$(LIBS)) LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) +#check ARMV4T +ifdef CPU +ifeq ("$(CPU)","arm920t") +ARMV4T := yes +endif +ifeq ("$(CPU)","arm720t") +ARMV4T := yes +endif +endif + + # Add GCC lib ifdef USE_PRIVATE_LIBGCC ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") @@ -267,8 +278,12 @@ else PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc endif else +ifeq ("$(ARMV4T)","yes") +PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name -march=armv4t`) -lgcc +else PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc endif +endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS -- 1.7.0.4

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[U-Boot] Kindly Subscribe me to this list for U-boot
by Srigopal Kalyanaraman 08 Sep '10

08 Sep '10

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[U-Boot] [PATCH v3 0/2] Add support for new SoC APM821XX
by tmarri＠apm.com 08 Sep '10

08 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM821XX is Applied Micro Circuits Corporations naming convention for new line of SoCs. V2: * Missing space before "<". * SDR_AHB_CFG not used, remove. * boot device dfinitions are board specific ? removed. * APM82161_MASK not used, remove * set_mcsr() is already called in ddr init, no need to call here. * removed finding bootdevice function which is not used. * Add spaces in tlbentry() function. * Board early init function is empty remove. * Remove CONFIG_SYS_EXTSRAM_BASE. * Set CONFIG_SYS_FLASH_SIZE to 4MB * Remove CONFIG_SIZE_REDUCE & CONFIG_SECTOR_REDUCE. * Spaces around " >> " . * Correct the phy name CONFIG_M88E1111_PHY to CONFIG_RTL8211CL_PHY. * Removed Defines added to 405ex. V3: * Missing TLB entry for CONFIG_SYS_BOOT_BASE_ADDR. * Move CONFIG_SYS_EBC_PB0AP etc to EBC area in the config file. * remove unused CONFIG_RTL8211CL_PHY. * Replace hard coded valued for CONFIG_SYS_EBC_CFG with macro definitions. * Change APM82XXX to APM821XX * Modify the way cpu id is printed. * Correct inadvertent change. * Sort define list. * Remove comment for get_sys_info(). * Define a symbolic constat CONFIG_SYS_OCM_SIZE. * Create apm821xx.h instead of using ppc440.h * board.cfg add the entry in sorted. * use puts() if there is no formating needed. * Correct multiline comment. Tirumala Marri (2): APM821xx: Add CPU support APM821xx: Add bluestone board support MAINTAINERS | 3 + MAKEALL | 1 + arch/powerpc/cpu/ppc4xx/cpu.c | 36 ++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 5 +- arch/powerpc/cpu/ppc4xx/speed.c | 76 +++++- arch/powerpc/cpu/ppc4xx/start.S | 11 +- arch/powerpc/cpu/ppc4xx/tlb.c | 2 + arch/powerpc/include/asm/ppc4xx-ebc.h | 4 + arch/powerpc/include/asm/ppc4xx-isram.h | 14 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + board/amcc/bluestone/Makefile | 52 ++++ board/amcc/bluestone/bluestone.c | 111 +++++++ board/amcc/bluestone/config.mk | 40 +++ board/amcc/bluestone/init.S | 59 ++++ boards.cfg | 1 + include/apm821xx.h | 493 +++++++++++++++++++++++++++++++ include/configs/bluestone.h | 175 +++++++++++ include/ppc4xx.h | 11 +- 20 files changed, 1087 insertions(+), 25 deletions(-) create mode 100644 board/amcc/bluestone/Makefile create mode 100644 board/amcc/bluestone/bluestone.c create mode 100644 board/amcc/bluestone/config.mk create mode 100644 board/amcc/bluestone/init.S create mode 100644 include/apm821xx.h create mode 100644 include/configs/bluestone.h

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[U-Boot] [v3 0/2] Add support for new SoC APM82XXX
by tmarri＠apm.com 08 Sep '10

08 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM8XXXX is Applied Micro Circuits Corporations naming convention for new line of SoCs. V1: * Squash some of the patches. * add space between "||" and "\". * Add spaces around operators. * Unsigned int to u32. * Add empty line which was removed. * remove warning "unused variable" in cpu_init.c * Remove "All rights reserved" phrase from headers. * Add empty line which was removed. * Move EBC definititions to bluestone_config.h file * Remove reconfigure_EBC() function. * Remove unused CONFIG_SDRAM16BIT_OFFSET. * Remove unused CONFIG_SDRAM_INFO_EEPROM_ADDR. * Add empty lines in bluestone.c file. * Replacing AC_R | AC_W | AC_X with AC_RWX. * Remove changes to main Makefile * Remove NAND references from config file. * Squash some of the patches. * Remove top Makefile change. V2: * Missing space before "<". * SDR_AHB_CFG not used, remove. * boot device dfinitions are board specific ? removed. * APM82161_MASK not used, remove * set_mcsr() is already called in ddr init, no need to call here. * removed finding bootdevice function which is not used. * Add spaces in tlbentry() function. * Board early init function is empty remove. * Remove CONFIG_SYS_EXTSRAM_BASE. * Set CONFIG_SYS_FLASH_SIZE to 4MB * Remove CONFIG_SIZE_REDUCE & CONFIG_SECTOR_REDUCE. * Spaces around " >> " . * Correct the phy name CONFIG_M88E1111_PHY to CONFIG_RTL8211CL_PHY. * Removed Defines added to 405ex. V3: * Missing TLB entry for CONFIG_SYS_BOOT_BASE_ADDR. * Correct multiline comment. * Move CONFIG_SYS_EBC_PB0AP etc to EBC area in the config file. * remove unused CONFIG_RTL8211CL_PHY. * Replace hard coded valued for CONFIG_SYS_EBC_CFG with macro definitions. * board.cfg add the entry in sorted. * use puts() if there is no formating needed. * Change APM82XXX to APM821XX * Modify the way cpu id is printed. * Correct inadvertent change. * Sort define list. * Remove comment for get_sys_info(). * Define a symbolic constat ISRAM1_OCM_SIZE. * Create apm821xx.h instead of using ppc440.h Tirumala Marri (2): APM821xx: Add CPU support APM821xx: Add bluestone board support MAINTAINERS | 3 + MAKEALL | 1 + arch/powerpc/cpu/ppc4xx/cpu.c | 36 ++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 5 +- arch/powerpc/cpu/ppc4xx/speed.c | 76 +++++- arch/powerpc/cpu/ppc4xx/start.S | 11 +- arch/powerpc/cpu/ppc4xx/tlb.c | 2 + arch/powerpc/include/asm/ppc4xx-ebc.h | 4 + arch/powerpc/include/asm/ppc4xx-isram.h | 14 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + board/amcc/bluestone/Makefile | 52 ++++ board/amcc/bluestone/bluestone.c | 111 +++++++ board/amcc/bluestone/config.mk | 40 +++ board/amcc/bluestone/init.S | 59 ++++ boards.cfg | 1 + include/apm821xx.h | 493 +++++++++++++++++++++++++++++++ include/configs/bluestone.h | 175 +++++++++++ include/ppc4xx.h | 11 +- 20 files changed, 1087 insertions(+), 25 deletions(-) create mode 100644 board/amcc/bluestone/Makefile create mode 100644 board/amcc/bluestone/bluestone.c create mode 100644 board/amcc/bluestone/config.mk create mode 100644 board/amcc/bluestone/init.S create mode 100644 include/apm821xx.h create mode 100644 include/configs/bluestone.h

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[U-Boot] Loading u-boot from SD/MMC (was Re: [PATCH v3] AT91: MCI: add SD/MMC driver using mmc framework)
by Reinhard Meyer 08 Sep '10

08 Sep '10

Dear Will Tucker, > Hi, > > I’m trying to get the ATSAM9G20-EK booting from SD/MMC on MCI A, with the Nand > and Dataflash disabled, with no luck. > > I have gotten the latest u-boot-atmel compiled and placed boot.bin on a FAT 16 > formatted. When I turn power on I only get RomBoot on the debug uart. > > 1) Do I need to use the latest AT91Bootstrap, I have v1.16 but do not see any > way to enable the mci > > If I need an update where can I get the latest version? > > Any help would be appreciated, > > Will Tucker > First, please observe the following: 1. Start a new thread for comments/questions unrelated to the existing thread. 2. Always post the u-boot mailing list as well. 3. Please make your lines wrap at less than 80 characters. To give a brief answer to your issue: Please study sections 8 and 13 of the 9G20 datasheet. As a result you will see that the ROM will try to load "boot.bin" to internal SRAM. This will limit the image size to 16K. Apparently that cannot be u-boot itself. This 16k code would need to initialize SDRAM and load another, larger file (e.g. u-boot.bin) from SD/MMC into SDRAM. I don't know whether AT91Bootstrap sources already handle such a situation. Latest Versions you will find on the Atmel Website. Please note that this is not an u-boot issue. The patch "SD/MMC support" for u-boot enables to access SD/MMC from u-boot ONCE it is running. Best Regards, Reinhard

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[U-Boot] [v3 2/2] APM821xx: Add bluestone board support
by tmarri＠apm.com 08 Sep '10

08 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> Add support code for bluestone board wth APM82XXX processor based. This patch includes early board init, misc init, configure EBC, initializes UIC, MAKEALL, board.cfg and MAINTAINERS file. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com -- V1: * Remove "All rights reserved" phrase from headers. * Add empty line which was removed. * Move EBC definititions to bluestone_config.h file * Remove reconfigure_EBC() function. * Remove unused CONFIG_SDRAM16BIT_OFFSET. * Remove unused CONFIG_SDRAM_INFO_EEPROM_ADDR. * Add empty lines in bluestone.c file. * Replacing AC_R | AC_W | AC_X with AC_RWX. * Remove changes to main Makefile * Remove NAND references from config file. * Squash some of the patches. V2: * Missing space before "<". * SDR_AHB_CFG not used, remove. * boot device dfinitions are board specific ? removed. * APM82161_MASK not used, remove * set_mcsr() is already called in ddr init, no need to call here. * removed finding bootdevice function which is not used. * Add spaces in tlbentry() function. * Board early init function is empty remove. * Remove CONFIG_SYS_EXTSRAM_BASE. * Set CONFIG_SYS_FLASH_SIZE to 4MB * Remove CONFIG_SIZE_REDUCE & CONFIG_SECTOR_REDUCE. * Spaces around " >> " . * Correct the phy name CONFIG_M88E1111_PHY to CONFIG_RTL8211CL_PHY. V3: * Missing TLB entry for CONFIG_SYS_BOOT_BASE_ADDR. * Correct multiline comment. * Move CONFIG_SYS_EBC_PB0AP etc to EBC area in the config file. * remove unused CONFIG_RTL8211CL_PHY. * Replace hard coded valued for CONFIG_SYS_EBC_CFG with macro definitions. * board.cfg add the entry in sorted. * use puts() if there is no formating needed. * Change APM82XXX to APM821XX --- MAINTAINERS | 3 + MAKEALL | 1 + board/amcc/bluestone/Makefile | 52 +++++++++++ board/amcc/bluestone/bluestone.c | 111 ++++++++++++++++++++++++ board/amcc/bluestone/config.mk | 40 +++++++++ board/amcc/bluestone/init.S | 59 +++++++++++++ boards.cfg | 1 + include/configs/bluestone.h | 175 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 442 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..284d136 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -253,6 +253,9 @@ Feng Kan <fkan(a)amcc.com> redwood PPC4xx +Tirumala Marri <tmarri(a)apm.com> + bluestone APM821XX + Brad Kemp <Brad.Kemp(a)seranoa.com> ppmc8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index b34ae33..02d5c17 100755 --- a/MAKEALL +++ b/MAKEALL @@ -191,6 +191,7 @@ LIST_4xx=" \ ASH405 \ bamboo \ bamboo_nand \ + bluestone \ bubinga \ CANBT \ canyonlands \ diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile new file mode 100644 index 0000000..41751c8 --- /dev/null +++ b/board/amcc/bluestone/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +SOBJS := init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000..9bf5da2 --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,111 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <apm821xx.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/gpio.h> + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000..e2194e4 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM821XX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000..968f733 --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX | SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) + tlbtab_end diff --git a/boards.cfg b/boards.cfg index 69c6897..f436c66 100644 --- a/boards.cfg +++ b/boards.cfg @@ -186,6 +186,7 @@ t3corp powerpc ppc4xx zeus powerpc ppc4xx acadia powerpc ppc4xx - amcc bamboo powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc bubinga powerpc ppc4xx - amcc ebony powerpc ppc4xx - amcc katmai powerpc ppc4xx - amcc diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h new file mode 100644 index 0000000..40633b1 --- /dev/null +++ b/include/configs/bluestone.h @@ -0,0 +1,175 @@ +/* + * bluestone.h - configuration for Blouestone (APM821XX) + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_APM821XX 1 /* APM821XX series */ +#define CONFIG_HOSTNAME bluestone + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* EBC stuff */ +/* later mapped to this addr */ +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ + +/* EBC Boot Space: 0xFF000000 */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 80 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* SDRAM */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII +#define CONFIG_HAS_ETH0 +/* PHY address, See schematics */ +#define CONFIG_PHY_ADDR 0x1f +/* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_R +/* Include GbE speed/duplex detection */ +#define CONFIG_PHY_GIGE 1 +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * External Bus Controller (EBC) Setup + **/ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_2048PERCLK | \ + EBC_CFG_ATC_HI | \ + EBC_CFG_DTC_HI | \ + EBC_CFG_CTC_HI | \ + EBC_CFG_OEO_PREVIOUS) +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + + +#endif /* __CONFIG_H */ -- 1.6.1.rc3

1 0

[U-Boot] [v3 1/2] APM821xx: Add CPU support
by tmarri＠apm.com 08 Sep '10

08 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- V1: * Squash some of the patches. * add space between "||" and "\". * Add spaces around operators. * Unsigned int to u32. * Add empty line which was removed. * remove warning "unused variable" in cpu_init.c V2: * Removed Defines added to 405ex. V3: * Change APM82XXX to APM821XX * Modify the way cpu id is printed. * Correct inadvertent change. * Sort define list. * Remove comment for get_sys_info(). * Define a symbolic constat ISRAM1_OCM_SIZE. * Create apm821xx.h instead of using ppc440.h --- arch/powerpc/cpu/ppc4xx/cpu.c | 36 ++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 5 +- arch/powerpc/cpu/ppc4xx/speed.c | 76 +++++- arch/powerpc/cpu/ppc4xx/start.S | 11 +- arch/powerpc/cpu/ppc4xx/tlb.c | 2 + arch/powerpc/include/asm/ppc4xx-ebc.h | 4 + arch/powerpc/include/asm/ppc4xx-isram.h | 14 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + include/apm821xx.h | 493 +++++++++++++++++++++++++++++++ include/ppc4xx.h | 11 +- 12 files changed, 645 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065c..2c12907 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -80,7 +80,8 @@ static int pci_async_enabled(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ - !defined(CONFIG_405) && !defined(CONFIG_405EX) + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \ + !defined(CONFIG_APM821XX) int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) @@ -250,6 +251,21 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM821XX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -285,7 +301,7 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM821XX) u32 reg; #endif @@ -301,7 +317,9 @@ int checkcpu (void) puts("CPU: "); get_sys_info(&sys_info); - +#if defined(CONFIG_APM821XX) + puts("APM PowerPC APM821XX"); +#else #if defined(CONFIG_XILINX_440) puts("IBM PowerPC 4"); #else @@ -320,6 +338,7 @@ int checkcpu (void) puts("40"); #endif #endif +#endif switch (pvr) { case PVR_405GP_RB: @@ -598,7 +617,18 @@ int checkcpu (void) puts("GX Rev. A"); strcpy(addstr, "No Security support"); break; +#if defined(CONFIG_APM821XX) + case PVR_APM821XX_RA: + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00200000) + puts("181 Rev. A"); + if (reg & 0x00100000) + strcpy(addstr, "No Security support"); + else + strcpy(addstr, "Security support"); + break; +#endif case PVR_VIRTEX5: puts("x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index b31bd0b..009a35a 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -237,7 +237,8 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) || \ + defined(CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -393,7 +394,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 906face..9538736 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,79 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM821XX) + +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else + /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +380,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 4bad32f..74277fe 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -700,7 +700,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -728,7 +729,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM821XX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -741,7 +743,8 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -752,7 +755,7 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ + ori r1,r1,ISRAM1_SIZE /* ocm size */ mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c index 24a9a9c..9a8964a 100644 --- a/arch/powerpc/cpu/ppc4xx/tlb.c +++ b/arch/powerpc/cpu/ppc4xx/tlb.c @@ -25,7 +25,9 @@ #if defined(CONFIG_440) +#if !defined(CONFIG_APM821XX) #include <ppc440.h> +#endif #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46..2c79118 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -73,6 +73,10 @@ #define EBC_NUM_BANKS 3 #endif +#if defined(CONFIG_APM821XX) +#define EBC_NUM_BANKS 3 +#endif + /* Bank Configuration Register */ #define EBC_BXCR(n) (n) #define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..32e1297 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM821XX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -54,13 +56,19 @@ #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_SIZE 0x0984 /* OCM size 64k */ +#elif defined(CONFIG_APM821XX) +#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ +#endif + /* * L2 Cache */ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 4ec1ef8..8575c4d 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +375,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +423,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d045..3714a0a 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..9cafe85 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/apm821xx.h b/include/apm821xx.h new file mode 100644 index 0000000..fdf7fb7 --- /dev/null +++ b/include/apm821xx.h @@ -0,0 +1,493 @@ +/*----------------------------------------------------------------------------+ +| This source code is dual-licensed. You may use it under the terms of the +| GNU General Public License version 2, or under the license below. +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie(a)fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol(a)fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman(a)fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel(a)fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder(a)fr.ibm.com + * Tirumala Marri, APM/IBM, tmarri(a)apm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __APM821XX_H__ +#define __APM821XX_H__ + +#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + +/**************************************************************************** + * DCRs & Related + ****************************************************************************/ + +/* + * Clocking Controller + */ +/* values for clkcfga register - indirect addressing of these regs */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 + +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + +#define SDR0_SDSTP0 0x0020 /* */ +#define SDR0_SDSTP1 0x0021 /* */ +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_UART2 0x0122 /* UART2 Config */ +#define SDR0_UART3 0x0123 /* UART3 Config */ +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SD0_AMP0 0x0240 /* Override PLB4 prio for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prio for up to 8 masters */ +#define SDR0_PCI0 0x0300 +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_PFC0 0x4100 /* Pin Function 0 */ +#define SDR0_PFC1 0x4101 /* Pin Function 1 */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ + +/* + *Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). + */ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SWOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF + +/* + * External Bus Controller + */ +/* values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR 0x21 /* periph bus error status reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +/* + * On-Chip Buses + */ +/* + * Clocking, Power Management and Chip Control + */ +#define CNTRL_DCR_BASE 0x0b0 + +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System config reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System config reg 1 */ + +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0(RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1(RO) */ + +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg */ + +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 reg */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 reg */ + +/* + * DMA + */ +#define DMA_DCR_BASE 0x100 +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control reg 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control reg 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control reg 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control reg 2 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather cmd register */ + +/* + * Memory Access Layer + */ +#define MAL_DCR_BASE 0x180 +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear)*/ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (rst) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buf int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel actve (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buf int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +/* + * SDR0 Bit Settings + */ + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((u32)(n)) & 0x03) << 29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((u32)(n)) & 0x2FF) << 0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((u32)(n)) >> 0) & 0x2FF) + +#define SDR_SDSTP1_RL_DECODE(x) (((x) & 0x000C0000) >> 18) +#define SDR_SDSTP1_RL_EBC 0x0 +#define SDR_SDSTP1_RL_NDFC 0x2 + +/* ECID */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370 + +/* DDR SDRAM Controller clock (CPR register)*/ +#define SDR0_DDRCE 0x00E0 /* SDR register */ +#define CPR0_DDR2D 0x0100 /* CPR register */ +#define CPR0_DDR2D_DDR2DV_ENCODE(n) ((((u32)(n)) & 0x03) << 25) +#define CPR0_DDR2D_DDR2DV_DECODE(n) ((((u32)(n)) >> 25) & 0x03) + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal async receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal async receiver/ + transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter intgrated circuit 0 */ +#define SDR0_SRST0_IIC1 0x01000000 /* Inter intgrated circuit 1 */ +#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM mem controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power mgmt */ +#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal intr ctrller 1 */ +#define SDR0_SRST0_SRAM 0x00002000 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UIC2 0x00001000 /* Universal intr ctrller 2 */ +#define SDR0_SRST0_UIC3 0x00000800 /* Universal intr ctrller 3 */ +#define SDR0_SRST0_OCM 0x00000400 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ + transmitter 2 */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ +#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ + transmitter 3 */ +#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ + +#define SDR0_SRST1 0x201 +#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ +#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ +#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ +#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ +#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ +#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access + controller 0 */ +#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access + controller 1 */ +#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access + controller 2 */ +#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access + controller 3 */ +#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ +#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ +#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ +#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ +#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, + serdes */ +#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid PCS */ +#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ +#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ +#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ +#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ +#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ +#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ +#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ +#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ +#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ +#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ +#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ +#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ +#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ +#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ + +/* + * Clocking + */ +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL,1 = CPU,5=PerClk*/ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor src */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ +#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ +#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ +#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Div */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID) +#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID) +#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND) +#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS) +#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID) +#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) +#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE) +#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER) +#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE) +#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST) +#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0) +#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1) +#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2) +#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3) +#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4) +#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5) +#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS) +#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID) +#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID) +#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS) +#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST) +#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035) +#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036) +#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038) +#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE) +#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN) +#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ +#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ +#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ +#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ +#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by ctrl pkt */ +#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the txmitted fr*/ +#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ +#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ +#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-max bytes txmitted */ +#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes txmitted */ +#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes txmitted */ +#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes txmitted */ +#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes txmitted */ +#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes txmitted */ +#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ +#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ +#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ +#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ +#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ +#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ +#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ +#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ +#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ +#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ + +#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT) +#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT) + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) +#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) +#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) +#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) +#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) +#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) +#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) +#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) +#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) +#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) +#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) + +#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) +#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) +#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) +#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) +#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) +#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) +#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) +#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) +#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) + +#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) + +/***************************************************************************** + * GPIO macro register define + *****************************************************************************/ + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) + +#define GPIO0_OR (GPIO0_BASE+0x0) +#define GPIO0_TCR (GPIO0_BASE+0x4) +#define GPIO0_OSRL (GPIO0_BASE+0x8) +#define GPIO0_OSRH (GPIO0_BASE+0xC) +#define GPIO0_TSRL (GPIO0_BASE+0x10) +#define GPIO0_TSRH (GPIO0_BASE+0x14) +#define GPIO0_ODR (GPIO0_BASE+0x18) +#define GPIO0_IR (GPIO0_BASE+0x1C) +#define GPIO0_RR1 (GPIO0_BASE+0x20) +#define GPIO0_RR2 (GPIO0_BASE+0x24) +#define GPIO0_RR3 (GPIO0_BASE+0x28) +#define GPIO0_ISR1L (GPIO0_BASE+0x30) +#define GPIO0_ISR1H (GPIO0_BASE+0x34) +#define GPIO0_ISR2L (GPIO0_BASE+0x38) +#define GPIO0_ISR2H (GPIO0_BASE+0x3C) +#define GPIO0_ISR3L (GPIO0_BASE+0x40) +#define GPIO0_ISR3H (GPIO0_BASE+0x44) + +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#endif /* __APM821XX_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ee30a4c..06230bd 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -44,14 +44,15 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define CONFIG_NAND_NDFC #endif @@ -61,7 +62,7 @@ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define PLB_ARBITER_BASE 0x80 @@ -99,7 +100,9 @@ #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ -#if defined(CONFIG_440) +#if defined(CONFIG_APM821XX) +#include <apm821xx.h> +#elif defined(CONFIG_440) #include <ppc440.h> #else #include <ppc405.h> -- 1.6.1.rc3

1 0

[U-Boot] [PATCH] Add basic support for FriendlyARM MINI6410 development board
by Alex Ling 08 Sep '10

08 Sep '10

This patch adds basic support for FriendlyARM MINI6410 development board (a Chinese clone of Samsung SMDK6410) Signed-off-by: Alex Ling <kasimling(a)gmail.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 14 ++ board/samsung/mini6410/.gitignore | 5 + board/samsung/mini6410/Makefile | 57 +++++ board/samsung/mini6410/config.mk | 35 +++ board/samsung/mini6410/lowlevel_init.S | 310 ++++++++++++++++++++++++++++ board/samsung/mini6410/mini6410.c | 86 ++++++++ board/samsung/mini6410/u-boot-nand.lds | 62 ++++++ include/configs/mini6410.h | 296 ++++++++++++++++++++++++++ nand_spl/board/samsung/mini6410/Makefile | 112 ++++++++++ nand_spl/board/samsung/mini6410/config.mk | 41 ++++ nand_spl/board/samsung/mini6410/u-boot.lds | 61 ++++++ 13 files changed, 1084 insertions(+), 0 deletions(-) create mode 100644 board/samsung/mini6410/.gitignore create mode 100644 board/samsung/mini6410/Makefile create mode 100644 board/samsung/mini6410/config.mk create mode 100644 board/samsung/mini6410/lowlevel_init.S create mode 100644 board/samsung/mini6410/mini6410.c create mode 100644 board/samsung/mini6410/u-boot-nand.lds create mode 100644 include/configs/mini6410.h create mode 100644 nand_spl/board/samsung/mini6410/Makefile create mode 100644 nand_spl/board/samsung/mini6410/config.mk create mode 100644 nand_spl/board/samsung/mini6410/u-boot.lds diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..e858c5c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -815,6 +815,10 @@ Alex Z lart SA1100 dnp1110 SA1110 +Alex Ling <kasimling(a)gmail.com> + + MINI6410 ARM1176JZF-S (S3C6410) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index b34ae33..e3e3def 100755 --- a/MAKEALL +++ b/MAKEALL @@ -644,6 +644,7 @@ LIST_ARM11=" \ qong \ smdk6400 \ tnetv107x_evm \ + mini6410 \ " ######################################################################### diff --git a/Makefile b/Makefile index 4f1cb1b..200a365 100644 --- a/Makefile +++ b/Makefile @@ -2235,6 +2235,20 @@ smdk6400_config : unconfig @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk +mini6410_noUSB_config \ +mini6410_config : unconfig + @mkdir -p $(obj)include $(obj)board/samsung/mini6410 + @mkdir -p $(obj)nand_spl/board/samsung/mini6410 + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + @if [ -z "$(findstring mini6410_noUSB_config,$@)" ]; then \ + echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/mini6410/config.tmp;\ + else \ + echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/mini6410/config.tmp;\ + fi + @$(MKCONFIG) mini6410 arm arm1176 mini6410 samsung s3c64xx + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + #======================================================================== # MIPS #======================================================================== diff --git a/board/samsung/mini6410/.gitignore b/board/samsung/mini6410/.gitignore new file mode 100644 index 0000000..25ab492 --- /dev/null +++ b/board/samsung/mini6410/.gitignore @@ -0,0 +1,5 @@ +# +# Generated files +# + +/config.tmp diff --git a/board/samsung/mini6410/Makefile b/board/samsung/mini6410/Makefile new file mode 100644 index 0000000..ef86f48 --- /dev/null +++ b/board/samsung/mini6410/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# (C) Copyright 2010 +# Alex Ling, <kasimling(a)gmail.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := mini6410.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(SOBJS) $(OBJS) + $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/mini6410/config.mk b/board/samsung/mini6410/config.mk new file mode 100644 index 0000000..7e9177f --- /dev/null +++ b/board/samsung/mini6410/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# (C) Copyright 2010 +# Alex Ling, <kasimling(a)gmail.com> +# +# FriendlyARM MINI6410 board with mDirac3 (ARM1176) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG + +# On MINI6410 we use the 128 MB SDRAM bank at +# +# 0x50000000 to 0x58000000 +# +# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000 +# +# we load ourselves to 0x57e00000 without MMU +# with MMU, load address is changed to 0xc7e00000 +# +# download area is 0x5000c000 + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef CONFIG_NAND_SPL +TEXT_BASE = $(RAM_TEXT) +else +TEXT_BASE = 0 +endif + +LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot-nand.lds diff --git a/board/samsung/mini6410/lowlevel_init.S b/board/samsung/mini6410/lowlevel_init.S new file mode 100644 index 0000000..c00d0ab --- /dev/null +++ b/board/samsung/mini6410/lowlevel_init.S @@ -0,0 +1,310 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * (C) Copyright 2010 + * Alex Ling, <kasimling(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> + +#include <asm/arch/s3c6400.h> + +#ifdef CONFIG_SERIAL1 +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) +#elif defined(CONFIG_SERIAL2) +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) +#else +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) +#endif + +_TEXT_BASE: + .word TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + mov r12, lr + + /* Disable Watchdog */ + ldr r0, =0x7e000000 @0x7e004000 + orr r0, r0, #0x4000 + mov r1, #0 + str r1, [r0] + + /* External interrupt pending clear */ + ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ + ldr r1, [r0] + str r1, [r0] + + ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 + ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 + + /* Disable all interrupts (VIC0 and VIC1) */ + mvn r3, #0x0 + str r3, [r0, #oINTMSK] + str r3, [r1, #oINTMSK] + + /* Set all interrupts as IRQ */ + mov r3, #0x0 + str r3, [r0, #oINTMOD] + str r3, [r1, #oINTMOD] + + /* Pending Interrupt Clear */ + mov r3, #0x0 + str r3, [r0, #oVECTADDR] + str r3, [r1, #oVECTADDR] + + /* init system clock */ + bl system_clock_init + +#ifndef CONFIG_NAND_SPL + /* for UART */ + bl uart_asm_init +#endif + +#ifdef CONFIG_BOOT_NAND + /* simple init for NAND */ + bl nand_asm_init +#endif + + /* Memory subsystem address 0x7e00f120 */ + ldr r0, =ELFIN_MEM_SYS_CFG + + /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ + mov r1, #S3C64XX_MEM_SYS_CFG_NAND + str r1, [r0] + + bl mem_ctrl_asm_init + +/* Wakeup support. Don't know if it's going to be used, untested. */ + ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) + ldr r1, [r0] + bic r1, r1, #0xfffffff7 + cmp r1, #0x8 + beq wakeup_reset + +1: + mov lr, r12 + mov pc, lr + +wakeup_reset: + + /* Clear wakeup status register */ + ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) + ldr r1, [r0] + str r1, [r0] + + /* Load return address and jump to kernel */ + ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) + /* r1 = physical address of s3c6400_cpu_resume function */ + ldr r1, [r0] + /* Jump to kernel (sleep-s3c6400.S) */ + mov pc, r1 + nop + nop +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ + +#ifdef CONFIG_SYNC_MODE + ldr r1, [r0, #OTHERS_OFFSET] + mov r2, #0x40 + orr r1, r1, r2 + str r1, [r0, #OTHERS_OFFSET] + + nop + nop + nop + nop + nop + + ldr r2, =0x80 + orr r1, r1, r2 + str r1, [r0, #OTHERS_OFFSET] + +check_syncack: + ldr r1, [r0, #OTHERS_OFFSET] + ldr r2, =0xf00 + and r1, r1, r2 + cmp r1, #0xf00 + bne check_syncack +#else /* ASYNC Mode */ + nop + nop + nop + nop + nop + + /* + * This was unconditional in original Samsung sources, but it doesn't + * seem to make much sense on S3C6400. + */ +#ifndef CONFIG_S3C6400 + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0xC0 + orr r1, r1, #0x40 + str r1, [r0, #OTHERS_OFFSET] + +wait_for_async: + ldr r1, [r0, #OTHERS_OFFSET] + and r1, r1, #0xf00 + cmp r1, #0x0 + bne wait_for_async +#endif + + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0x40 + str r1, [r0, #OTHERS_OFFSET] +#endif + + mov r1, #0xff00 + orr r1, r1, #0xff + str r1, [r0, #APLL_LOCK_OFFSET] + str r1, [r0, #MPLL_LOCK_OFFSET] + + /* Set Clock Divider */ + ldr r1, [r0, #CLK_DIV0_OFFSET] + bic r1, r1, #0x30000 + bic r1, r1, #0xff00 + bic r1, r1, #0xff + ldr r2, =CLK_DIV_VAL + orr r1, r1, r2 + str r1, [r0, #CLK_DIV0_OFFSET] + + ldr r1, =APLL_VAL + str r1, [r0, #APLL_CON_OFFSET] + ldr r1, =MPLL_VAL + str r1, [r0, #MPLL_CON_OFFSET] + + /* FOUT of EPLL is 96MHz */ + ldr r1, =0x200203 + str r1, [r0, #EPLL_CON0_OFFSET] + ldr r1, =0x0 + str r1, [r0, #EPLL_CON1_OFFSET] + + /* APLL, MPLL, EPLL select to Fout */ + ldr r1, [r0, #CLK_SRC_OFFSET] + orr r1, r1, #0x7 + str r1, [r0, #CLK_SRC_OFFSET] + + /* wait at least 200us to stablize all clock */ + mov r1, #0x10000 +1: subs r1, r1, #1 + bne 1b + + /* Synchronization for VIC port */ +#if defined(CONFIG_SYNC_MODE) + ldr r1, [r0, #OTHERS_OFFSET] + orr r1, r1, #0x20 + str r1, [r0, #OTHERS_OFFSET] +#elif !defined(CONFIG_S3C6400) + /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */ + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0x20 + str r1, [r0, #OTHERS_OFFSET] +#endif + mov pc, lr + + +#ifndef CONFIG_NAND_SPL +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* set GPIO to enable UART */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x220022 + str r1, [r0, #GPACON_OFFSET] + mov pc, lr +#endif + +#ifdef CONFIG_BOOT_NAND +/* + * NAND Interface init for SMDK6400 + */ +nand_asm_init: + ldr r0, =ELFIN_NAND_BASE + ldr r1, [r0, #NFCONF_OFFSET] + orr r1, r1, #0x70 + orr r1, r1, #0x7700 + str r1, [r0, #NFCONF_OFFSET] + + ldr r1, [r0, #NFCONT_OFFSET] + orr r1, r1, #0x07 + str r1, [r0, #NFCONT_OFFSET] + + mov pc, lr +#endif + +#ifdef CONFIG_ENABLE_MMU +/* + * MMU Table for MINI6410 + */ + + /* form a first-level section entry */ +.macro FL_SECTION_ENTRY base,ap,d,c,b + .word (\base << 20) | (\ap << 10) | \ + (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1) +.endm + +.section .mmudata, "a" + .align 14 + /* the following alignment creates the mmu table at address 0x4000. */ + .globl mmu_table +mmu_table: + .set __base, 0 + /* 1:1 mapping for debugging */ + .rept 0xA00 + FL_SECTION_ENTRY __base, 3, 0, 0, 0 + .set __base, __base + 1 + .endr + + /* access is not allowed. */ + .rept 0xC00 - 0xA00 + .word 0x00000000 + .endr + + /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */ + .set __base, 0x500 + .rept 0xC80 - 0xC00 + FL_SECTION_ENTRY __base, 3, 0, 1, 1 + .set __base, __base + 1 + .endr + + /* access is not allowed. */ + .rept 0x1000 - 0xc80 + .word 0x00000000 + .endr +#endif diff --git a/board/samsung/mini6410/mini6410.c b/board/samsung/mini6410/mini6410.c new file mode 100644 index 0000000..0db6f76 --- /dev/null +++ b/board/samsung/mini6410/mini6410.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * (C) Copyright 2010 + * Alex Ling, <kasimling(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/s3c6400.h> + +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" + : "=r" (loops) : "0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = MACH_TYPE; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("Board: MINI6410\n"); + return 0; +} +#endif + +#ifdef CONFIG_ENABLE_MMU +ulong virt_to_phy_mini6410(ulong addr) +{ + if ((0xc0000000 <= addr) && (addr < 0xc8000000)) + return addr - 0xc0000000 + 0x50000000; + else + printf("do not support this address : %08lx\n", addr); + + return addr; +} +#endif diff --git a/board/samsung/mini6410/u-boot-nand.lds b/board/samsung/mini6410/u-boot-nand.lds new file mode 100644 index 0000000..29a4f61 --- /dev/null +++ b/board/samsung/mini6410/u-boot-nand.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm1176/start.o (.text) + arch/arm/cpu/arm1176/s3c64xx/cpu_init.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + .mmudata : { *(.mmudata) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/include/configs/mini6410.h b/include/configs/mini6410.h new file mode 100644 index 0000000..3995970 --- /dev/null +++ b/include/configs/mini6410.h @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * Gary Jennejohn <garyj(a)denx.de> + * David Mueller <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2010 + * Alex Ling, <kasimling(a)gmail.com> + * + * Configuation settings for the FriendlyARM MINI6410 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */ +#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ +#define CONFIG_MINI6410 1 /* on a FriendlyARM MINI6410 Board */ + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x70000000 +#define CONFIG_PERIPORT_SIZE 0x13 + +#define CONFIG_SYS_SDRAM_BASE 0x50000000 + +/* input clock of PLL: SMDK6400 has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000) +#define CONFIG_ENABLE_MMU +#endif + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +/* + * Architecture magic and machine type + */ +#define MACH_TYPE 2520 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on MINI6410 */ + +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_CMDLINE_EDITING + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NAND +#if defined(CONFIG_BOOT_ONENAND) +#define CONFIG_CMD_ONENAND +#endif +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MINI6410 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */ + +/********************************** + Support Clock Settings + ********************************** + Setting SYNC ASYNC + ---------------------------------- + 667_133_66 X O + 533_133_66 O O + 400_133_66 X O + 400_100_50 O O + **********************************/ + +/*#define CONFIG_CLK_667_133_66*/ +#define CONFIG_CLK_533_133_66 +/* +#define CONFIG_CLK_400_100_50 +#define CONFIG_CLK_400_133_66 +#define CONFIG_SYNC_MODE +*/ + +/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* + * MINI6410 board specific data + */ + +#define CONFIG_IDENT_STRING " for MINI6410" + +/* base address for uboot */ +#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000) +/* total memory available to uboot */ +#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) + +/* Put environment copies after the end of U-Boot owned RAM */ +#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) + +#ifdef CONFIG_ENABLE_MMU +#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 +#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ + "bootm 0xc0018000" +#else +#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE +#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ + "bootm 0x50018000" +#endif + +/* NAND U-Boot load and start address */ +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000) + +#define CONFIG_ENV_OFFSET 0x0040000 + +/* NAND configuration */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x70200010 +#define CONFIG_SYS_S3C_NAND_HWECC + +#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CONFIG_SYS_NAND_WP 1 +#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */ +#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */ + +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ + +#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ +#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ + +/* NAND chip page size */ +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +/* NAND chip block size */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND chip page per block count */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +/* Location of the bad-block label */ +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +/* Extra address cycle for > 128MiB */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */ +#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE +/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */ +#define CONFIG_SYS_NAND_ECCBYTES 4 +/* Number of ECC-blocks per NAND page */ +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) +/* Size of a single OOB region */ +#define CONFIG_SYS_NAND_OOBSIZE 64 +/* Number of ECC bytes per page */ +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) +/* ECC byte positions */ +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63} + +/* Boot configuration (define only one of next 3) */ +#define CONFIG_BOOT_NAND +/* None of these are currently implemented. Left from the original Samsung + * version for reference +#define CONFIG_BOOT_NOR +#define CONFIG_BOOT_MOVINAND +#define CONFIG_BOOT_ONENAND +*/ + +#define CONFIG_NAND +#define CONFIG_NAND_S3C64XX +/* Unimplemented or unsupported. See comment above. +#define CONFIG_ONENAND +#define CONFIG_MOVINAND +*/ + +/* Settings as above boot configuration */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_BOOTARGS "console=ttySAC,115200" + +#if !defined(CONFIG_ENABLE_MMU) +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_S3C64XX +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 + +#define CONFIG_USB_STORAGE 1 +#endif +#define CONFIG_DOS_PARTITION 1 + +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU) +# error "usb_ohci.c is currently broken with MMU enabled." +#endif + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/samsung/mini6410/Makefile b/nand_spl/board/samsung/mini6410/Makefile new file mode 100644 index 0000000..bdf7b43 --- /dev/null +++ b/nand_spl/board/samsung/mini6410/Makefile @@ -0,0 +1,112 @@ +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# (C) Copyright 2010 +# Alex Ling, <kasimling(a)gmail.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o cpu_init.o lowlevel_init.o +COBJS = nand_boot.o nand_ecc.o s3c64xx.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@ + +# from SoC directory +$(obj)cpu_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@ + +# from board directory +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/board/samsung/mini6410/lowlevel_init.S $@ + +# from nand_spl directory +$(obj)nand_boot.c: + @rm -f $@ + @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@ + +# from drivers/mtd/nand directory +$(obj)nand_ecc.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@ + +$(obj)s3c64xx.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@ + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/samsung/mini6410/config.mk b/nand_spl/board/samsung/mini6410/config.mk new file mode 100644 index 0000000..556fcb3 --- /dev/null +++ b/nand_spl/board/samsung/mini6410/config.mk @@ -0,0 +1,41 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# FriendlyARM MINI6410 development board, based on +# Samsung S3C64xx Reference Platform (smdk6400) board + +# TEXT_BASE for SPL: +# +# On S3C64xx platforms the SPL is located in SRAM at 0. +# +# TEXT_BASE = 0 + +include $(TOPDIR)/board/$(BOARDDIR)/config.mk + +# PAD_TO used to generate a 4kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 4096 +PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096]) + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/nand_spl/board/samsung/mini6410/u-boot.lds b/nand_spl/board/samsung/mini6410/u-boot.lds new file mode 100644 index 0000000..3ac6aa1 --- /dev/null +++ b/nand_spl/board/samsung/mini6410/u-boot.lds @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + cpu_init.o (.text) + nand_boot.o (.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) . = ALIGN(4); } + _end = .; +} -- 1.7.0.4

3 2

[U-Boot] [PATCH] display_buffer: fix misaligned buffer
by Reinhard Meyer 08 Sep '10

08 Sep '10

Signed-off-by: Reinhard Meyer <u-boot(a)emk-elektronik.de> --- lib/display_options.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/lib/display_options.c b/lib/display_options.c index 20319e6..9048a8a 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -101,7 +101,7 @@ void print_size(unsigned long long size, const char *s) #define DEFAULT_LINE_LENGTH_BYTES (16) int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen) { - uint8_t linebuf[MAX_LINE_LENGTH_BYTES + 1]; + uint32_t linebuf[MAX_LINE_LENGTH_BYTES/4 + 1]; uint32_t *uip = (void*)linebuf; uint16_t *usp = (void*)linebuf; uint8_t *ucp = (void*)linebuf; -- 1.5.6.5

6 22

[U-Boot] Pull request: u-boot-atmel/avr32
by Reinhard Meyer 08 Sep '10

08 Sep '10

The following changes since commit bd2313078114c4b44c4a5ce149af43bcb7fc8854: Wolfgang Denk (1): Merge branch 'master' of ssh://gemini/home/wd/git/u-boot/master are available in the git repository at: git://git.denx.de/u-boot-atmel avr32 Haavard Skinnemoen (3): avr32: Print unrelocated PC on exception avr32: Use uncached() macro to get an address for SDRAM init avr32: Add simple paging support arch/avr32/cpu/at32ap700x/Makefile | 2 +- arch/avr32/cpu/at32ap700x/mmu.c | 78 ++++++++++++++++++++ arch/avr32/cpu/exception.c | 3 +- arch/avr32/cpu/start.S | 19 +++-- arch/avr32/include/asm/arch-at32ap700x/addrspace.h | 5 +- arch/avr32/include/asm/arch-at32ap700x/mmu.h | 66 +++++++++++++++++ arch/avr32/lib/board.c | 4 + board/atmel/atngw100/atngw100.c | 19 ++++- board/atmel/atstk1000/atstk1000.c | 19 ++++- board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 19 ++++- board/mimc/mimc200/mimc200.c | 24 +++++- board/miromico/hammerhead/hammerhead.c | 19 ++++- include/configs/atngw100.h | 3 + include/configs/atstk1002.h | 3 + include/configs/atstk1003.h | 3 + include/configs/atstk1004.h | 3 + include/configs/atstk1006.h | 3 + include/configs/favr-32-ezkit.h | 3 + include/configs/hammerhead.h | 3 + include/configs/mimc200.h | 3 + 20 files changed, 274 insertions(+), 27 deletions(-) create mode 100644 arch/avr32/cpu/at32ap700x/mmu.c create mode 100644 arch/avr32/include/asm/arch-at32ap700x/mmu.h

2 1