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September 2010

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[U-Boot] [PATCH] cp/cmp: Add WATCHDOG_RESET in copy and compare loop
by Stefan Roese 09 Sep '10

09 Sep '10

On some boards with a very short watchdog timeout, the "cp" and "cmp" commands may reset the board. This patch adds some watchdog resets inside the loops. Otherwise for example the lwmon5 board will reset while doing something like this: => cp.b fc000000 1000000 100000 Signed-off-by: Stefan Roese <sr(a)denx.de> --- common/cmd_mem.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 44834ea..c426997 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -337,6 +337,10 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ngood++; addr1 += size; addr2 += size; + + /* reset watchdog from time to time */ + if ((count % 1000) == 0) + WATCHDOG_RESET(); } printf("Total of %ld %s%s were the same\n", @@ -447,6 +451,10 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) *((u_char *)dest) = *((u_char *)addr); addr += size; dest += size; + + /* reset watchdog from time to time */ + if ((count % 1000) == 0) + WATCHDOG_RESET(); } return 0; } -- 1.7.2.2

3 3

[U-Boot] [PATCH v3 1/2] APM821xx: Add CPU support
by tmarri＠apm.com 09 Sep '10

09 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- V2: * Removed Defines added to 405ex. V3: * Change APM82XXX to APM821XX * Modify the way cpu id is printed. * Correct inadvertent change. * Sort define list. * Remove comment for get_sys_info(). * Define a symbolic constat ISRAM1_OCM_SIZE. * Create apm821xx.h instead of using ppc440.h * Correct multiline comment. --- arch/powerpc/cpu/ppc4xx/cpu.c | 36 ++- arch/powerpc/cpu/ppc4xx/cpu_init.c | 5 +- arch/powerpc/cpu/ppc4xx/speed.c | 76 +++++- arch/powerpc/cpu/ppc4xx/start.S | 11 +- arch/powerpc/cpu/ppc4xx/tlb.c | 2 + arch/powerpc/include/asm/ppc4xx-ebc.h | 4 + arch/powerpc/include/asm/ppc4xx-isram.h | 14 +- arch/powerpc/include/asm/ppc4xx-sdram.h | 12 +- arch/powerpc/include/asm/ppc4xx-uic.h | 5 +- arch/powerpc/include/asm/processor.h | 1 + include/apm821xx.h | 493 +++++++++++++++++++++++++++++++ include/ppc4xx.h | 11 +- 12 files changed, 645 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065c..2c12907 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -80,7 +80,8 @@ static int pci_async_enabled(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ - !defined(CONFIG_405) && !defined(CONFIG_405EX) + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \ + !defined(CONFIG_APM821XX) int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) @@ -250,6 +251,21 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM821XX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -285,7 +301,7 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM821XX) u32 reg; #endif @@ -301,7 +317,9 @@ int checkcpu (void) puts("CPU: "); get_sys_info(&sys_info); - +#if defined(CONFIG_APM821XX) + puts("APM PowerPC APM821XX"); +#else #if defined(CONFIG_XILINX_440) puts("IBM PowerPC 4"); #else @@ -320,6 +338,7 @@ int checkcpu (void) puts("40"); #endif #endif +#endif switch (pvr) { case PVR_405GP_RB: @@ -598,7 +617,18 @@ int checkcpu (void) puts("GX Rev. A"); strcpy(addstr, "No Security support"); break; +#if defined(CONFIG_APM821XX) + case PVR_APM821XX_RA: + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00200000) + puts("181 Rev. A"); + if (reg & 0x00100000) + strcpy(addstr, "No Security support"); + else + strcpy(addstr, "Security support"); + break; +#endif case PVR_VIRTEX5: puts("x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index b31bd0b..009a35a 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -237,7 +237,8 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if !defined(CONFIG_APM821XX) && (defined(CONFIG_405EP) || \ + defined(CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -393,7 +394,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 906face..9538736 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,79 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM821XX) + +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else + /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +380,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 4bad32f..74277fe 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -700,7 +700,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -728,7 +729,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM821XX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -741,7 +743,8 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -752,7 +755,7 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ + ori r1,r1,ISRAM1_SIZE /* ocm size */ mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c index 24a9a9c..9a8964a 100644 --- a/arch/powerpc/cpu/ppc4xx/tlb.c +++ b/arch/powerpc/cpu/ppc4xx/tlb.c @@ -25,7 +25,9 @@ #if defined(CONFIG_440) +#if !defined(CONFIG_APM821XX) #include <ppc440.h> +#endif #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46..2c79118 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -73,6 +73,10 @@ #define EBC_NUM_BANKS 3 #endif +#if defined(CONFIG_APM821XX) +#define EBC_NUM_BANKS 3 +#endif + /* Bank Configuration Register */ #define EBC_BXCR(n) (n) #define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17)) diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..32e1297 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM821XX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -54,13 +56,19 @@ #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_SIZE 0x0984 /* OCM size 64k */ +#elif defined(CONFIG_APM821XX) +#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ +#endif + /* * L2 Cache */ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 4ec1ef8..8575c4d 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +375,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +423,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d045..3714a0a 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..9cafe85 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/apm821xx.h b/include/apm821xx.h new file mode 100644 index 0000000..fdf7fb7 --- /dev/null +++ b/include/apm821xx.h @@ -0,0 +1,493 @@ +/*----------------------------------------------------------------------------+ +| This source code is dual-licensed. You may use it under the terms of the +| GNU General Public License version 2, or under the license below. +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie(a)fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol(a)fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman(a)fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel(a)fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder(a)fr.ibm.com + * Tirumala Marri, APM/IBM, tmarri(a)apm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __APM821XX_H__ +#define __APM821XX_H__ + +#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + +/**************************************************************************** + * DCRs & Related + ****************************************************************************/ + +/* + * Clocking Controller + */ +/* values for clkcfga register - indirect addressing of these regs */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 + +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + +#define SDR0_SDSTP0 0x0020 /* */ +#define SDR0_SDSTP1 0x0021 /* */ +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_UART2 0x0122 /* UART2 Config */ +#define SDR0_UART3 0x0123 /* UART3 Config */ +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SD0_AMP0 0x0240 /* Override PLB4 prio for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prio for up to 8 masters */ +#define SDR0_PCI0 0x0300 +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_PFC0 0x4100 /* Pin Function 0 */ +#define SDR0_PFC1 0x4101 /* Pin Function 1 */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ + +/* + *Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). + */ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SWOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF + +/* + * External Bus Controller + */ +/* values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR 0x21 /* periph bus error status reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +/* + * On-Chip Buses + */ +/* + * Clocking, Power Management and Chip Control + */ +#define CNTRL_DCR_BASE 0x0b0 + +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System config reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System config reg 1 */ + +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0(RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1(RO) */ + +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg */ + +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 reg */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 reg */ + +/* + * DMA + */ +#define DMA_DCR_BASE 0x100 +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control reg 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control reg 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control reg 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control reg 2 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather cmd register */ + +/* + * Memory Access Layer + */ +#define MAL_DCR_BASE 0x180 +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear)*/ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (rst) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buf int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel actve (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buf int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +/* + * SDR0 Bit Settings + */ + +#define SDR0_DDR0 0x00E1 +#define SDR0_DDR0_DDRM_ENCODE(n) ((((u32)(n)) & 0x03) << 29) +#define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) +#define SDR0_DDR0_TUNE_ENCODE(n) ((((u32)(n)) & 0x2FF) << 0) +#define SDR0_DDR0_TUNE_DECODE(n) ((((u32)(n)) >> 0) & 0x2FF) + +#define SDR_SDSTP1_RL_DECODE(x) (((x) & 0x000C0000) >> 18) +#define SDR_SDSTP1_RL_EBC 0x0 +#define SDR_SDSTP1_RL_NDFC 0x2 + +/* ECID */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 +#define SDR0_AHB_CFG 0x370 + +/* DDR SDRAM Controller clock (CPR register)*/ +#define SDR0_DDRCE 0x00E0 /* SDR register */ +#define CPR0_DDR2D 0x0100 /* CPR register */ +#define CPR0_DDR2D_DDR2DV_ENCODE(n) ((((u32)(n)) & 0x03) << 25) +#define CPR0_DDR2D_DDR2DV_DECODE(n) ((((u32)(n)) >> 25) & 0x03) + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal async receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal async receiver/ + transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter intgrated circuit 0 */ +#define SDR0_SRST0_IIC1 0x01000000 /* Inter intgrated circuit 1 */ +#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM mem controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power mgmt */ +#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal intr ctrller 1 */ +#define SDR0_SRST0_SRAM 0x00002000 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UIC2 0x00001000 /* Universal intr ctrller 2 */ +#define SDR0_SRST0_UIC3 0x00000800 /* Universal intr ctrller 3 */ +#define SDR0_SRST0_OCM 0x00000400 /* Universal intr ctrller 0 */ +#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ + transmitter 2 */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ +#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ + transmitter 3 */ +#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ + +#define SDR0_SRST1 0x201 +#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ +#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ +#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ +#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ +#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ +#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access + controller 0 */ +#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access + controller 1 */ +#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access + controller 2 */ +#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access + controller 3 */ +#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ +#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ +#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ +#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ +#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, + serdes */ +#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid PCS */ +#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ +#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ +#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ +#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ +#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ +#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ +#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ +#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ +#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ +#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ +#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ +#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ +#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ +#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ + +/* + * Clocking + */ +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL,1 = CPU,5=PerClk*/ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor src */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ +#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ +#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ +#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Div */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID) +#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID) +#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND) +#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS) +#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID) +#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) +#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE) +#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER) +#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE) +#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST) +#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0) +#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1) +#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2) +#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3) +#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4) +#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5) +#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS) +#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID) +#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID) +#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS) +#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST) +#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035) +#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036) +#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038) +#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE) +#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN) +#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ +#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ +#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ +#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ +#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by ctrl pkt */ +#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the txmitted fr*/ +#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ +#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ +#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-max bytes txmitted */ +#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes txmitted */ +#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes txmitted */ +#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes txmitted */ +#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes txmitted */ +#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes txmitted */ +#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ +#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ +#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ +#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ +#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ +#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ +#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ +#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ +#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ +#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ + +#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT) +#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT) + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) +#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) +#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) +#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) +#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) +#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) +#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) +#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) +#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) +#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) +#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) + +#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) +#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) +#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) +#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) +#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) +#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) +#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) +#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) +#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) + +#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) + +/***************************************************************************** + * GPIO macro register define + *****************************************************************************/ + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) + +#define GPIO0_OR (GPIO0_BASE+0x0) +#define GPIO0_TCR (GPIO0_BASE+0x4) +#define GPIO0_OSRL (GPIO0_BASE+0x8) +#define GPIO0_OSRH (GPIO0_BASE+0xC) +#define GPIO0_TSRL (GPIO0_BASE+0x10) +#define GPIO0_TSRH (GPIO0_BASE+0x14) +#define GPIO0_ODR (GPIO0_BASE+0x18) +#define GPIO0_IR (GPIO0_BASE+0x1C) +#define GPIO0_RR1 (GPIO0_BASE+0x20) +#define GPIO0_RR2 (GPIO0_BASE+0x24) +#define GPIO0_RR3 (GPIO0_BASE+0x28) +#define GPIO0_ISR1L (GPIO0_BASE+0x30) +#define GPIO0_ISR1H (GPIO0_BASE+0x34) +#define GPIO0_ISR2L (GPIO0_BASE+0x38) +#define GPIO0_ISR2H (GPIO0_BASE+0x3C) +#define GPIO0_ISR3L (GPIO0_BASE+0x40) +#define GPIO0_ISR3H (GPIO0_BASE+0x44) + +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#endif /* __APM821XX_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ee30a4c..06230bd 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -44,14 +44,15 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define CONFIG_NAND_NDFC #endif @@ -61,7 +62,7 @@ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define PLB_ARBITER_BASE 0x80 @@ -99,7 +100,9 @@ #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ -#if defined(CONFIG_440) +#if defined(CONFIG_APM821XX) +#include <apm821xx.h> +#elif defined(CONFIG_440) #include <ppc440.h> #else #include <ppc405.h> -- 1.6.1.rc3

5 6

[U-Boot] [PATCH] MX51: Update responsible for mx51evk
by Stefano Babic 09 Sep '10

09 Sep '10

Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- MAINTAINERS | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..6699393 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -152,10 +152,6 @@ Dave Ellis <DGE(a)sixnetio.com> SXNI855T MPC8xx -Fred Fan <fanyefeng(a)gmail.com> - - mx51evk i.MX51 - Thomas Frieden <ThomasF(a)hyperion-entertainment.com> AmigaOneG3SE MPC7xx @@ -549,6 +545,7 @@ Stefano Babic <sbabic(a)denx.de> polaris xscale trizepsiv xscale + mx51evk i.MX51 Dirk Behme <dirk.behme(a)gmail.com> -- 1.6.3.3

2 1

[U-Boot] Please Pull u-boot-ti/master
by s-paulraj＠ti.com 09 Sep '10

09 Sep '10

Wolfgang, Please pull u-boot-ti/master This pull request comprises of a NAND patch which has been ACK'ed by Scott Wood. Also I ran MAKEALL for all ARM V7 boards and saw no issues. Thanks, Sandeep The following changes since commit 2df0e6fc6b71448e1752e4ce1d5577d8977f3e5e: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mips are available in the git repository at: git://git.denx.de/u-boot-ti.git master Mans Rullgard (3): ARMV7: OMAP3: Fix and clean up L2 cache enable/disable functions ARMV7: OMAP3: Convert setup_auxcr() to pure asm ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions Ricardo Salveti de Araujo (1): ARMV7: Fix pad mux for Panda LEDs Steve Sakoman (15): ARMV7: OMAP: Move syslib.c to omap-common since it can be shared by OMAP3 and OMAP4 ARMV7: OMAP: add convenience function to set TWL4030 regulator voltages ARMV7: OMAP: Enable input driver on Overo's MMC1_CLK and MMC3_CLK pinmux setup ARMV7: OMAP: Add mpurate boot arg for Overo and Beagle ARMV7: OMAP: Add board revision detection for Overo ARMV7: OMAP: Add detection and support for Beagle C4 revision ARMV7: OMAP: Configure Overo's second network chip ARMV7: OMAP3: Update CPU type detection for AM35XX/OMAP36XX/37XX ARMV7: OMAP3: Add clock setup for OMAP36XX/37XX ARMV7: OMAP3: Fix broken reset command on OMAP36XX/37XX and OMAP4 ARMV7: OMAP3: Remove erroneous hard coded sdram setup for 128MB/bank mtd: nand: supress 'unknown NAND' warning if no nand is found ARMV7: OMAP3: Add CONFIG_SYS_NAND_QUIET_TEST to Beagle and Overo configs ARMV7: OMAP3: Add support for Beagle xM ARMV7: OMAP: Overo: Autodetect presence/absence of transceiver on mmc2 arch/arm/cpu/armv7/omap-common/Makefile | 2 + arch/arm/cpu/armv7/omap-common/reset.S | 4 +- arch/arm/cpu/armv7/{omap3 => omap-common}/syslib.c | 2 - arch/arm/cpu/armv7/omap3/Makefile | 1 - arch/arm/cpu/armv7/omap3/board.c | 35 -- arch/arm/cpu/armv7/omap3/cache.S | 101 ++-- arch/arm/cpu/armv7/omap3/clock.c | 549 ++++++++++++++------ arch/arm/cpu/armv7/omap3/lowlevel_init.S | 69 +++ arch/arm/cpu/armv7/omap3/sdrc.c | 43 +- arch/arm/cpu/armv7/omap3/sys_info.c | 147 +++++- arch/arm/include/asm/arch-omap3/clocks.h | 17 + arch/arm/include/asm/arch-omap3/clocks_omap3.h | 27 + arch/arm/include/asm/arch-omap3/cpu.h | 15 +- arch/arm/include/asm/arch-omap3/omap3.h | 32 ++- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 + arch/arm/include/asm/arch-omap4/omap4.h | 1 + arch/arm/include/asm/arch-omap4/sys_proto.h | 3 + board/overo/overo.c | 105 ++++- board/overo/overo.h | 47 ++- board/ti/beagle/beagle.c | 102 +++-- board/ti/beagle/beagle.h | 40 ++- board/ti/panda/panda.h | 44 +- drivers/mtd/nand/nand_base.c | 9 +- drivers/power/twl4030.c | 69 ++-- include/configs/omap3_beagle.h | 4 + include/configs/omap3_overo.h | 4 + include/twl4030.h | 14 + 27 files changed, 1070 insertions(+), 418 deletions(-) rename arch/arm/cpu/armv7/{omap3 => omap-common}/syslib.c (97%)

2 1

[U-Boot] Your Email Id has won £1,000,000.00. in the British Tobacco Promo. send your
by sharon-sharp＠sbcglobal.net 09 Sep '10

09 Sep '10

Name.. Country..

1 0

[U-Boot] [PATCH v3 2/2] APM821xx: Add bluestone board support
by tmarri＠apm.com 09 Sep '10

09 Sep '10

From: Tirumala Marri <tmarri(a)apm.com> Add support code for bluestone board wth APM821XX processor based. This patch includes early board init, misc init, configure EBC, initializes UIC, MAKEALL, board.cfg and MAINTAINERS file. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com --- V2: * Missing space before "<". * SDR_AHB_CFG not used, remove. * boot device dfinitions are board specific ? removed. * APM82161_MASK not used, remove * set_mcsr() is already called in ddr init, no need to call here. * removed finding bootdevice function which is not used. * Add spaces in tlbentry() function. * Board early init function is empty remove. * Remove CONFIG_SYS_EXTSRAM_BASE. * Set CONFIG_SYS_FLASH_SIZE to 4MB * Remove CONFIG_SIZE_REDUCE & CONFIG_SECTOR_REDUCE. * Spaces around " >> " . * Correct the phy name CONFIG_M88E1111_PHY to CONFIG_RTL8211CL_PHY. V3: * Missing TLB entry for CONFIG_SYS_BOOT_BASE_ADDR. * Move CONFIG_SYS_EBC_PB0AP etc to EBC area in the config file. * remove unused CONFIG_RTL8211CL_PHY. * Replace hard coded valued for CONFIG_SYS_EBC_CFG with macro definitions. * Change APM82XXX to APM821XX * board.cfg add the entry in sorted. * use puts() if there is no formating needed. --- MAINTAINERS | 3 + MAKEALL | 1 + board/amcc/bluestone/Makefile | 52 +++++++++++ board/amcc/bluestone/bluestone.c | 111 ++++++++++++++++++++++++ board/amcc/bluestone/config.mk | 40 +++++++++ board/amcc/bluestone/init.S | 59 +++++++++++++ boards.cfg | 1 + include/configs/bluestone.h | 175 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 442 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..284d136 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -253,6 +253,9 @@ Feng Kan <fkan(a)amcc.com> redwood PPC4xx +Tirumala Marri <tmarri(a)apm.com> + bluestone APM821XX + Brad Kemp <Brad.Kemp(a)seranoa.com> ppmc8260 MPC8260 diff --git a/MAKEALL b/MAKEALL index b34ae33..02d5c17 100755 --- a/MAKEALL +++ b/MAKEALL @@ -191,6 +191,7 @@ LIST_4xx=" \ ASH405 \ bamboo \ bamboo_nand \ + bluestone \ bubinga \ CANBT \ canyonlands \ diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile new file mode 100644 index 0000000..41751c8 --- /dev/null +++ b/board/amcc/bluestone/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +SOBJS := init.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000..9bf5da2 --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,111 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <apm821xx.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/gpio.h> + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000..e2194e4 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri(a)apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM821XX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000..968f733 --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX | SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) + tlbtab_end diff --git a/boards.cfg b/boards.cfg index 69c6897..f436c66 100644 --- a/boards.cfg +++ b/boards.cfg @@ -186,6 +186,7 @@ t3corp powerpc ppc4xx zeus powerpc ppc4xx acadia powerpc ppc4xx - amcc bamboo powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc bubinga powerpc ppc4xx - amcc ebony powerpc ppc4xx - amcc katmai powerpc ppc4xx - amcc diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h new file mode 100644 index 0000000..40633b1 --- /dev/null +++ b/include/configs/bluestone.h @@ -0,0 +1,175 @@ +/* + * bluestone.h - configuration for Blouestone (APM821XX) + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri(a)apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_APM821XX 1 /* APM821XX series */ +#define CONFIG_HOSTNAME bluestone + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* EBC stuff */ +/* later mapped to this addr */ +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ + +/* EBC Boot Space: 0xFF000000 */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 80 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* SDRAM */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8 >> 1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII +#define CONFIG_HAS_ETH0 +/* PHY address, See schematics */ +#define CONFIG_PHY_ADDR 0x1f +/* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_R +/* Include GbE speed/duplex detection */ +#define CONFIG_PHY_GIGE 1 +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * External Bus Controller (EBC) Setup + **/ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_2048PERCLK | \ + EBC_CFG_ATC_HI | \ + EBC_CFG_DTC_HI | \ + EBC_CFG_CTC_HI | \ + EBC_CFG_OEO_PREVIOUS) +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + + +#endif /* __CONFIG_H */ -- 1.6.1.rc3

2 1

[U-Boot] [PATCH 2/4 v2] cfi_flash: Add weak default for cfi_flash_bank_addr()
by Stefan Roese 09 Sep '10

09 Sep '10

cfi_flash_bank_addr(int bank_nr) returns the base addresses of the requested bank. Introducing this weak default enables boards to override this functions with a board specific version when required. This feature will be used in the lwmon5 board update, supporting runtime detection of 2 board revisions with different flash layouts. Signed-off-by: Stefan Roese <sr(a)denx.de> --- v2: Coding-style update: Remove spaces before parantheses in function calls drivers/mtd/cfi_flash.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index b4a09dc..49a2b5e 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -85,6 +85,13 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif +static phys_addr_t __cfi_flash_bank_addr(int i) +{ + return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; +} +phys_addr_t cfi_flash_bank_addr(int i) + __attribute__((weak, alias("__cfi_flash_bank_addr"))); + static void __flash_write8(u8 value, void *addr) { __raw_writeb(value, addr); @@ -2021,14 +2028,12 @@ unsigned long flash_init (void) getenv_f("unlock", s, sizeof(s)); #endif -#define BANK_BASE(i) (((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i]) - /* Init: no FLASHes known */ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; - if (!flash_detect_legacy (BANK_BASE(i), i)) - flash_get_size (BANK_BASE(i), i); + if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) + flash_get_size(cfi_flash_bank_addr(i), i); size += flash_info[i].size; if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CONFIG_SYS_FLASH_QUIET_TEST -- 1.7.2.3

2 4

[U-Boot] [PATCH] fw_env_main: updated help for fw_printenv
by Frans Meulenbroeks 09 Sep '10

09 Sep '10

mention also that you can do fw_printenv name and fw_printenv -n name Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks(a)gmail.com> --- tools/env/fw_env_main.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 82116b4..ff2924d 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -60,6 +60,8 @@ void usage(void) fprintf(stderr, "fw_printenv/fw_setenv, " "a command line interface to U-Boot environment\n\n" "usage:\tfw_printenv\n" + "\tfw_printenv [variable name]\n" + "\tfw_printenv -n [variable name]\n" "\tfw_setenv [variable name] [variable value]\n" "\tfw_setenv -s [ file ]\n" "\tfw_setenv -s - < [ file ]\n\n" -- 1.7.0.4

1 0

[U-Boot] Winner
by Camelot Groups Lottery Board 09 Sep '10

09 Sep '10

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1 0

[U-Boot] [PATCH 01/13] PXA: pxa-regs.h cleanup
by Marek Vasut 09 Sep '10

09 Sep '10

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- Let's hope nothing got broken here. Please review thoroughly. pxa-regs.h was nearly replaced in order to make it a bit more readable. arch/arm/cpu/pxa/cpu.c | 28 +- arch/arm/cpu/pxa/i2c.c | 59 +- arch/arm/cpu/pxa/pxafb.c | 59 +- arch/arm/cpu/pxa/timer.c | 7 +- arch/arm/cpu/pxa/usb.c | 61 +- arch/arm/include/asm/arch-pxa/hardware.h | 61 +- arch/arm/include/asm/arch-pxa/pxa-regs.h | 2672 ++++++++++++++++-------------- board/colibri_pxa270/colibri_pxa270.c | 32 +- board/cradle/cradle.c | 5 +- board/cradle/lowlevel_init.S | 4 +- board/csb226/csb226.c | 13 +- board/delta/delta.c | 37 +- board/delta/nand.c | 110 +- board/innokom/innokom.c | 14 +- board/pxa255_idp/pxa_idp.c | 27 +- board/trizepsiv/conxs.c | 32 +- board/vpac270/vpac270.c | 35 +- board/wepep250/wepep250.c | 11 +- board/zipitz2/zipitz2.c | 33 +- board/zylonite/nand.c | 110 +- drivers/mmc/pxa_mmc.c | 83 +- drivers/serial/serial_pxa.c | 61 +- include/configs/cradle.h | 2 - include/configs/delta.h | 1 + include/configs/zylonite.h | 1 + 25 files changed, 1861 insertions(+), 1697 deletions(-) diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index 800d120..330d013 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -30,10 +30,11 @@ * CPU specific code */ -#include <common.h> -#include <command.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> #include <asm/system.h> +#include <command.h> +#include <common.h> static void cache_flush(void); @@ -71,17 +72,22 @@ void set_GPIO_mode(int gpio_mode) { int gpio = gpio_mode & GPIO_MD_MASK_NR; int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int gafr; + int val; + + /* This below changes direction setting of GPIO "gpio" */ + val = readl(GPDR(gpio)); if (gpio_mode & GPIO_MD_MASK_DIR) - { - GPDR(gpio) |= GPIO_bit(gpio); - } + val |= GPIO_bit(gpio); else - { - GPDR(gpio) &= ~GPIO_bit(gpio); - } - gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); - GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); + val &= ~GPIO_bit(gpio); + + writel(val, GPDR(gpio)); + + /* This below updates only AF of GPIO "gpio" */ + val = readl(GAFR(gpio)); + val &= ~(0x3 << (((gpio) & 0xf) * 2)); + val |= fn << (((gpio) & 0xf) * 2); + writel(val, GAFR(gpio)); } #endif /* CONFIG_CPU_MONAHANS */ diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c index 6b72ba1..0f9abf0 100644 --- a/arch/arm/cpu/pxa/i2c.c +++ b/arch/arm/cpu/pxa/i2c.c @@ -33,6 +33,7 @@ /* FIXME: this file is PXA255 specific! What about other XScales? */ #include <common.h> +#include <asm/io.h> #ifdef CONFIG_HARD_I2C @@ -93,19 +94,19 @@ struct i2c_msg { static void i2c_reset( void ) { - ICR &= ~ICR_IUE; /* disable unit */ - ICR |= ICR_UR; /* reset the unit */ + writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ + writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */ udelay(100); - ICR &= ~ICR_IUE; /* disable unit */ + writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ #ifdef CONFIG_CPU_MONAHANS - CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ + writel(readl(CKENB) | (CKENB_4_I2C), CKENB); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ #else /* CONFIG_CPU_MONAHANS */ - CKEN |= CKEN14_I2C; /* set the global I2C clock on */ + writel(readl(CKEN) | CKEN14_I2C, CKEN); /* set the global I2C clock on */ #endif - ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ - ICR = I2C_ICR_INIT; /* set control register values */ - ISR = I2C_ISR_INIT; /* set clear interrupt bits */ - ICR |= ICR_IUE; /* enable unit */ + writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */ + writel(I2C_ICR_INIT, ICR); /* set control register values */ + writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */ + writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */ udelay(100); } @@ -159,22 +160,22 @@ int i2c_transfer(struct i2c_msg *msg) goto transfer_error_bus_busy; /* start transmission */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - IDBR = msg->data; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; + writel(readl(ICR) & ~ICR_START, ICR); + writel(readl(ICR) & ~ICR_STOP, ICR); + writel(msg->data, IDBR); + if (msg->condition == I2C_COND_START) writel(readl(ICR) | ICR_START, ICR); + if (msg->condition == I2C_COND_STOP) writel(readl(ICR) | ICR_STOP, ICR); + if (msg->acknack == I2C_ACKNAK_SENDNAK) writel(readl(ICR) | ICR_ACKNAK, ICR); + if (msg->acknack == I2C_ACKNAK_SENDACK) writel(readl(ICR) & ~ICR_ACKNAK, ICR); + writel(readl(ICR) & ~ICR_ALDIE, ICR); + writel(readl(ICR) | ICR_TB, ICR); /* transmit register empty? */ if (!i2c_isr_set_cleared(ISR_ITE,0)) goto transfer_error_transmit_timeout; /* clear 'transmit empty' state */ - ISR |= ISR_ITE; + writel(readl(ISR) | ISR_ITE, ISR); /* wait for ACK from slave */ if (msg->acknack == I2C_ACKNAK_WAITACK) @@ -189,23 +190,23 @@ int i2c_transfer(struct i2c_msg *msg) goto transfer_error_bus_busy; /* start receive */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; + writel(readl(ICR) & ~ICR_START, ICR); + writel(readl(ICR) & ~ICR_STOP, ICR); + if (msg->condition == I2C_COND_START) writel(readl(ICR) | ICR_START, ICR); + if (msg->condition == I2C_COND_STOP) writel(readl(ICR) | ICR_STOP, ICR); + if (msg->acknack == I2C_ACKNAK_SENDNAK) writel(readl(ICR) | ICR_ACKNAK, ICR); + if (msg->acknack == I2C_ACKNAK_SENDACK) writel(readl(ICR) & ~ICR_ACKNAK, ICR); + writel(readl(ICR) & ~ICR_ALDIE, ICR); + writel(readl(ICR) | ICR_TB, ICR); /* receive register full? */ if (!i2c_isr_set_cleared(ISR_IRF,0)) goto transfer_error_receive_timeout; - msg->data = IDBR; + msg->data = readl(IDBR); /* clear 'receive empty' state */ - ISR |= ISR_IRF; + writel(readl(ISR) | ISR_IRF, ISR); break; diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c index 524a03b..e03e724 100644 --- a/arch/arm/cpu/pxa/pxafb.c +++ b/arch/arm/cpu/pxa/pxafb.c @@ -35,6 +35,7 @@ #include <stdio_dev.h> #include <lcd.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> /* #define DEBUG */ @@ -377,12 +378,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 4 bit data\n"); /* bits 58-61 */ - GPDR1 |= (0xf << 26); - GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR1) | (0xf << 26), GPDR1); + writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), GAFR1_U); /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), GAFR2_L); } /* 8 bit interface */ @@ -391,15 +392,15 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 8 bit data\n"); /* bits 58-65 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= (0x3); + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | (0x3), GPDR2); - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & ~0xf) | (0xa); + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), GAFR1_U); + writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), GAFR2_L); } /* 16 bit interface */ @@ -407,11 +408,11 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 16 bit data\n"); /* bits 58-77 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= 0x00003fff; + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | 0x00003fff, GPDR2); - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa; + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), GAFR1_U); + writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); } else { @@ -425,26 +426,26 @@ static void pxafb_enable_controller (vidinfo_t *vid) debug("Enabling LCD controller\n"); /* Sequence from 11.7.10 */ - LCCR3 = vid->pxa.reg_lccr3; - LCCR2 = vid->pxa.reg_lccr2; - LCCR1 = vid->pxa.reg_lccr1; - LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB; - FDADR0 = vid->pxa.fdadr0; - FDADR1 = vid->pxa.fdadr1; - LCCR0 |= LCCR0_ENB; + writel(vid->pxa.reg_lccr3, LCCR3); + writel(vid->pxa.reg_lccr2, LCCR2); + writel(vid->pxa.reg_lccr1, LCCR1); + writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); + writel(vid->pxa.fdadr0, FDADR0); + writel(vid->pxa.fdadr1, FDADR1); + writel(readl(LCCR0) | LCCR0_ENB, LCCR0); #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_1_LCD; + writel(readl(CKENA) | CKENA_1_LCD, CKENA); #else - CKEN |= CKEN16_LCD; + writel(readl(CKEN) | CKEN16_LCD, CKEN); #endif - debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0); - debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1); - debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0); - debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1); - debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2); - debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3); + debug("FDADR0 = 0x%08x\n", (unsigned int)readl(FDADR0)); + debug("FDADR1 = 0x%08x\n", (unsigned int)readl(FDADR1)); + debug("LCCR0 = 0x%08x\n", (unsigned int)readl(LCCR0)); + debug("LCCR1 = 0x%08x\n", (unsigned int)readl(LCCR1)); + debug("LCCR2 = 0x%08x\n", (unsigned int)readl(LCCR2)); + debug("LCCR3 = 0x%08x\n", (unsigned int)readl(LCCR3)); } static int pxafb_init (vidinfo_t *vid) diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 8d0f826..ec950c7 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -26,8 +26,9 @@ * MA 02111-1307 USA */ -#include <common.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> +#include <common.h> #include <div64.h> #ifdef CONFIG_USE_IRQ @@ -86,7 +87,7 @@ void __udelay (unsigned long usec) void reset_timer_masked (void) { - OSCR = 0; + writel(0, OSCR); } ulong get_timer_masked (void) @@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec) */ unsigned long long get_ticks(void) { - return OSCR; + return readl(OSCR); } /* diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index bd718a6..0311d5e 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -27,86 +27,79 @@ # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include <asm/arch/pxa-regs.h> +#include <asm/io.h> #include <usb.h> int usb_cpu_init(void) { #if defined(CONFIG_CPU_MONAHANS) /* Enable USB host clock. */ - CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC); + writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); udelay(100); #endif #if defined(CONFIG_PXA27X) /* Enable USB host clock. */ - CKEN |= CKEN10_USBHOST; + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); #endif #if defined(CONFIG_CPU_MONAHANS) /* Configure Port 2 for Host (USB Client Registers) */ - UP2OCR = 0x3000c; + writel(0x3000c, UP2OCR); #endif - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); wait_ms(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCHR |= UHCHR_FSBIR; - while (UHCHR & UHCHR_FSBIR) + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + while (readl(UHCHR) & UHCHR_FSBIR) udelay(1); #if defined(CONFIG_CPU_MONAHANS) - UHCHR &= ~UHCHR_SSEP0; + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR &= ~UHCHR_SSEP2; + writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); #endif - UHCHR &= ~UHCHR_SSEP1; - UHCHR &= ~UHCHR_SSE; + writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); return 0; } int usb_cpu_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS); udelay(10); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; - - return 0; -} - -int usb_cpu_init_fail(void) -{ - UHCHR |= UHCHR_FHR; - udelay(11); - UHCHR &= ~UHCHR_FHR; - - UHCCOMS |= 1; - udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + /* Disable USB host clock. */ + writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); + udelay(100); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + /* Disable USB host clock. */ + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; return 0; } +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h index c8c479a..44b800f 100644 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ b/arch/arm/include/asm/arch-pxa/hardware.h @@ -21,6 +21,19 @@ #include <linux/config.h> #include <asm/mach-types.h> +/* + * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. + * PXA300/310/320 all have distinct register mappings in some cases, that's why + * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common + * drivers and compatibility glue with old source then. + */ +#ifndef CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA300) || \ + defined(CONFIG_CPU_PXA310) || \ + defined(CONFIG_CPU_PXA320) +#define CONFIG_CPU_MONAHANS +#endif +#endif /* * These are statically mapped PCMCIA IO space for designs using it as a @@ -51,54 +64,6 @@ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff */ -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 - -#ifndef UBOOT_REG_FIX -#ifndef __ASSEMBLY__ - -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) - -/* - * This __REG() version gives the same results as the one above, except - * that we are fooling gcc somehow so it generates far better and smaller - * assembly code for access to contigous registers. It's a shame that gcc - * doesn't guess this by itself. - */ -#include <asm/types.h> -typedef struct { volatile u32 offset[4096]; } __regbase; -# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] -# define __REG(x) __REGP(io_p2v(x)) -#endif - -/* Let's kick gcc's ass again... */ -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */ -# define __REG_2(x) (x) -# define __REG_3(x) (x) -# endif -# endif -#endif /* UBOOT_REG_FIX */ - #include "pxa-regs.h" #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index d442fb0..a02963d 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -93,42 +93,42 @@ typedef void (*ExcpHndlr) (void) ; /* * DMA Controller */ -#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ -#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ -#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ -#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ -#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ -#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ -#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ -#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ -#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ -#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ -#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ -#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ -#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ -#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ -#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ -#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ -#ifdef CONFIG_CPU_MONAHANS -#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */ -#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */ -#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */ -#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */ -#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */ -#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */ -#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */ -#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */ -#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */ -#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */ -#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */ -#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */ -#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */ -#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */ -#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */ -#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_CPU_MONAHANS */ - -#define DCSR(x) __REG2(0x40000000, (x) << 2) +#define DCSR0 (0x40000000) /* DMA Control / Status Register for Channel 0 */ +#define DCSR1 (0x40000004) /* DMA Control / Status Register for Channel 1 */ +#define DCSR2 (0x40000008) /* DMA Control / Status Register for Channel 2 */ +#define DCSR3 (0x4000000c) /* DMA Control / Status Register for Channel 3 */ +#define DCSR4 (0x40000010) /* DMA Control / Status Register for Channel 4 */ +#define DCSR5 (0x40000014) /* DMA Control / Status Register for Channel 5 */ +#define DCSR6 (0x40000018) /* DMA Control / Status Register for Channel 6 */ +#define DCSR7 (0x4000001c) /* DMA Control / Status Register for Channel 7 */ +#define DCSR8 (0x40000020) /* DMA Control / Status Register for Channel 8 */ +#define DCSR9 (0x40000024) /* DMA Control / Status Register for Channel 9 */ +#define DCSR10 (0x40000028) /* DMA Control / Status Register for Channel 10 */ +#define DCSR11 (0x4000002c) /* DMA Control / Status Register for Channel 11 */ +#define DCSR12 (0x40000030) /* DMA Control / Status Register for Channel 12 */ +#define DCSR13 (0x40000034) /* DMA Control / Status Register for Channel 13 */ +#define DCSR14 (0x40000038) /* DMA Control / Status Register for Channel 14 */ +#define DCSR15 (0x4000003c) /* DMA Control / Status Register for Channel 15 */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define DCSR16 (0x40000040) /* DMA Control / Status Register for Channel 16 */ +#define DCSR17 (0x40000044) /* DMA Control / Status Register for Channel 17 */ +#define DCSR18 (0x40000048) /* DMA Control / Status Register for Channel 18 */ +#define DCSR19 (0x4000004c) /* DMA Control / Status Register for Channel 19 */ +#define DCSR20 (0x40000050) /* DMA Control / Status Register for Channel 20 */ +#define DCSR21 (0x40000054) /* DMA Control / Status Register for Channel 21 */ +#define DCSR22 (0x40000058) /* DMA Control / Status Register for Channel 22 */ +#define DCSR23 (0x4000005c) /* DMA Control / Status Register for Channel 23 */ +#define DCSR24 (0x40000060) /* DMA Control / Status Register for Channel 24 */ +#define DCSR25 (0x40000064) /* DMA Control / Status Register for Channel 25 */ +#define DCSR26 (0x40000068) /* DMA Control / Status Register for Channel 26 */ +#define DCSR27 (0x4000006c) /* DMA Control / Status Register for Channel 27 */ +#define DCSR28 (0x40000070) /* DMA Control / Status Register for Channel 28 */ +#define DCSR29 (0x40000074) /* DMA Control / Status Register for Channel 29 */ +#define DCSR30 (0x40000078) /* DMA Control / Status Register for Channel 30 */ +#define DCSR31 (0x4000007c) /* DMA Control / Status Register for Channel 31 */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +#define DCSR(x) (0x40000000 | ((x) << 2)) #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ @@ -150,52 +150,52 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ -#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ - -#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ -#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ -#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ -#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ -#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ -#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ -#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ -#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ -#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ -#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ -#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ -#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ -#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ -#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ -#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ -#define DRCMR15 __REG(0x4000013c) /* Reserved */ -#define DRCMR16 __REG(0x40000140) /* Reserved */ -#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ -#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ -#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ -#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ -#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ -#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ -#define DRCMR23 __REG(0x4000015c) /* Reserved */ -#define DRCMR24 __REG(0x40000160) /* Reserved */ -#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ -#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ -#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ -#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ -#define DRCMR29 __REG(0x40000174) /* Reserved */ -#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ -#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ -#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ -#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ -#define DRCMR34 __REG(0x40000188) /* Reserved */ -#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ -#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ -#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ -#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ -#define DRCMR39 __REG(0x4000019C) /* Reserved */ - -#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ -#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ -#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ +#define DINT (0x400000f0) /* DMA Interrupt Register */ + +#define DRCMR0 (0x40000100) /* Request to Channel Map Register for DREQ 0 */ +#define DRCMR1 (0x40000104) /* Request to Channel Map Register for DREQ 1 */ +#define DRCMR2 (0x40000108) /* Request to Channel Map Register for I2S receive Request */ +#define DRCMR3 (0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ +#define DRCMR4 (0x40000110) /* Request to Channel Map Register for BTUART receive Request */ +#define DRCMR5 (0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ +#define DRCMR6 (0x40000118) /* Request to Channel Map Register for FFUART receive Request */ +#define DRCMR7 (0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ +#define DRCMR8 (0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ +#define DRCMR9 (0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ +#define DRCMR10 (0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ +#define DRCMR11 (0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ +#define DRCMR12 (0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ +#define DRCMR13 (0x40000134) /* Request to Channel Map Register for SSP receive Request */ +#define DRCMR14 (0x40000138) /* Request to Channel Map Register for SSP transmit Request */ +#define DRCMR15 (0x4000013c) /* Reserved */ +#define DRCMR16 (0x40000140) /* Reserved */ +#define DRCMR17 (0x40000144) /* Request to Channel Map Register for ICP receive Request */ +#define DRCMR18 (0x40000148) /* Request to Channel Map Register for ICP transmit Request */ +#define DRCMR19 (0x4000014c) /* Request to Channel Map Register for STUART receive Request */ +#define DRCMR20 (0x40000150) /* Request to Channel Map Register for STUART transmit Request */ +#define DRCMR21 (0x40000154) /* Request to Channel Map Register for MMC receive Request */ +#define DRCMR22 (0x40000158) /* Request to Channel Map Register for MMC transmit Request */ +#define DRCMR23 (0x4000015c) /* Reserved */ +#define DRCMR24 (0x40000160) /* Reserved */ +#define DRCMR25 (0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ +#define DRCMR26 (0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ +#define DRCMR27 (0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ +#define DRCMR28 (0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ +#define DRCMR29 (0x40000174) /* Reserved */ +#define DRCMR30 (0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ +#define DRCMR31 (0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ +#define DRCMR32 (0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ +#define DRCMR33 (0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ +#define DRCMR34 (0x40000188) /* Reserved */ +#define DRCMR35 (0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ +#define DRCMR36 (0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ +#define DRCMR37 (0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ +#define DRCMR38 (0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ +#define DRCMR39 (0x4000019C) /* Reserved */ + +#define DRCMR68 (0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ +#define DRCMR69 (0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ +#define DRCMR70 (0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ #define DRCMRRXSADR DRCMR2 #define DRCMRTXSADR DRCMR3 @@ -220,75 +220,75 @@ typedef void (*ExcpHndlr) (void) ; #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ -#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ -#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ -#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ -#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ -#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ -#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ -#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ -#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ -#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ -#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ -#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ -#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ -#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ -#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ -#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ -#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ -#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ -#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ -#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ -#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ -#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ -#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ -#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ -#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ -#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ -#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ -#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ -#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ -#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ -#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ -#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ -#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ -#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ -#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ -#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ -#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ -#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ -#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ -#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ -#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ -#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ -#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ -#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ -#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ -#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ -#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ -#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ -#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ -#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ -#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ -#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ -#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ -#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ -#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ -#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ -#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ -#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ -#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ -#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ -#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ -#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ -#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ -#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ -#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ - -#define DDADR(x) __REG2(0x40000200, (x) << 4) -#define DSADR(x) __REG2(0x40000204, (x) << 4) -#define DTADR(x) __REG2(0x40000208, (x) << 4) -#define DCMD(x) __REG2(0x4000020c, (x) << 4) +#define DDADR0 (0x40000200) /* DMA Descriptor Address Register Channel 0 */ +#define DSADR0 (0x40000204) /* DMA Source Address Register Channel 0 */ +#define DTADR0 (0x40000208) /* DMA Target Address Register Channel 0 */ +#define DCMD0 (0x4000020c) /* DMA Command Address Register Channel 0 */ +#define DDADR1 (0x40000210) /* DMA Descriptor Address Register Channel 1 */ +#define DSADR1 (0x40000214) /* DMA Source Address Register Channel 1 */ +#define DTADR1 (0x40000218) /* DMA Target Address Register Channel 1 */ +#define DCMD1 (0x4000021c) /* DMA Command Address Register Channel 1 */ +#define DDADR2 (0x40000220) /* DMA Descriptor Address Register Channel 2 */ +#define DSADR2 (0x40000224) /* DMA Source Address Register Channel 2 */ +#define DTADR2 (0x40000228) /* DMA Target Address Register Channel 2 */ +#define DCMD2 (0x4000022c) /* DMA Command Address Register Channel 2 */ +#define DDADR3 (0x40000230) /* DMA Descriptor Address Register Channel 3 */ +#define DSADR3 (0x40000234) /* DMA Source Address Register Channel 3 */ +#define DTADR3 (0x40000238) /* DMA Target Address Register Channel 3 */ +#define DCMD3 (0x4000023c) /* DMA Command Address Register Channel 3 */ +#define DDADR4 (0x40000240) /* DMA Descriptor Address Register Channel 4 */ +#define DSADR4 (0x40000244) /* DMA Source Address Register Channel 4 */ +#define DTADR4 (0x40000248) /* DMA Target Address Register Channel 4 */ +#define DCMD4 (0x4000024c) /* DMA Command Address Register Channel 4 */ +#define DDADR5 (0x40000250) /* DMA Descriptor Address Register Channel 5 */ +#define DSADR5 (0x40000254) /* DMA Source Address Register Channel 5 */ +#define DTADR5 (0x40000258) /* DMA Target Address Register Channel 5 */ +#define DCMD5 (0x4000025c) /* DMA Command Address Register Channel 5 */ +#define DDADR6 (0x40000260) /* DMA Descriptor Address Register Channel 6 */ +#define DSADR6 (0x40000264) /* DMA Source Address Register Channel 6 */ +#define DTADR6 (0x40000268) /* DMA Target Address Register Channel 6 */ +#define DCMD6 (0x4000026c) /* DMA Command Address Register Channel 6 */ +#define DDADR7 (0x40000270) /* DMA Descriptor Address Register Channel 7 */ +#define DSADR7 (0x40000274) /* DMA Source Address Register Channel 7 */ +#define DTADR7 (0x40000278) /* DMA Target Address Register Channel 7 */ +#define DCMD7 (0x4000027c) /* DMA Command Address Register Channel 7 */ +#define DDADR8 (0x40000280) /* DMA Descriptor Address Register Channel 8 */ +#define DSADR8 (0x40000284) /* DMA Source Address Register Channel 8 */ +#define DTADR8 (0x40000288) /* DMA Target Address Register Channel 8 */ +#define DCMD8 (0x4000028c) /* DMA Command Address Register Channel 8 */ +#define DDADR9 (0x40000290) /* DMA Descriptor Address Register Channel 9 */ +#define DSADR9 (0x40000294) /* DMA Source Address Register Channel 9 */ +#define DTADR9 (0x40000298) /* DMA Target Address Register Channel 9 */ +#define DCMD9 (0x4000029c) /* DMA Command Address Register Channel 9 */ +#define DDADR10 (0x400002a0) /* DMA Descriptor Address Register Channel 10 */ +#define DSADR10 (0x400002a4) /* DMA Source Address Register Channel 10 */ +#define DTADR10 (0x400002a8) /* DMA Target Address Register Channel 10 */ +#define DCMD10 (0x400002ac) /* DMA Command Address Register Channel 10 */ +#define DDADR11 (0x400002b0) /* DMA Descriptor Address Register Channel 11 */ +#define DSADR11 (0x400002b4) /* DMA Source Address Register Channel 11 */ +#define DTADR11 (0x400002b8) /* DMA Target Address Register Channel 11 */ +#define DCMD11 (0x400002bc) /* DMA Command Address Register Channel 11 */ +#define DDADR12 (0x400002c0) /* DMA Descriptor Address Register Channel 12 */ +#define DSADR12 (0x400002c4) /* DMA Source Address Register Channel 12 */ +#define DTADR12 (0x400002c8) /* DMA Target Address Register Channel 12 */ +#define DCMD12 (0x400002cc) /* DMA Command Address Register Channel 12 */ +#define DDADR13 (0x400002d0) /* DMA Descriptor Address Register Channel 13 */ +#define DSADR13 (0x400002d4) /* DMA Source Address Register Channel 13 */ +#define DTADR13 (0x400002d8) /* DMA Target Address Register Channel 13 */ +#define DCMD13 (0x400002dc) /* DMA Command Address Register Channel 13 */ +#define DDADR14 (0x400002e0) /* DMA Descriptor Address Register Channel 14 */ +#define DSADR14 (0x400002e4) /* DMA Source Address Register Channel 14 */ +#define DTADR14 (0x400002e8) /* DMA Target Address Register Channel 14 */ +#define DCMD14 (0x400002ec) /* DMA Command Address Register Channel 14 */ +#define DDADR15 (0x400002f0) /* DMA Descriptor Address Register Channel 15 */ +#define DSADR15 (0x400002f4) /* DMA Source Address Register Channel 15 */ +#define DTADR15 (0x400002f8) /* DMA Target Address Register Channel 15 */ +#define DCMD15 (0x400002fc) /* DMA Command Address Register Channel 15 */ + +#define DDADR(x) (0x40000200 | ((x) << 4)) +#define DSADR(x) (0x40000204 | ((x) << 4)) +#define DTADR(x) (0x40000208 | ((x) << 4)) +#define DCMD(x) (0x4000020c | ((x) << 4)) #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ #define DDADR_STOP (1 << 0) /* Stop (read / write) */ @@ -313,56 +313,57 @@ typedef void (*ExcpHndlr) (void) ; #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) +/******************************************************************************/ /* * UARTs */ /* Full Function UART (FFUART) */ #define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define FFRBR (0x40100000) /* Receive Buffer Register (read only) */ +#define FFTHR (0x40100000) /* Transmit Holding Register (write only) */ +#define FFIER (0x40100004) /* Interrupt Enable Register (read/write) */ +#define FFIIR (0x40100008) /* Interrupt ID Register (read only) */ +#define FFFCR (0x40100008) /* FIFO Control Register (write only) */ +#define FFLCR (0x4010000C) /* Line Control Register (read/write) */ +#define FFMCR (0x40100010) /* Modem Control Register (read/write) */ +#define FFLSR (0x40100014) /* Line Status Register (read only) */ +#define FFMSR (0x40100018) /* Modem Status Register (read only) */ +#define FFSPR (0x4010001C) /* Scratch Pad Register (read/write) */ +#define FFISR (0x40100020) /* Infrared Selection Register (read/write) */ +#define FFDLL (0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH (0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Bluetooth UART (BTUART) */ #define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define BTRBR (0x40200000) /* Receive Buffer Register (read only) */ +#define BTTHR (0x40200000) /* Transmit Holding Register (write only) */ +#define BTIER (0x40200004) /* Interrupt Enable Register (read/write) */ +#define BTIIR (0x40200008) /* Interrupt ID Register (read only) */ +#define BTFCR (0x40200008) /* FIFO Control Register (write only) */ +#define BTLCR (0x4020000C) /* Line Control Register (read/write) */ +#define BTMCR (0x40200010) /* Modem Control Register (read/write) */ +#define BTLSR (0x40200014) /* Line Status Register (read only) */ +#define BTMSR (0x40200018) /* Modem Status Register (read only) */ +#define BTSPR (0x4020001C) /* Scratch Pad Register (read/write) */ +#define BTISR (0x40200020) /* Infrared Selection Register (read/write) */ +#define BTDLL (0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH (0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Standard UART (STUART) */ #define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define STRBR (0x40700000) /* Receive Buffer Register (read only) */ +#define STTHR (0x40700000) /* Transmit Holding Register (write only) */ +#define STIER (0x40700004) /* Interrupt Enable Register (read/write) */ +#define STIIR (0x40700008) /* Interrupt ID Register (read only) */ +#define STFCR (0x40700008) /* FIFO Control Register (write only) */ +#define STLCR (0x4070000C) /* Line Control Register (read/write) */ +#define STMCR (0x40700010) /* Modem Control Register (read/write) */ +#define STLSR (0x40700014) /* Line Status Register (read only) */ +#define STMSR (0x40700018) /* Reserved */ +#define STSPR (0x4070001C) /* Scratch Pad Register (read/write) */ +#define STISR (0x40700020) /* Infrared Selection Register (read/write) */ +#define STDLL (0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH (0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ #define IER_DMAE (1 << 7) /* DMA Requests Enable */ #define IER_UUE (1 << 6) /* UART Unit Enable */ @@ -423,6 +424,7 @@ typedef void (*ExcpHndlr) (void) ; #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ +/******************************************************************************/ /* * IrSR (Infrared Selection Register) */ @@ -456,17 +458,25 @@ typedef void (*ExcpHndlr) (void) ; /* * I2C registers */ -#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ -#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ -#define ICR __REG(0x40301690) /* I2C Control Register - ICR */ -#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ -#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ - -#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ -#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ -#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ -#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ -#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */ +#define IBMR (0x40301680) /* I2C Bus Monitor Register - IBMR */ +#define IDBR (0x40301688) /* I2C Data Buffer Register - IDBR */ +#define ICR (0x40301690) /* I2C Control Register - ICR */ +#define ISR (0x40301698) /* I2C Status Register - ISR */ +#define ISAR (0x403016A0) /* I2C Slave Address Register - ISAR */ + +#ifdef CONFIG_CPU_MONAHANS +#define PWRIBMR (0x40f500C0) /* Power I2C Bus Monitor Register-IBMR */ +#define PWRIDBR (0x40f500C4) /* Power I2C Data Buffer Register-IDBR */ +#define PWRICR (0x40f500C8) /* Power I2C Control Register - ICR */ +#define PWRISR (0x40f500CC) /* Power I2C Status Register - ISR */ +#define PWRISAR (0x40f500D0) /* Power I2C Slave Address Register-ISAR */ +#else +#define PWRIBMR (0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ +#define PWRIDBR (0x40f00188) /* Power I2C Data Buffer Register-IDBR */ +#define PWRICR (0x40f00190) /* Power I2C Control Register - ICR */ +#define PWRISR (0x40f00198) /* Power I2C Status Register - ISR */ +#define PWRISAR (0x40f001A0) /* Power I2C Slave Address Register-ISAR */ +#endif /* ----- Control register bits ---------------------------------------- */ @@ -507,28 +517,28 @@ typedef void (*ExcpHndlr) (void) ; /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these * short defines because there is too much chance of namespace collision */ -/*#define SACR0 __REG(0x40400000) / Global Control Register */ -/*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */ -/*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -/*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */ -/*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */ -/*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */ -/*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */ +///*#define SACR0 (0x40400000) / Global Control Register */ +///*#define SACR1 (0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */ +///*#define SASR0 (0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ +///*#define SAIMR (0x40400014) / Serial Audio Interrupt Mask Register */ +///*#define SAICR (0x40400018) / Serial Audio Interrupt Clear Register */ +///*#define SADIV (0x40400060) / Audio Clock Divider Register. */ +///*#define SADR (0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */ /* * AC97 Controller registers */ -#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR (0x40500000) /* PCM Out Control Register */ #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR (0x40500004) /* PCM In Control Register */ #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR (0x40500008) /* Mic In Control Register */ #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define GCR __REG(0x4050000C) /* Global Control Register */ +#define GCR (0x4050000C) /* Global Control Register */ #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ @@ -540,16 +550,16 @@ typedef void (*ExcpHndlr) (void) ; #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ -#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR (0x40500010) /* PCM Out Status Register */ #define POSR_FIFOE (1 << 4) /* FIFO error */ -#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR (0x40500014) /* PCM In Status Register */ #define PISR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR (0x40500018) /* Mic In Status Register */ #define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR (0x4050001C) /* Global Status Register */ #define GSR_CDONE (1 << 19) /* Command Done */ #define GSR_SDONE (1 << 18) /* Status Done */ #define GSR_RDCS (1 << 15) /* Read Completion Status */ @@ -567,38 +577,38 @@ typedef void (*ExcpHndlr) (void) ; #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ -#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR (0x40500020) /* CODEC Access Register */ #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ +#define PCDR (0x40500040) /* PCM FIFO Data Register */ +#define MCDR (0x40500060) /* Mic-in FIFO Data Register */ -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR (0x40500100) /* Modem Out Control Register */ #define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR (0x40500108) /* Modem In Control Register */ #define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR (0x40500110) /* Modem Out Status Register */ #define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR (0x40500118) /* Modem In Status Register */ #define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ +#define MODR (0x40500140) /* Modem FIFO Data Register */ -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ +#define PAC_REG_BASE (0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE (0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE (0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE (0x40500500) /* Secondary Modem Codec */ /* * USB Device Controller */ -#ifdef CONFIG_PXA27X +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR (0x40600000) /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ #define UDCCR_UDA (1 << 1) /* UDC active */ #define UDCCR_RSM (1 << 2) /* Device resume */ @@ -623,7 +633,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */ #define UDCCR_AAISN_S 5 -#define UDCCS0 __REG(0x40600100) /* UDC Endpoint 0 Control/Status Register */ +#define UDCCS0 (0x40600100) /* UDC Endpoint 0 Control/Status Register */ #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ #define UDCCS0_IPR (1 << 1) /* IN packet ready */ #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ @@ -634,9 +644,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS0_SA (1 << 7) /* Setup active */ /* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 __REG(0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ +#define UDCCS1 (0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */ +#define UDCCS6 (0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ +#define UDCCS11 (0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ @@ -647,9 +657,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ /* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 __REG(0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ +#define UDCCS2 (0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */ +#define UDCCS7 (0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ +#define UDCCS12 (0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ @@ -660,9 +670,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ /* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ +#define UDCCS3 (0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ +#define UDCCS8 (0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ +#define UDCCS13 (0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ @@ -671,9 +681,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ /* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ +#define UDCCS4 (0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ +#define UDCCS9 (0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ +#define UDCCS14 (0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ @@ -683,9 +693,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ /* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ +#define UDCCS5 (0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ +#define UDCCS10 (0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ +#define UDCCS15 (0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ @@ -695,32 +705,32 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_INT_FST (1 << 5) /* Force stall */ #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ -#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ -#define UFNRL __REG(0x40600014) /* UDC Frame Number Register Low */ -#define UBCR2 __REG(0x40600208) /* UDC Byte Count Reg 2 */ -#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ -#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ -#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ -#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ -#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ -#define UDDR0 __REG(0x40600300) /* UDC Endpoint 0 Data Register */ -#define UDDR1 __REG(0x40600304) /* UDC Endpoint 1 Data Register */ -#define UDDR2 __REG(0x40600308) /* UDC Endpoint 2 Data Register */ -#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ -#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ -#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ -#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ -#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ -#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ -#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ -#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ -#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ -#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ -#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ -#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ -#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ - -#define UICR0 __REG(0x40600004) /* UDC Interrupt Control Register 0 */ +#define UFNRH (0x40600060) /* UDC Frame Number Register High */ +#define UFNRL (0x40600014) /* UDC Frame Number Register Low */ +#define UBCR2 (0x40600208) /* UDC Byte Count Reg 2 */ +#define UBCR4 (0x4060006c) /* UDC Byte Count Reg 4 */ +#define UBCR7 (0x40600070) /* UDC Byte Count Reg 7 */ +#define UBCR9 (0x40600074) /* UDC Byte Count Reg 9 */ +#define UBCR12 (0x40600078) /* UDC Byte Count Reg 12 */ +#define UBCR14 (0x4060007c) /* UDC Byte Count Reg 14 */ +#define UDDR0 (0x40600300) /* UDC Endpoint 0 Data Register */ +#define UDDR1 (0x40600304) /* UDC Endpoint 1 Data Register */ +#define UDDR2 (0x40600308) /* UDC Endpoint 2 Data Register */ +#define UDDR3 (0x40600200) /* UDC Endpoint 3 Data Register */ +#define UDDR4 (0x40600400) /* UDC Endpoint 4 Data Register */ +#define UDDR5 (0x406000A0) /* UDC Endpoint 5 Data Register */ +#define UDDR6 (0x40600600) /* UDC Endpoint 6 Data Register */ +#define UDDR7 (0x40600680) /* UDC Endpoint 7 Data Register */ +#define UDDR8 (0x40600700) /* UDC Endpoint 8 Data Register */ +#define UDDR9 (0x40600900) /* UDC Endpoint 9 Data Register */ +#define UDDR10 (0x406000C0) /* UDC Endpoint 10 Data Register */ +#define UDDR11 (0x40600B00) /* UDC Endpoint 11 Data Register */ +#define UDDR12 (0x40600B80) /* UDC Endpoint 12 Data Register */ +#define UDDR13 (0x40600C00) /* UDC Endpoint 13 Data Register */ +#define UDDR14 (0x40600E00) /* UDC Endpoint 14 Data Register */ +#define UDDR15 (0x406000E0) /* UDC Endpoint 15 Data Register */ + +#define UICR0 (0x40600004) /* UDC Interrupt Control Register 0 */ #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ @@ -731,7 +741,7 @@ typedef void (*ExcpHndlr) (void) ; #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ -#define UICR1 __REG(0x40600008) /* UDC Interrupt Control Register 1 */ +#define UICR1 (0x40600008) /* UDC Interrupt Control Register 1 */ #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ @@ -742,7 +752,7 @@ typedef void (*ExcpHndlr) (void) ; #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ -#define USIR0 __REG(0x4060000C) /* UDC Status Interrupt Register 0 */ +#define USIR0 (0x4060000C) /* UDC Status Interrupt Register 0 */ #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ #define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ @@ -753,7 +763,7 @@ typedef void (*ExcpHndlr) (void) ; #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ -#define USIR1 __REG(0x40600010) /* UDC Status Interrupt Register 1 */ +#define USIR1 (0x40600010) /* UDC Status Interrupt Register 1 */ #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ @@ -765,8 +775,8 @@ typedef void (*ExcpHndlr) (void) ; #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ -#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ -#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ +#define UDCICR0 (0x40600004) /* UDC Interrupt Control Register0 */ +#define UDCICR1 (0x40600008) /* UDC Interrupt Control Register1 */ #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ @@ -777,8 +787,8 @@ typedef void (*ExcpHndlr) (void) ; #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ -#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ -#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ +#define UDCISR0 (0x4060000C) /* UDC Interrupt Status Register 0 */ +#define UDCISR1 (0x40600010) /* UDC Interrupt Status Register 1 */ #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ @@ -787,8 +797,8 @@ typedef void (*ExcpHndlr) (void) ; #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ -#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ -#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ +#define UDCFNR (0x40600014) /* UDC Frame Number Register */ +#define UDCOTGICR (0x40600018) /* UDC On-The-Go interrupt control */ #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ @@ -804,7 +814,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ #define UDCCSN(x) __REG2(0x40600100, (x) << 2) -#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ +#define UDCCSR0 (0x40600100) /* UDC Control/Status register - Endpoint 0 */ #define UDCCSR0_SA (1 << 7) /* Setup Active */ #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ @@ -815,29 +825,29 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ -#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ +#define UDCCSRA (0x40600104) /* UDC Control/Status register - Endpoint A */ +#define UDCCSRB (0x40600108) /* UDC Control/Status register - Endpoint B */ +#define UDCCSRC (0x4060010C) /* UDC Control/Status register - Endpoint C */ +#define UDCCSRD (0x40600110) /* UDC Control/Status register - Endpoint D */ +#define UDCCSRE (0x40600114) /* UDC Control/Status register - Endpoint E */ +#define UDCCSRF (0x40600118) /* UDC Control/Status register - Endpoint F */ +#define UDCCSRG (0x4060011C) /* UDC Control/Status register - Endpoint G */ +#define UDCCSRH (0x40600120) /* UDC Control/Status register - Endpoint H */ +#define UDCCSRI (0x40600124) /* UDC Control/Status register - Endpoint I */ +#define UDCCSRJ (0x40600128) /* UDC Control/Status register - Endpoint J */ +#define UDCCSRK (0x4060012C) /* UDC Control/Status register - Endpoint K */ +#define UDCCSRL (0x40600130) /* UDC Control/Status register - Endpoint L */ +#define UDCCSRM (0x40600134) /* UDC Control/Status register - Endpoint M */ +#define UDCCSRN (0x40600138) /* UDC Control/Status register - Endpoint N */ +#define UDCCSRP (0x4060013C) /* UDC Control/Status register - Endpoint P */ +#define UDCCSRQ (0x40600140) /* UDC Control/Status register - Endpoint Q */ +#define UDCCSRR (0x40600144) /* UDC Control/Status register - Endpoint R */ +#define UDCCSRS (0x40600148) /* UDC Control/Status register - Endpoint S */ +#define UDCCSRT (0x4060014C) /* UDC Control/Status register - Endpoint T */ +#define UDCCSRU (0x40600150) /* UDC Control/Status register - Endpoint U */ +#define UDCCSRV (0x40600154) /* UDC Control/Status register - Endpoint V */ +#define UDCCSRW (0x40600158) /* UDC Control/Status register - Endpoint W */ +#define UDCCSRX (0x4060015C) /* UDC Control/Status register - Endpoint X */ #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ @@ -852,81 +862,81 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_FS (1 << 0) /* FIFO needs service */ #define UDCBCN(x) __REG2(0x40600200, (x)<<2) -#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ -#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ -#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ -#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ -#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ -#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ -#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ -#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ -#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ -#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ -#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ -#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ -#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ -#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ -#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ -#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ -#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ -#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ -#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ -#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ -#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ -#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ -#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ -#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ +#define UDCBCR0 (0x40600200) /* Byte Count Register - EP0 */ +#define UDCBCRA (0x40600204) /* Byte Count Register - EPA */ +#define UDCBCRB (0x40600208) /* Byte Count Register - EPB */ +#define UDCBCRC (0x4060020C) /* Byte Count Register - EPC */ +#define UDCBCRD (0x40600210) /* Byte Count Register - EPD */ +#define UDCBCRE (0x40600214) /* Byte Count Register - EPE */ +#define UDCBCRF (0x40600218) /* Byte Count Register - EPF */ +#define UDCBCRG (0x4060021C) /* Byte Count Register - EPG */ +#define UDCBCRH (0x40600220) /* Byte Count Register - EPH */ +#define UDCBCRI (0x40600224) /* Byte Count Register - EPI */ +#define UDCBCRJ (0x40600228) /* Byte Count Register - EPJ */ +#define UDCBCRK (0x4060022C) /* Byte Count Register - EPK */ +#define UDCBCRL (0x40600230) /* Byte Count Register - EPL */ +#define UDCBCRM (0x40600234) /* Byte Count Register - EPM */ +#define UDCBCRN (0x40600238) /* Byte Count Register - EPN */ +#define UDCBCRP (0x4060023C) /* Byte Count Register - EPP */ +#define UDCBCRQ (0x40600240) /* Byte Count Register - EPQ */ +#define UDCBCRR (0x40600244) /* Byte Count Register - EPR */ +#define UDCBCRS (0x40600248) /* Byte Count Register - EPS */ +#define UDCBCRT (0x4060024C) /* Byte Count Register - EPT */ +#define UDCBCRU (0x40600250) /* Byte Count Register - EPU */ +#define UDCBCRV (0x40600254) /* Byte Count Register - EPV */ +#define UDCBCRW (0x40600258) /* Byte Count Register - EPW */ +#define UDCBCRX (0x4060025C) /* Byte Count Register - EPX */ #define UDCDN(x) __REG2(0x40600300, (x)<<2) -#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ -#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ -#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ -#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ -#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ -#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ -#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ -#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ -#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ -#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ -#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ -#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ -#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ -#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ -#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ -#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ -#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ -#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ -#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ -#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ -#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ -#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ -#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ -#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ +#define UDCDR0 (0x40600300) /* Data Register - EP0 */ +#define UDCDRA (0x40600304) /* Data Register - EPA */ +#define UDCDRB (0x40600308) /* Data Register - EPB */ +#define UDCDRC (0x4060030C) /* Data Register - EPC */ +#define UDCDRD (0x40600310) /* Data Register - EPD */ +#define UDCDRE (0x40600314) /* Data Register - EPE */ +#define UDCDRF (0x40600318) /* Data Register - EPF */ +#define UDCDRG (0x4060031C) /* Data Register - EPG */ +#define UDCDRH (0x40600320) /* Data Register - EPH */ +#define UDCDRI (0x40600324) /* Data Register - EPI */ +#define UDCDRJ (0x40600328) /* Data Register - EPJ */ +#define UDCDRK (0x4060032C) /* Data Register - EPK */ +#define UDCDRL (0x40600330) /* Data Register - EPL */ +#define UDCDRM (0x40600334) /* Data Register - EPM */ +#define UDCDRN (0x40600338) /* Data Register - EPN */ +#define UDCDRP (0x4060033C) /* Data Register - EPP */ +#define UDCDRQ (0x40600340) /* Data Register - EPQ */ +#define UDCDRR (0x40600344) /* Data Register - EPR */ +#define UDCDRS (0x40600348) /* Data Register - EPS */ +#define UDCDRT (0x4060034C) /* Data Register - EPT */ +#define UDCDRU (0x40600350) /* Data Register - EPU */ +#define UDCDRV (0x40600354) /* Data Register - EPV */ +#define UDCDRW (0x40600358) /* Data Register - EPW */ +#define UDCDRX (0x4060035C) /* Data Register - EPX */ #define UDCCN(x) __REG2(0x40600400, (x)<<2) -#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ -#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ -#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ -#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ -#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ -#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ -#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ -#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ -#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ -#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ -#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ -#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ -#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ -#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ -#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ -#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ -#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ -#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ -#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ -#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ -#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ -#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ -#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ +#define UDCCRA (0x40600404) /* Configuration register EPA */ +#define UDCCRB (0x40600408) /* Configuration register EPB */ +#define UDCCRC (0x4060040C) /* Configuration register EPC */ +#define UDCCRD (0x40600410) /* Configuration register EPD */ +#define UDCCRE (0x40600414) /* Configuration register EPE */ +#define UDCCRF (0x40600418) /* Configuration register EPF */ +#define UDCCRG (0x4060041C) /* Configuration register EPG */ +#define UDCCRH (0x40600420) /* Configuration register EPH */ +#define UDCCRI (0x40600424) /* Configuration register EPI */ +#define UDCCRJ (0x40600428) /* Configuration register EPJ */ +#define UDCCRK (0x4060042C) /* Configuration register EPK */ +#define UDCCRL (0x40600430) /* Configuration register EPL */ +#define UDCCRM (0x40600434) /* Configuration register EPM */ +#define UDCCRN (0x40600438) /* Configuration register EPN */ +#define UDCCRP (0x4060043C) /* Configuration register EPP */ +#define UDCCRQ (0x40600440) /* Configuration register EPQ */ +#define UDCCRR (0x40600444) /* Configuration register EPR */ +#define UDCCRS (0x40600448) /* Configuration register EPS */ +#define UDCCRT (0x4060044C) /* Configuration register EPT */ +#define UDCCRU (0x40600450) /* Configuration register EPU */ +#define UDCCRV (0x40600454) /* Configuration register EPV */ +#define UDCCRW (0x40600458) /* Configuration register EPW */ +#define UDCCRX (0x4060045C) /* Configuration register EPX */ #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ #define UDCCONR_CN_S (25) @@ -959,38 +969,39 @@ typedef void (*ExcpHndlr) (void) ; #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +/******************************************************************************/ /* * USB Host Controller */ #define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ -#define UHCREV __REG(0x4C000000) -#define UHCHCON __REG(0x4C000004) -#define UHCCOMS __REG(0x4C000008) -#define UHCINTS __REG(0x4C00000C) -#define UHCINTE __REG(0x4C000010) -#define UHCINTD __REG(0x4C000014) -#define UHCHCCA __REG(0x4C000018) -#define UHCPCED __REG(0x4C00001C) -#define UHCCHED __REG(0x4C000020) -#define UHCCCED __REG(0x4C000024) -#define UHCBHED __REG(0x4C000028) -#define UHCBCED __REG(0x4C00002C) -#define UHCDHEAD __REG(0x4C000030) -#define UHCFMI __REG(0x4C000034) -#define UHCFMR __REG(0x4C000038) -#define UHCFMN __REG(0x4C00003C) -#define UHCPERS __REG(0x4C000040) -#define UHCLST __REG(0x4C000044) -#define UHCRHDA __REG(0x4C000048) -#define UHCRHDB __REG(0x4C00004C) -#define UHCRHS __REG(0x4C000050) -#define UHCRHPS1 __REG(0x4C000054) -#define UHCRHPS2 __REG(0x4C000058) -#define UHCRHPS3 __REG(0x4C00005C) -#define UHCSTAT __REG(0x4C000060) -#define UHCHR __REG(0x4C000064) -#define UHCHIE __REG(0x4C000068) -#define UHCHIT __REG(0x4C00006C) +#define UHCREV (0x4C000000) +#define UHCHCON (0x4C000004) +#define UHCCOMS (0x4C000008) +#define UHCINTS (0x4C00000C) +#define UHCINTE (0x4C000010) +#define UHCINTD (0x4C000014) +#define UHCHCCA (0x4C000018) +#define UHCPCED (0x4C00001C) +#define UHCCHED (0x4C000020) +#define UHCCCED (0x4C000024) +#define UHCBHED (0x4C000028) +#define UHCBCED (0x4C00002C) +#define UHCDHEAD (0x4C000030) +#define UHCFMI (0x4C000034) +#define UHCFMR (0x4C000038) +#define UHCFMN (0x4C00003C) +#define UHCPERS (0x4C000040) +#define UHCLST (0x4C000044) +#define UHCRHDA (0x4C000048) +#define UHCRHDB (0x4C00004C) +#define UHCRHS (0x4C000050) +#define UHCRHPS1 (0x4C000054) +#define UHCRHPS2 (0x4C000058) +#define UHCRHPS3 (0x4C00005C) +#define UHCSTAT (0x4C000060) +#define UHCHR (0x4C000064) +#define UHCHIE (0x4C000068) +#define UHCHIT (0x4C00006C) #define UHCHR_FSBIR (1<<0) #define UHCHR_FHR (1<<1) @@ -1011,9 +1022,7 @@ typedef void (*ExcpHndlr) (void) ; #define UHCHIE_HBAIE (1<<8) #define UHCHIE_RWIE (1<<7) -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) -#define UP2OCR __REG(0x40600020) -#endif +#define UP2OCR (0x40600020) #define UP2OCR_HXOE (1<<17) #define UP2OCR_HXS (1<<16) @@ -1029,36 +1038,37 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +/******************************************************************************/ /* * Fast Infrared Communication Port */ -#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ -#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ -#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ -#define ICDR __REG(0x4080000c) /* ICP Data Register */ -#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ -#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ +#define ICCR0 (0x40800000) /* ICP Control Register 0 */ +#define ICCR1 (0x40800004) /* ICP Control Register 1 */ +#define ICCR2 (0x40800008) /* ICP Control Register 2 */ +#define ICDR (0x4080000c) /* ICP Data Register */ +#define ICSR0 (0x40800014) /* ICP Status Register 0 */ +#define ICSR1 (0x40800018) /* ICP Status Register 1 */ /* * Real Time Clock */ -#define RCNR __REG(0x40900000) /* RTC Count Register */ -#define RTAR __REG(0x40900004) /* RTC Alarm Register */ -#define RTSR __REG(0x40900008) /* RTC Status Register */ -#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ -#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */ -#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */ -#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ -#define RDCR __REG(0x40900010) /* RTC Day Count Register. */ -#define RYCR __REG(0x40900014) /* RTC Year Count Register. */ -#define SWCR __REG(0x40900028) /* Stopwatch Count Register */ -#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */ +#define RCNR (0x40900000) /* RTC Count Register */ +#define RTAR (0x40900004) /* RTC Alarm Register */ +#define RTSR (0x40900008) /* RTC Status Register */ +#define RTTR (0x4090000C) /* RTC Timer Trim Register */ +#define RDAR1 (0x40900018) /* Wristwatch Day Alarm Reg 1 */ +#define RDAR2 (0x40900020) /* Wristwatch Day Alarm Reg 2 */ +#define RYAR1 (0x4090001C) /* Wristwatch Year Alarm Reg 1 */ +#define RYAR2 (0x40900024) /* Wristwatch Year Alarm Reg 2 */ +#define SWAR1 (0x4090002C) /* Stopwatch Alarm Register 1 */ +#define SWAR2 (0x40900030) /* Stopwatch Alarm Register 2 */ +#define PIAR (0x40900038) /* Periodic Interrupt Alarm Register */ +#define RDCR (0x40900010) /* RTC Day Count Register. */ +#define RYCR (0x40900014) /* RTC Year Count Register. */ +#define SWCR (0x40900028) /* Stopwatch Count Register */ +#define RTCPICR (0x40900034) /* Periodic Interrupt Counter Register */ #define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ #define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ @@ -1068,48 +1078,48 @@ typedef void (*ExcpHndlr) (void) ; #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ #define RTSR_AL (1 << 0) /* RTC alarm detected */ +/******************************************************************************/ /* * OS Timer & Match Registers */ -#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */ -#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */ -#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */ -#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */ -#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ -#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ -#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ -#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ +#define OSMR0 (0x40A00000) /* OS Timer Match Register 0 */ +#define OSMR1 (0x40A00004) /* OS Timer Match Register 1 */ +#define OSMR2 (0x40A00008) /* OS Timer Match Register 2 */ +#define OSMR3 (0x40A0000C) /* OS Timer Match Register 3 */ +#define OSCR (0x40A00010) /* OS Timer Counter Register */ +#define OSSR (0x40A00014) /* OS Timer Status Register */ +#define OWER (0x40A00018) /* OS Timer Watchdog Enable Register */ +#define OIER (0x40A0001C) /* OS Timer Interrupt Enable Register */ -#ifdef CONFIG_CPU_MONAHANS -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */ -#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */ -#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */ -#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */ -#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */ -#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */ -#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */ -#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */ - -#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */ -#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */ -#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */ -#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */ -#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */ -#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */ -#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */ -#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */ - -#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */ -#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */ -#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */ -#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */ -#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */ -#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */ -#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */ -#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */ - -#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */ -#endif /* CONFIG_CPU_MONAHANS */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define OSCR4 (0x40A00040) /* OS Timer Counter Register 4 */ +#define OSCR5 (0x40A00044) /* OS Timer Counter Register 5 */ +#define OSCR6 (0x40A00048) /* OS Timer Counter Register 6 */ +#define OSCR7 (0x40A0004C) /* OS Timer Counter Register 7 */ +#define OSCR8 (0x40A00050) /* OS Timer Counter Register 8 */ +#define OSCR9 (0x40A00054) /* OS Timer Counter Register 9 */ +#define OSCR10 (0x40A00058) /* OS Timer Counter Register 10 */ +#define OSCR11 (0x40A0005C) /* OS Timer Counter Register 11 */ + +#define OSMR4 (0x40A00080) /* OS Timer Match Register 4 */ +#define OSMR5 (0x40A00084) /* OS Timer Match Register 5 */ +#define OSMR6 (0x40A00088) /* OS Timer Match Register 6 */ +#define OSMR7 (0x40A0008C) /* OS Timer Match Register 7 */ +#define OSMR8 (0x40A00090) /* OS Timer Match Register 8 */ +#define OSMR9 (0x40A00094) /* OS Timer Match Register 9 */ +#define OSMR10 (0x40A00098) /* OS Timer Match Register 10 */ +#define OSMR11 (0x40A0009C) /* OS Timer Match Register 11 */ + +#define OMCR4 (0x40A000C0) /* OS Match Control Register 4 */ +#define OMCR5 (0x40A000C4) /* OS Match Control Register 5 */ +#define OMCR6 (0x40A000C8) /* OS Match Control Register 6 */ +#define OMCR7 (0x40A000CC) /* OS Match Control Register 7 */ +#define OMCR8 (0x40A000D0) /* OS Match Control Register 8 */ +#define OMCR9 (0x40A000D4) /* OS Match Control Register 9 */ +#define OMCR10 (0x40A000D8) /* OS Match Control Register 10 */ +#define OMCR11 (0x40A000DC) /* OS Match Control Register 11 */ + +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1125,321 +1135,696 @@ typedef void (*ExcpHndlr) (void) ; #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ +#define OSCR_CLK_FREQ 3250 + +/******************************************************************************/ /* - * Pulse Width Modulator + * Core Clock */ -#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ -#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */ -#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ +#if defined(CONFIG_CPU_MONAHANS) +#define ACCR (0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR (0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR (0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA (0x4134000C) /* A Clock Enable Register */ +#define CKENB (0x41340010) /* B Clock Enable Register */ +#define AC97_DIV (0x41340014) /* AC97 clock divisor value register */ + +#define ACCR_SMC_MASK (0x03800000) /* Static Memory Controller Frequency Select */ +#define ACCR_SRAM_MASK (0x000c0000) /* SRAM Controller Frequency Select */ +#define ACCR_FC_MASK (0x00030000) /* Frequency Change Frequency Select */ +#define ACCR_HSIO_MASK (0x0000c000) /* High Speed IO Frequency Select */ +#define ACCR_DDR_MASK (0x00003000) /* DDR Memory Controller Frequency Select */ +#define ACCR_XN_MASK (0x00000700) /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define ACCR_XL_MASK (0x0000001f) /* Crystal Frequency to Memory Frequency Multiplier */ +#define ACCR_XPDIS (1 << 31) +#define ACCR_SPDIS (1 << 30) +#define ACCR_13MEND1 (1 << 27) +#define ACCR_D0CS (1 << 26) +#define ACCR_13MEND2 (1 << 21) +#define ACCR_PCCE (1 << 11) + +#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ +#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ +#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ +#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ +#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ +#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ +#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ +#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ +#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ +#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ +#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ +#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ +#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ +#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ +#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ +#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ +#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ +#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ +#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ +#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ +#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ +#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ +#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ +#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ +#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ +#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ +#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ +#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ + +#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ +#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ + +#else /* if defined CONFIG_CPU_MONAHANS */ + +#define CCCR (0x41300000) /* Core Clock Configuration Register */ +#define CKEN (0x41300004) /* Clock Enable Register */ +#define OSCC (0x41300008) /* Oscillator Configuration Register */ +#define CCSR (0x4130000C) /* Core Clock Status Register */ + +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controler */ +#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ +#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ +#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ +#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#if !defined(CONFIG_PXA27X) +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#endif +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */ -#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */ -#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */ +#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ +#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ +#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ +#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ +#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ +#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ +#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ +#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ +#if defined(CONFIG_PXA27X) +#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ +#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ +#endif +#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ +#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ +#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ +#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ +#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ +#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ +#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ -#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */ -#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */ -#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */ +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ +#if !defined(CONFIG_PXA27X) +#define CCCR_L09 (0x1F) +#define CCCR_L27 (0x1) +#define CCCR_L32 (0x2) +#define CCCR_L36 (0x3) +#define CCCR_L40 (0x4) +#define CCCR_L45 (0x5) + +#define CCCR_M1 (0x1 << 5) +#define CCCR_M2 (0x2 << 5) +#define CCCR_M4 (0x3 << 5) + +#define CCCR_N10 (0x2 << 7) +#define CCCR_N15 (0x3 << 7) +#define CCCR_N20 (0x4 << 7) +#define CCCR_N25 (0x5 << 7) +#define CCCR_N30 (0x6 << 7) +#endif + +#endif /* CONFIG_CPU_MONAHANS */ + +/******************************************************************************/ /* - * Interrupt Controller + * Pulse Width Modulator */ -#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ -#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ -#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ -#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ -#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ -#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#define PWM_CTRL0 (0x40B00000) /* PWM 0 Control Register */ +#define PWM_PWDUTY0 (0x40B00004) /* PWM 0 Duty Cycle Register */ +#define PWM_PERVAL0 (0x40B00008) /* PWM 0 Period Control Register */ -#ifdef CONFIG_CPU_MONAHANS -#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ -/* Missing: 32 Interrupt priority registers - * These are the same as beneath for PXA27x: maybe can be merged if - * GPIO Stuff is same too. +#define PWM_CTRL1 (0x40C00000) /* PWM 1 Control Register */ +#define PWM_PWDUTY1 (0x40C00004) /* PWM 1 Duty Cycle Register */ +#define PWM_PERVAL1 (0x40C00008) /* PWM 1 Period Control Register */ + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define PWM_CTRL2 (0x40B00010) /* PWM 2 Control Register */ +#define PWM_PWDUTY2 (0x40B00014) /* PWM 2 Duty Cycle Register */ +#define PWM_PERVAL2 (0x40B00018) /* PWM 2 Period Control Register */ + +#define PWM_CTRL3 (0x40C00010) /* PWM 3 Control Register */ +#define PWM_PWDUTY3 (0x40C00014) /* PWM 3 Duty Cycle Register */ +#define PWM_PERVAL3 (0x40C00018) /* PWM 3 Period Control Register */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +/* + * Interrupt Controller */ -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ -/* Missing: 2 Interrupt priority registers */ -#endif /* CONFIG_CPU_MONAHANS */ +#define ICIP (0x40D00000) /* Interrupt Controller IRQ Pending Register */ +#define ICMR (0x40D00004) /* Interrupt Controller Mask Register */ +#define ICLR (0x40D00008) /* Interrupt Controller Level Register */ +#define ICFP (0x40D0000C) /* Interrupt Controller FIQ Pending Register */ +#define ICPR (0x40D00010) /* Interrupt Controller Pending Register */ +#define ICCR (0x40D00014) /* Interrupt Controller Control Register */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define ICHP (0x40D00018) /* Interrupt Controller Highest Priority Register */ +#define ICIP2 (0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 (0x40D000A0) /* Interrupt Controller Mask Register 2 */ +#define ICLR2 (0x40D000A4) /* Interrupt Controller Level Register 2 */ +#define ICFP2 (0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 (0x40D000AC) /* Interrupt Controller Pending Register 2 */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +/******************************************************************************/ /* * General Purpose I/O */ -#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ -#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ +#define GPLR0 (0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ +#define GPLR1 (0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ +#define GPLR2 (0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ -#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ +#define GPDR0 (0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ +#define GPDR1 (0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ +#define GPDR2 (0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ -#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ +#define GPSR0 (0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ +#define GPSR1 (0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ +#define GPSR2 (0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ -#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ +#define GPCR0 (0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ +#define GPCR1 (0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 (0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ -#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ +#define GRER0 (0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ +#define GRER1 (0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ +#define GRER2 (0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ -#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ +#define GFER0 (0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GFER1 (0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ +#define GFER2 (0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ -#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ +#define GEDR0 (0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ +#define GEDR1 (0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ +#define GEDR2 (0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ + +#define GAFR0_L (0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ +#define GAFR0_U (0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ +#define GAFR1_L (0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ +#define GAFR1_U (0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ +#define GAFR2_L (0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ +#define GAFR2_U (0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR3 (0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ +#define GPDR3 (0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ +#define GPSR3 (0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ +#define GPCR3 (0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ +#define GRER3 (0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ +#define GFER3 (0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ +#define GEDR3 (0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ +#define GAFR3_L (0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ +#define GAFR3_U (0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3) -#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3) - -/* Multi-funktion Pin Registers, uncomplete, only: - * - GPIO - * - Data Flash DF_* pins defined. +#define GSDR0 (0x40E00400) /* Bit-wise Set of GPDR[31:0] */ +#define GSDR1 (0x40E00404) /* Bit-wise Set of GPDR[63:32] */ +#define GSDR2 (0x40E00408) /* Bit-wise Set of GPDR[95:64] */ +#define GSDR3 (0x40E0040C) /* Bit-wise Set of GPDR[127:96] */ + +#define GCDR0 (0x40E00420) /* Bit-wise Clear of GPDR[31:0] */ +#define GCDR1 (0x40E00424) /* Bit-wise Clear of GPDR[63:32] */ +#define GCDR2 (0x40E00428) /* Bit-wise Clear of GPDR[95:64] */ +#define GCDR3 (0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ + +#define GSRER0 (0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ +#define GSRER1 (0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ +#define GSRER2 (0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ +#define GSRER3 (0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ + +#define GCRER0 (0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ +#define GCRER1 (0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ +#define GCRER2 (0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ +#define GCRER3 (0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ + +#define GSFER0 (0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ +#define GSFER1 (0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ +#define GSFER2 (0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ +#define GSFER3 (0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ + +#define GCFER0 (0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ +#define GCFER1 (0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ +#define GCFER2 (0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ +#define GCFER3 (0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ + +#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) +#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) +#endif + +#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) +#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) +#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) +#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) +#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) +#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) +#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) +#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) +#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) +#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) +#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) +#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) +#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) +#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) +#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ + ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) +#else +#define GPLR(x) _GPLR(x) +#define GPDR(x) _GPDR(x) +#define GPSR(x) _GPSR(x) +#define GPCR(x) _GPCR(x) +#define GRER(x) _GRER(x) +#define GFER(x) _GFER(x) +#define GEDR(x) _GEDR(x) +#define GAFR(x) _GAFR(x) +#endif + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) + +/******************************************************************************/ +/* + * Multi-function Pin Registers: */ -#define GPIO0 __REG(0x40e10124) -#define GPIO1 __REG(0x40e10128) -#define GPIO2 __REG(0x40e1012c) -#define GPIO3 __REG(0x40e10130) -#define GPIO4 __REG(0x40e10134) -#define nXCVREN __REG(0x40e10138) - -#define DF_CLE_NOE __REG(0x40e10204) -#define DF_ALE_WE1 __REG(0x40e10208) - -#define DF_SCLK_E __REG(0x40e10210) -#define nBE0 __REG(0x40e10214) -#define nBE1 __REG(0x40e10218) -#define DF_ALE_WE2 __REG(0x40e1021c) -#define DF_INT_RnB __REG(0x40e10220) -#define DF_nCS0 __REG(0x40e10224) -#define DF_nCS1 __REG(0x40e10228) -#define DF_nWE __REG(0x40e1022c) -#define DF_nRE __REG(0x40e10230) -#define nLUA __REG(0x40e10234) -#define nLLA __REG(0x40e10238) -#define DF_ADDR0 __REG(0x40e1023c) -#define DF_ADDR1 __REG(0x40e10240) -#define DF_ADDR2 __REG(0x40e10244) -#define DF_ADDR3 __REG(0x40e10248) -#define DF_IO0 __REG(0x40e1024c) -#define DF_IO8 __REG(0x40e10250) -#define DF_IO1 __REG(0x40e10254) -#define DF_IO9 __REG(0x40e10258) -#define DF_IO2 __REG(0x40e1025c) -#define DF_IO10 __REG(0x40e10260) -#define DF_IO3 __REG(0x40e10264) -#define DF_IO11 __REG(0x40e10268) -#define DF_IO4 __REG(0x40e1026c) -#define DF_IO12 __REG(0x40e10270) -#define DF_IO5 __REG(0x40e10274) -#define DF_IO13 __REG(0x40e10278) -#define DF_IO6 __REG(0x40e1027c) -#define DF_IO14 __REG(0x40e10280) -#define DF_IO7 __REG(0x40e10284) -#define DF_IO15 __REG(0x40e10288) - -#define GPIO5 __REG(0x40e1028c) -#define GPIO6 __REG(0x40e10290) -#define GPIO7 __REG(0x40e10294) -#define GPIO8 __REG(0x40e10298) -#define GPIO9 __REG(0x40e1029c) - -#define GPIO11 __REG(0x40e102a0) -#define GPIO12 __REG(0x40e102a4) -#define GPIO13 __REG(0x40e102a8) -#define GPIO14 __REG(0x40e102ac) -#define GPIO15 __REG(0x40e102b0) -#define GPIO16 __REG(0x40e102b4) -#define GPIO17 __REG(0x40e102b8) -#define GPIO18 __REG(0x40e102bc) -#define GPIO19 __REG(0x40e102c0) -#define GPIO20 __REG(0x40e102c4) -#define GPIO21 __REG(0x40e102c8) -#define GPIO22 __REG(0x40e102cc) -#define GPIO23 __REG(0x40e102d0) -#define GPIO24 __REG(0x40e102d4) -#define GPIO25 __REG(0x40e102d8) -#define GPIO26 __REG(0x40e102dc) - -#define GPIO27 __REG(0x40e10400) -#define GPIO28 __REG(0x40e10404) -#define GPIO29 __REG(0x40e10408) -#define GPIO30 __REG(0x40e1040c) -#define GPIO31 __REG(0x40e10410) -#define GPIO32 __REG(0x40e10414) -#define GPIO33 __REG(0x40e10418) -#define GPIO34 __REG(0x40e1041c) -#define GPIO35 __REG(0x40e10420) -#define GPIO36 __REG(0x40e10424) -#define GPIO37 __REG(0x40e10428) -#define GPIO38 __REG(0x40e1042c) -#define GPIO39 __REG(0x40e10430) -#define GPIO40 __REG(0x40e10434) -#define GPIO41 __REG(0x40e10438) -#define GPIO42 __REG(0x40e1043c) -#define GPIO43 __REG(0x40e10440) -#define GPIO44 __REG(0x40e10444) -#define GPIO45 __REG(0x40e10448) -#define GPIO46 __REG(0x40e1044c) -#define GPIO47 __REG(0x40e10450) -#define GPIO48 __REG(0x40e10454) - -#define GPIO10 __REG(0x40e10458) - -#define GPIO49 __REG(0x40e1045c) -#define GPIO50 __REG(0x40e10460) -#define GPIO51 __REG(0x40e10464) -#define GPIO52 __REG(0x40e10468) -#define GPIO53 __REG(0x40e1046c) -#define GPIO54 __REG(0x40e10470) -#define GPIO55 __REG(0x40e10474) -#define GPIO56 __REG(0x40e10478) -#define GPIO57 __REG(0x40e1047c) -#define GPIO58 __REG(0x40e10480) -#define GPIO59 __REG(0x40e10484) -#define GPIO60 __REG(0x40e10488) -#define GPIO61 __REG(0x40e1048c) -#define GPIO62 __REG(0x40e10490) - -#define GPIO6_2 __REG(0x40e10494) -#define GPIO7_2 __REG(0x40e10498) -#define GPIO8_2 __REG(0x40e1049c) -#define GPIO9_2 __REG(0x40e104a0) -#define GPIO10_2 __REG(0x40e104a4) -#define GPIO11_2 __REG(0x40e104a8) -#define GPIO12_2 __REG(0x40e104ac) -#define GPIO13_2 __REG(0x40e104b0) - -#define GPIO63 __REG(0x40e104b4) -#define GPIO64 __REG(0x40e104b8) -#define GPIO65 __REG(0x40e104bc) -#define GPIO66 __REG(0x40e104c0) -#define GPIO67 __REG(0x40e104c4) -#define GPIO68 __REG(0x40e104c8) -#define GPIO69 __REG(0x40e104cc) -#define GPIO70 __REG(0x40e104d0) -#define GPIO71 __REG(0x40e104d4) -#define GPIO72 __REG(0x40e104d8) -#define GPIO73 __REG(0x40e104dc) - -#define GPIO14_2 __REG(0x40e104e0) -#define GPIO15_2 __REG(0x40e104e4) -#define GPIO16_2 __REG(0x40e104e8) -#define GPIO17_2 __REG(0x40e104ec) - -#define GPIO74 __REG(0x40e104f0) -#define GPIO75 __REG(0x40e104f4) -#define GPIO76 __REG(0x40e104f8) -#define GPIO77 __REG(0x40e104fc) -#define GPIO78 __REG(0x40e10500) -#define GPIO79 __REG(0x40e10504) -#define GPIO80 __REG(0x40e10508) -#define GPIO81 __REG(0x40e1050c) -#define GPIO82 __REG(0x40e10510) -#define GPIO83 __REG(0x40e10514) -#define GPIO84 __REG(0x40e10518) -#define GPIO85 __REG(0x40e1051c) -#define GPIO86 __REG(0x40e10520) -#define GPIO87 __REG(0x40e10524) -#define GPIO88 __REG(0x40e10528) -#define GPIO89 __REG(0x40e1052c) -#define GPIO90 __REG(0x40e10530) -#define GPIO91 __REG(0x40e10534) -#define GPIO92 __REG(0x40e10538) -#define GPIO93 __REG(0x40e1053c) -#define GPIO94 __REG(0x40e10540) -#define GPIO95 __REG(0x40e10544) -#define GPIO96 __REG(0x40e10548) -#define GPIO97 __REG(0x40e1054c) -#define GPIO98 __REG(0x40e10550) - -#define GPIO99 __REG(0x40e10600) -#define GPIO100 __REG(0x40e10604) -#define GPIO101 __REG(0x40e10608) -#define GPIO102 __REG(0x40e1060c) -#define GPIO103 __REG(0x40e10610) -#define GPIO104 __REG(0x40e10614) -#define GPIO105 __REG(0x40e10618) -#define GPIO106 __REG(0x40e1061c) -#define GPIO107 __REG(0x40e10620) -#define GPIO108 __REG(0x40e10624) -#define GPIO109 __REG(0x40e10628) -#define GPIO110 __REG(0x40e1062c) -#define GPIO111 __REG(0x40e10630) -#define GPIO112 __REG(0x40e10634) - -#define GPIO113 __REG(0x40e10638) -#define GPIO114 __REG(0x40e1063c) -#define GPIO115 __REG(0x40e10640) -#define GPIO116 __REG(0x40e10644) -#define GPIO117 __REG(0x40e10648) -#define GPIO118 __REG(0x40e1064c) -#define GPIO119 __REG(0x40e10650) -#define GPIO120 __REG(0x40e10654) -#define GPIO121 __REG(0x40e10658) -#define GPIO122 __REG(0x40e1065c) -#define GPIO123 __REG(0x40e10660) -#define GPIO124 __REG(0x40e10664) -#define GPIO125 __REG(0x40e10668) -#define GPIO126 __REG(0x40e1066c) -#define GPIO127 __REG(0x40e10670) - -#define GPIO0_2 __REG(0x40e10674) -#define GPIO1_2 __REG(0x40e10678) -#define GPIO2_2 __REG(0x40e1067c) -#define GPIO3_2 __REG(0x40e10680) -#define GPIO4_2 __REG(0x40e10684) -#define GPIO5_2 __REG(0x40e10688) +/* PXA320 */ +#if defined(CONFIG_CPU_PXA320) +#define DF_IO0 (0x40e1024c) +#define DF_IO1 (0x40e10254) +#define DF_IO2 (0x40e1025c) +#define DF_IO3 (0x40e10264) +#define DF_IO4 (0x40e1026c) +#define DF_IO5 (0x40e10274) +#define DF_IO6 (0x40e1027c) +#define DF_IO7 (0x40e10284) +#define DF_IO8 (0x40e10250) +#define DF_IO9 (0x40e10258) +#define DF_IO10 (0x40e10260) +#define DF_IO11 (0x40e10268) +#define DF_IO12 (0x40e10270) +#define DF_IO13 (0x40e10278) +#define DF_IO14 (0x40e10280) +#define DF_IO15 (0x40e10288) +#define DF_CLE_nOE (0x40e10204) +#define DF_ALE_nWE1 (0x40e10208) +#define DF_ALE_nWE2 (0x40e1021c) +#define DF_SCLK_E (0x40e10210) +#define DF_nCS0 (0x40e10224) +#define DF_nCS1 (0x40e10228) +#define nBE0 (0x40e10214) +#define nBE1 (0x40e10218) +#define nLUA (0x40e10234) +#define nLLA (0x40e10238) +#define DF_ADDR0 (0x40e1023c) +#define DF_ADDR1 (0x40e10240) +#define DF_ADDR2 (0x40e10244) +#define DF_ADDR3 (0x40e10248) +#define DF_INT_RnB (0x40e10220) +#define DF_nCS0 (0x40e10224) +#define DF_nCS1 (0x40e10228) +#define DF_nWE (0x40e1022c) +#define DF_nRE (0x40e10230) + +#define nXCVREN (0x40e10138) + +#define GPIO0 (0x40e10124) +#define GPIO1 (0x40e10128) +#define GPIO2 (0x40e1012c) +#define GPIO3 (0x40e10130) +#define GPIO4 (0x40e10134) +#define GPIO5 (0x40e1028c) +#define GPIO6 (0x40e10290) +#define GPIO7 (0x40e10294) +#define GPIO8 (0x40e10298) +#define GPIO9 (0x40e1029c) +#define GPIO10 (0x40e10458) +#define GPIO11 (0x40e102a0) +#define GPIO12 (0x40e102a4) +#define GPIO13 (0x40e102a8) +#define GPIO14 (0x40e102ac) +#define GPIO15 (0x40e102b0) +#define GPIO16 (0x40e102b4) +#define GPIO17 (0x40e102b8) +#define GPIO18 (0x40e102bc) +#define GPIO19 (0x40e102c0) +#define GPIO20 (0x40e102c4) +#define GPIO21 (0x40e102c8) +#define GPIO22 (0x40e102cc) +#define GPIO23 (0x40e102d0) +#define GPIO24 (0x40e102d4) +#define GPIO25 (0x40e102d8) +#define GPIO26 (0x40e102dc) + +#define GPIO27 (0x40e10400) +#define GPIO28 (0x40e10404) +#define GPIO29 (0x40e10408) +#define GPIO30 (0x40e1040c) +#define GPIO31 (0x40e10410) +#define GPIO32 (0x40e10414) +#define GPIO33 (0x40e10418) +#define GPIO34 (0x40e1041c) +#define GPIO35 (0x40e10420) +#define GPIO36 (0x40e10424) +#define GPIO37 (0x40e10428) +#define GPIO38 (0x40e1042c) +#define GPIO39 (0x40e10430) +#define GPIO40 (0x40e10434) +#define GPIO41 (0x40e10438) +#define GPIO42 (0x40e1043c) +#define GPIO43 (0x40e10440) +#define GPIO44 (0x40e10444) +#define GPIO45 (0x40e10448) +#define GPIO46 (0x40e1044c) +#define GPIO47 (0x40e10450) +#define GPIO48 (0x40e10454) +#define GPIO49 (0x40e1045c) +#define GPIO50 (0x40e10460) +#define GPIO51 (0x40e10464) +#define GPIO52 (0x40e10468) +#define GPIO53 (0x40e1046c) +#define GPIO54 (0x40e10470) +#define GPIO55 (0x40e10474) +#define GPIO56 (0x40e10478) +#define GPIO57 (0x40e1047c) +#define GPIO58 (0x40e10480) +#define GPIO59 (0x40e10484) +#define GPIO60 (0x40e10488) +#define GPIO61 (0x40e1048c) +#define GPIO62 (0x40e10490) + +#define GPIO6_2 (0x40e10494) +#define GPIO7_2 (0x40e10498) +#define GPIO8_2 (0x40e1049c) +#define GPIO9_2 (0x40e104a0) +#define GPIO10_2 (0x40e104a4) +#define GPIO11_2 (0x40e104a8) +#define GPIO12_2 (0x40e104ac) +#define GPIO13_2 (0x40e104b0) + +#define GPIO63 (0x40e104b4) +#define GPIO64 (0x40e104b8) +#define GPIO65 (0x40e104bc) +#define GPIO66 (0x40e104c0) +#define GPIO67 (0x40e104c4) +#define GPIO68 (0x40e104c8) +#define GPIO69 (0x40e104cc) +#define GPIO70 (0x40e104d0) +#define GPIO71 (0x40e104d4) +#define GPIO72 (0x40e104d8) +#define GPIO73 (0x40e104dc) + +#define GPIO14_2 (0x40e104e0) +#define GPIO15_2 (0x40e104e4) +#define GPIO16_2 (0x40e104e8) +#define GPIO17_2 (0x40e104ec) + +#define GPIO74 (0x40e104f0) +#define GPIO75 (0x40e104f4) +#define GPIO76 (0x40e104f8) +#define GPIO77 (0x40e104fc) +#define GPIO78 (0x40e10500) +#define GPIO79 (0x40e10504) +#define GPIO80 (0x40e10508) +#define GPIO81 (0x40e1050c) +#define GPIO82 (0x40e10510) +#define GPIO83 (0x40e10514) +#define GPIO84 (0x40e10518) +#define GPIO85 (0x40e1051c) +#define GPIO86 (0x40e10520) +#define GPIO87 (0x40e10524) +#define GPIO88 (0x40e10528) +#define GPIO89 (0x40e1052c) +#define GPIO90 (0x40e10530) +#define GPIO91 (0x40e10534) +#define GPIO92 (0x40e10538) +#define GPIO93 (0x40e1053c) +#define GPIO94 (0x40e10540) +#define GPIO95 (0x40e10544) +#define GPIO96 (0x40e10548) +#define GPIO97 (0x40e1054c) +#define GPIO98 (0x40e10550) + +#define GPIO99 (0x40e10600) +#define GPIO100 (0x40e10604) +#define GPIO101 (0x40e10608) +#define GPIO102 (0x40e1060c) +#define GPIO103 (0x40e10610) +#define GPIO104 (0x40e10614) +#define GPIO105 (0x40e10618) +#define GPIO106 (0x40e1061c) +#define GPIO107 (0x40e10620) +#define GPIO108 (0x40e10624) +#define GPIO109 (0x40e10628) +#define GPIO110 (0x40e1062c) +#define GPIO111 (0x40e10630) +#define GPIO112 (0x40e10634) + +#define GPIO113 (0x40e10638) +#define GPIO114 (0x40e1063c) +#define GPIO115 (0x40e10640) +#define GPIO116 (0x40e10644) +#define GPIO117 (0x40e10648) +#define GPIO118 (0x40e1064c) +#define GPIO119 (0x40e10650) +#define GPIO120 (0x40e10654) +#define GPIO121 (0x40e10658) +#define GPIO122 (0x40e1065c) +#define GPIO123 (0x40e10660) +#define GPIO124 (0x40e10664) +#define GPIO125 (0x40e10668) +#define GPIO126 (0x40e1066c) +#define GPIO127 (0x40e10670) + +#define GPIO0_2 (0x40e10674) +#define GPIO1_2 (0x40e10678) +#define GPIO2_2 (0x40e1067c) +#define GPIO3_2 (0x40e10680) +#define GPIO4_2 (0x40e10684) +#define GPIO5_2 (0x40e10688) + +/* PXA300 and PXA310 */ +#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) +#define DF_IO0 (0x40e10220) +#define DF_IO1 (0x40e10228) +#define DF_IO2 (0x40e10230) +#define DF_IO3 (0x40e10238) +#define DF_IO4 (0x40e10258) +#define DF_IO5 (0x40e10260) +#define DF_IO7 (0x40e10270) +#define DF_IO6 (0x40e10268) +#define DF_IO8 (0x40e10224) +#define DF_IO9 (0x40e1022c) +#define DF_IO10 (0x40e10234) +#define DF_IO11 (0x40e1023c) +#define DF_IO12 (0x40e1025c) +#define DF_IO13 (0x40e10264) +#define DF_IO14 (0x40e1026c) +#define DF_IO15 (0x40e10274) +#define DF_CLE_NOE (0x40e10240) +#define DF_ALE_nWE (0x40e1020c) +#define DF_SCLK_E (0x40e10250) +#define nCS0 (0x40e100c4) +#define nCS1 (0x40e100c0) +#define nBE0 (0x40e10204) +#define nBE1 (0x40e10208) +#define nLUA (0x40e10244) +#define nLLA (0x40e10254) +#define DF_ADDR0 (0x40e10210) +#define DF_ADDR1 (0x40e10214) +#define DF_ADDR2 (0x40e10218) +#define DF_ADDR3 (0x40e1021c) +#define DF_INT_RnB (0x40e100c8) +#define DF_nCS0 (0x40e10248) +#define DF_nCS1 (0x40e10278) +#define DF_nWE (0x40e100cc) +#define DF_nRE (0x40e10200) + +#define GPIO0 (0x40e100b4) +#define GPIO1 (0x40e100b8) +#define GPIO2 (0x40e100bc) +#define GPIO3 (0x40e1027c) +#define GPIO4 (0x40e10280) + +#define GPIO5 (0x40e10284) +#define GPIO6 (0x40e10288) +#define GPIO7 (0x40e1028c) +#define GPIO8 (0x40e10290) +#define GPIO9 (0x40e10294) +#define GPIO10 (0x40e10298) +#define GPIO11 (0x40e1029c) +#define GPIO12 (0x40e102a0) +#define GPIO13 (0x40e102a4) +#define GPIO14 (0x40e102a8) +#define GPIO15 (0x40e102ac) +#define GPIO16 (0x40e102b0) +#define GPIO17 (0x40e102b4) +#define GPIO18 (0x40e102b8) +#define GPIO19 (0x40e102bc) +#define GPIO20 (0x40e102c0) +#define GPIO21 (0x40e102c4) +#define GPIO22 (0x40e102c8) +#define GPIO23 (0x40e102cc) +#define GPIO24 (0x40e102d0) +#define GPIO25 (0x40e102d4) +#define GPIO26 (0x40e102d8) + +#define GPIO27 (0x40e10400) +#define GPIO28 (0x40e10404) +#define GPIO29 (0x40e10408) +#define ULPI_STP (0x40e1040c) +#define ULPI_NXT (0x40e10410) +#define ULPI_DIR (0x40e10414) +#define GPIO30 (0x40e10418) +#define GPIO31 (0x40e1041c) +#define GPIO32 (0x40e10420) +#define GPIO33 (0x40e10424) +#define GPIO34 (0x40e10428) +#define GPIO35 (0x40e1042c) +#define GPIO36 (0x40e10430) +#define GPIO37 (0x40e10434) +#define GPIO38 (0x40e10438) +#define GPIO39 (0x40e1043c) +#define GPIO40 (0x40e10440) +#define GPIO41 (0x40e10444) +#define GPIO42 (0x40e10448) +#define GPIO43 (0x40e1044c) +#define GPIO44 (0x40e10450) +#define GPIO45 (0x40e10454) +#define GPIO46 (0x40e10458) +#define GPIO47 (0x40e1045c) +#define GPIO48 (0x40e10460) + +#define GPIO49 (0x40e10464) +#define GPIO50 (0x40e10468) +#define GPIO51 (0x40e1046c) +#define GPIO52 (0x40e10470) +#define GPIO53 (0x40e10474) +#define GPIO54 (0x40e10478) +#define GPIO55 (0x40e1047c) +#define GPIO56 (0x40e10480) +#define GPIO57 (0x40e10484) +#define GPIO58 (0x40e10488) +#define GPIO59 (0x40e1048c) +#define GPIO60 (0x40e10490) +#define GPIO61 (0x40e10494) +#define GPIO62 (0x40e10498) +#define GPIO63 (0x40e1049c) +#define GPIO64 (0x40e104a0) +#define GPIO65 (0x40e104a4) +#define GPIO66 (0x40e104a8) +#define GPIO67 (0x40e104ac) +#define GPIO68 (0x40e104b0) +#define GPIO69 (0x40e104b4) +#define GPIO70 (0x40e104b8) +#define GPIO71 (0x40e104bc) +#define GPIO72 (0x40e104c0) +#define GPIO73 (0x40e104c4) +#define GPIO74 (0x40e104c8) +#define GPIO75 (0x40e104cc) +#define GPIO76 (0x40e104d0) +#define GPIO77 (0x40e104d4) +#define GPIO78 (0x40e104d8) +#define GPIO79 (0x40e104dc) +#define GPIO80 (0x40e104e0) +#define GPIO81 (0x40e104e4) +#define GPIO82 (0x40e104e8) +#define GPIO83 (0x40e104ec) +#define GPIO84 (0x40e104f0) +#define GPIO85 (0x40e104f4) +#define GPIO86 (0x40e104f8) +#define GPIO87 (0x40e104fc) +#define GPIO88 (0x40e10500) +#define GPIO89 (0x40e10504) +#define GPIO90 (0x40e10508) +#define GPIO91 (0x40e1050c) +#define GPIO92 (0x40e10510) +#define GPIO93 (0x40e10514) +#define GPIO94 (0x40e10518) +#define GPIO95 (0x40e1051c) +#define GPIO96 (0x40e10520) +#define GPIO97 (0x40e10524) +#define GPIO98 (0x40e10528) + +#define GPIO99 (0x40e10600) +#define GPIO100 (0x40e10604) +#define GPIO101 (0x40e10608) +#define GPIO102 (0x40e1060c) +#define GPIO103 (0x40e10610) +#define GPIO104 (0x40e10614) +#define GPIO105 (0x40e10618) +#define GPIO106 (0x40e1061c) +#define GPIO107 (0x40e10620) +#define GPIO108 (0x40e10624) +#define GPIO109 (0x40e10628) +#define GPIO110 (0x40e1062c) +#define GPIO111 (0x40e10630) +#define GPIO112 (0x40e10634) + +#define GPIO113 (0x40e10638) +#define GPIO114 (0x40e1063c) +#define GPIO115 (0x40e10640) +#define GPIO116 (0x40e10644) +#define GPIO117 (0x40e10648) +#define GPIO118 (0x40e1064c) +#define GPIO119 (0x40e10650) +#define GPIO120 (0x40e10654) +#define GPIO121 (0x40e10658) +#define GPIO122 (0x40e1065c) +#define GPIO123 (0x40e10660) +#define GPIO124 (0x40e10664) +#define GPIO125 (0x40e10668) +#define GPIO126 (0x40e1066c) +#define GPIO127 (0x40e10670) + +#define GPIO0_2 (0x40e10674) +#define GPIO1_2 (0x40e10678) +#define GPIO2_2 (0x40e102dc) +#define GPIO3_2 (0x40e102e0) +#define GPIO4_2 (0x40e102e4) +#define GPIO5_2 (0x40e102e8) +#define GPIO6_2 (0x40e102ec) + +#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ +#define GPIO7_2 (0x40e1052c) +#define GPIO8_2 (0x40e10530) +#define GPIO9_2 (0x40e10534) +#define GPIO10_2 (0x40e10538) +#endif +#endif +#ifdef CONFIG_CPU_MONAHANS /* MFPR Bit Definitions, see 4-10, Vol. 1 */ #define PULL_SEL 0x8000 #define PULLUP_EN 0x4000 @@ -1470,62 +1855,8 @@ typedef void (*ExcpHndlr) (void) ; #define AF_SEL_6 0x6 /* Alternate function 6 */ #define AF_SEL_7 0x7 /* Alternate function 7 */ - -#else /* CONFIG_CPU_MONAHANS */ - -#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ #endif /* CONFIG_CPU_MONAHANS */ -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#ifdef CONFIG_PXA27X - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) -#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) -#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) -#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) -#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) -#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) -#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) -#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ - ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - /* GPIO alternate function assignments */ #define GPIO1_RST 1 /* reset */ @@ -1732,63 +2063,63 @@ typedef void (*ExcpHndlr) (void) ; */ #ifdef CONFIG_CPU_MONAHANS -#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */ -#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */ -#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */ -#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */ -#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */ - -#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ -#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ -#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ -#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ -#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ -#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ -#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ -#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ -#define PCMD(x) __REG(0x40F50110 + x*4) -#define PCMD0 __REG(0x40F50110 + 0 * 4) -#define PCMD1 __REG(0x40F50110 + 1 * 4) -#define PCMD2 __REG(0x40F50110 + 2 * 4) -#define PCMD3 __REG(0x40F50110 + 3 * 4) -#define PCMD4 __REG(0x40F50110 + 4 * 4) -#define PCMD5 __REG(0x40F50110 + 5 * 4) -#define PCMD6 __REG(0x40F50110 + 6 * 4) -#define PCMD7 __REG(0x40F50110 + 7 * 4) -#define PCMD8 __REG(0x40F50110 + 8 * 4) -#define PCMD9 __REG(0x40F50110 + 9 * 4) -#define PCMD10 __REG(0x40F50110 + 10 * 4) -#define PCMD11 __REG(0x40F50110 + 11 * 4) -#define PCMD12 __REG(0x40F50110 + 12 * 4) -#define PCMD13 __REG(0x40F50110 + 13 * 4) -#define PCMD14 __REG(0x40F50110 + 14 * 4) -#define PCMD15 __REG(0x40F50110 + 15 * 4) -#define PCMD16 __REG(0x40F50110 + 16 * 4) -#define PCMD17 __REG(0x40F50110 + 17 * 4) -#define PCMD18 __REG(0x40F50110 + 18 * 4) -#define PCMD19 __REG(0x40F50110 + 19 * 4) -#define PCMD20 __REG(0x40F50110 + 20 * 4) -#define PCMD21 __REG(0x40F50110 + 21 * 4) -#define PCMD22 __REG(0x40F50110 + 22 * 4) -#define PCMD23 __REG(0x40F50110 + 23 * 4) -#define PCMD24 __REG(0x40F50110 + 24 * 4) -#define PCMD25 __REG(0x40F50110 + 25 * 4) -#define PCMD26 __REG(0x40F50110 + 26 * 4) -#define PCMD27 __REG(0x40F50110 + 27 * 4) -#define PCMD28 __REG(0x40F50110 + 28 * 4) -#define PCMD29 __REG(0x40F50110 + 29 * 4) -#define PCMD30 __REG(0x40F50110 + 30 * 4) -#define PCMD31 __REG(0x40F50110 + 31 * 4) +#define ASCR (0x40F40000) /* Application Subsystem Power Status/Control Register */ +#define ARSR (0x40F40004) /* Application Subsystem Reset Status Register */ +#define AD3ER (0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ +#define AD3SR (0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ +#define AD2D0ER (0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ +#define AD2D0SR (0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ +#define AD2D1ER (0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ +#define AD2D1SR (0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ +#define AD1D0ER (0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ +#define AD1D0SR (0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ +#define ASDCNT (0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ +#define AD3R (0x40F40030) /* Application Subsystem D3 State Configuration Register */ +#define AD2R (0x40F40034) /* Application Subsystem D2 State Configuration Register */ +#define AD1R (0x40F40038) /* Application Subsystem D1 State Configuration Register */ + +#define PMCR (0x40F50000) /* Power Manager Control Register */ +#define PSR (0x40F50004) /* Power Manager S2 Status Register */ +#define PSPR (0x40F50008) /* Power Manager Scratch Pad Register */ +#define PCFR (0x40F5000C) /* Power Manager General Configuration Register */ +#define PWER (0x40F50010) /* Power Manager Wake-up Enable Register */ +#define PWSR (0x40F50014) /* Power Manager Wake-up Status Register */ +#define PECR (0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR (0x40F50080) /* DC-DC Controller Status Register */ +#define PVCR (0x40F50100) /* Power Manager Voltage Change Control Register */ +#define PCMD(x) (0x40F50110 + x*4) +#define PCMD0 (0x40F50110 + 0 * 4) +#define PCMD1 (0x40F50110 + 1 * 4) +#define PCMD2 (0x40F50110 + 2 * 4) +#define PCMD3 (0x40F50110 + 3 * 4) +#define PCMD4 (0x40F50110 + 4 * 4) +#define PCMD5 (0x40F50110 + 5 * 4) +#define PCMD6 (0x40F50110 + 6 * 4) +#define PCMD7 (0x40F50110 + 7 * 4) +#define PCMD8 (0x40F50110 + 8 * 4) +#define PCMD9 (0x40F50110 + 9 * 4) +#define PCMD10 (0x40F50110 + 10 * 4) +#define PCMD11 (0x40F50110 + 11 * 4) +#define PCMD12 (0x40F50110 + 12 * 4) +#define PCMD13 (0x40F50110 + 13 * 4) +#define PCMD14 (0x40F50110 + 14 * 4) +#define PCMD15 (0x40F50110 + 15 * 4) +#define PCMD16 (0x40F50110 + 16 * 4) +#define PCMD17 (0x40F50110 + 17 * 4) +#define PCMD18 (0x40F50110 + 18 * 4) +#define PCMD19 (0x40F50110 + 19 * 4) +#define PCMD20 (0x40F50110 + 20 * 4) +#define PCMD21 (0x40F50110 + 21 * 4) +#define PCMD22 (0x40F50110 + 22 * 4) +#define PCMD23 (0x40F50110 + 23 * 4) +#define PCMD24 (0x40F50110 + 24 * 4) +#define PCMD25 (0x40F50110 + 25 * 4) +#define PCMD26 (0x40F50110 + 26 * 4) +#define PCMD27 (0x40F50110 + 27 * 4) +#define PCMD28 (0x40F50110 + 28 * 4) +#define PCMD29 (0x40F50110 + 29 * 4) +#define PCMD30 (0x40F50110 + 30 * 4) +#define PCMD31 (0x40F50110 + 31 * 4) #define PCMD_MBC (1<<12) #define PCMD_DCE (1<<11) @@ -1803,59 +2134,59 @@ typedef void (*ExcpHndlr) (void) ; #else /* ifdef CONFIG_CPU_MONAHANS */ -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ -#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ -#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ -#define PCMD(x) __REG(0x40F00080 + x*4) -#define PCMD0 __REG(0x40F00080 + 0 * 4) -#define PCMD1 __REG(0x40F00080 + 1 * 4) -#define PCMD2 __REG(0x40F00080 + 2 * 4) -#define PCMD3 __REG(0x40F00080 + 3 * 4) -#define PCMD4 __REG(0x40F00080 + 4 * 4) -#define PCMD5 __REG(0x40F00080 + 5 * 4) -#define PCMD6 __REG(0x40F00080 + 6 * 4) -#define PCMD7 __REG(0x40F00080 + 7 * 4) -#define PCMD8 __REG(0x40F00080 + 8 * 4) -#define PCMD9 __REG(0x40F00080 + 9 * 4) -#define PCMD10 __REG(0x40F00080 + 10 * 4) -#define PCMD11 __REG(0x40F00080 + 11 * 4) -#define PCMD12 __REG(0x40F00080 + 12 * 4) -#define PCMD13 __REG(0x40F00080 + 13 * 4) -#define PCMD14 __REG(0x40F00080 + 14 * 4) -#define PCMD15 __REG(0x40F00080 + 15 * 4) -#define PCMD16 __REG(0x40F00080 + 16 * 4) -#define PCMD17 __REG(0x40F00080 + 17 * 4) -#define PCMD18 __REG(0x40F00080 + 18 * 4) -#define PCMD19 __REG(0x40F00080 + 19 * 4) -#define PCMD20 __REG(0x40F00080 + 20 * 4) -#define PCMD21 __REG(0x40F00080 + 21 * 4) -#define PCMD22 __REG(0x40F00080 + 22 * 4) -#define PCMD23 __REG(0x40F00080 + 23 * 4) -#define PCMD24 __REG(0x40F00080 + 24 * 4) -#define PCMD25 __REG(0x40F00080 + 25 * 4) -#define PCMD26 __REG(0x40F00080 + 26 * 4) -#define PCMD27 __REG(0x40F00080 + 27 * 4) -#define PCMD28 __REG(0x40F00080 + 28 * 4) -#define PCMD29 __REG(0x40F00080 + 29 * 4) -#define PCMD30 __REG(0x40F00080 + 30 * 4) -#define PCMD31 __REG(0x40F00080 + 31 * 4) +#define PMCR (0x40F00000) /* Power Manager Control Register */ +#define PSSR (0x40F00004) /* Power Manager Sleep Status Register */ +#define PSPR (0x40F00008) /* Power Manager Scratch Pad Register */ +#define PWER (0x40F0000C) /* Power Manager Wake-up Enable Register */ +#define PRER (0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER (0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR (0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR (0x40F0001C) /* Power Manager General Configuration Register */ +#define PGSR0 (0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 (0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 (0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 (0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR (0x40F00030) /* Reset Controller Status Register */ + +#define PSLR (0x40F00034) /* Power Manager Sleep Config Register */ +#define PSTR (0x40F00038) /* Power Manager Standby Config Register */ +#define PSNR (0x40F0003C) /* Power Manager Sense Config Register */ +#define PVCR (0x40F00040) /* Power Manager VoltageControl Register */ +#define PKWR (0x40F00050) /* Power Manager KB Wake-up Enable Reg */ +#define PKSR (0x40F00054) /* Power Manager KB Level-Detect Register */ +#define PCMD(x) (0x40F00080 + x*4) +#define PCMD0 (0x40F00080 + 0 * 4) +#define PCMD1 (0x40F00080 + 1 * 4) +#define PCMD2 (0x40F00080 + 2 * 4) +#define PCMD3 (0x40F00080 + 3 * 4) +#define PCMD4 (0x40F00080 + 4 * 4) +#define PCMD5 (0x40F00080 + 5 * 4) +#define PCMD6 (0x40F00080 + 6 * 4) +#define PCMD7 (0x40F00080 + 7 * 4) +#define PCMD8 (0x40F00080 + 8 * 4) +#define PCMD9 (0x40F00080 + 9 * 4) +#define PCMD10 (0x40F00080 + 10 * 4) +#define PCMD11 (0x40F00080 + 11 * 4) +#define PCMD12 (0x40F00080 + 12 * 4) +#define PCMD13 (0x40F00080 + 13 * 4) +#define PCMD14 (0x40F00080 + 14 * 4) +#define PCMD15 (0x40F00080 + 15 * 4) +#define PCMD16 (0x40F00080 + 16 * 4) +#define PCMD17 (0x40F00080 + 17 * 4) +#define PCMD18 (0x40F00080 + 18 * 4) +#define PCMD19 (0x40F00080 + 19 * 4) +#define PCMD20 (0x40F00080 + 20 * 4) +#define PCMD21 (0x40F00080 + 21 * 4) +#define PCMD22 (0x40F00080 + 22 * 4) +#define PCMD23 (0x40F00080 + 23 * 4) +#define PCMD24 (0x40F00080 + 24 * 4) +#define PCMD25 (0x40F00080 + 25 * 4) +#define PCMD26 (0x40F00080 + 26 * 4) +#define PCMD27 (0x40F00080 + 27 * 4) +#define PCMD28 (0x40F00080 + 28 * 4) +#define PCMD29 (0x40F00080 + 29 * 4) +#define PCMD30 (0x40F00080 + 30 * 4) +#define PCMD31 (0x40F00080 + 31 * 4) #define PCMD_MBC (1<<12) #define PCMD_DCE (1<<11) @@ -1891,183 +2222,58 @@ typedef void (*ExcpHndlr) (void) ; /* * SSP Serial Port Registers */ -#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ -#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ -#define SSSR __REG(0x41000008) /* SSP Status Register */ -#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ -#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ +#define SSCR0 (0x41000000) /* SSP Control Register 0 */ +#define SSCR1 (0x41000004) /* SSP Control Register 1 */ +#define SSSR (0x41000008) /* SSP Status Register */ +#define SSITR (0x4100000C) /* SSP Interrupt Test Register */ +#define SSDR (0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ /* * MultiMediaCard (MMC) controller */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ -#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ -#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ -#define CKENB __REG(0x41340010) /* B Clock Enable Register */ -#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ +#define MMC_STRPCL (0x41100000) /* Control to start and stop MMC clock */ +#define MMC_STAT (0x41100004) /* MMC Status Register (read only) */ +#define MMC_CLKRT (0x41100008) /* MMC clock rate */ +#define MMC_SPI (0x4110000c) /* SPI mode control bits */ +#define MMC_CMDAT (0x41100010) /* Command/response/data sequence control */ +#define MMC_RESTO (0x41100014) /* Expected response time out */ +#define MMC_RDTO (0x41100018) /* Expected data read time out */ +#define MMC_BLKLEN (0x4110001c) /* Block length of data transaction */ +#define MMC_NOB (0x41100020) /* Number of blocks, for block mode */ +#define MMC_PRTBUF (0x41100024) /* Partial MMC_TXFIFO FIFO written */ +#define MMC_I_MASK (0x41100028) /* Interrupt Mask */ +#define MMC_I_REG (0x4110002c) /* Interrupt Register (read only) */ +#define MMC_CMD (0x41100030) /* Index of current command */ +#define MMC_ARGH (0x41100034) /* MSW part of the current command argument */ +#define MMC_ARGL (0x41100038) /* LSW part of the current command argument */ +#define MMC_RES (0x4110003c) /* Response FIFO (read only) */ +#define MMC_RXFIFO (0x41100040) /* Receive FIFO (read only) */ +#define MMC_TXFIFO (0x41100044) /* Transmit FIFO (write only) */ -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif - -#endif /* CONFIG_CPU_MONAHANS */ /* * LCD */ -#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ -#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ -#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ -#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ -#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */ -#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */ -#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ -#define TMEDCR __REG(0x44000044) /* TMED Control Register */ - -#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ -#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ +#define LCCR0 (0x44000000) /* LCD Controller Control Register 0 */ +#define LCCR1 (0x44000004) /* LCD Controller Control Register 1 */ +#define LCCR2 (0x44000008) /* LCD Controller Control Register 2 */ +#define LCCR3 (0x4400000C) /* LCD Controller Control Register 3 */ +#define DFBR0 (0x44000020) /* DMA Channel 0 Frame Branch Register */ +#define DFBR1 (0x44000024) /* DMA Channel 1 Frame Branch Register */ +#define LCSR0 (0x44000038) /* LCD Controller Status Register */ +#define LCSR1 (0x44000034) /* LCD Controller Status Register */ +#define LIIDR (0x4400003C) /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR (0x44000040) /* TMED RGB Seed Register */ +#define TMEDCR (0x44000044) /* TMED Control Register */ + +#define FDADR0 (0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ +#define FSADR0 (0x44000204) /* DMA Channel 0 Frame Source Address Register */ +#define FIDR0 (0x44000208) /* DMA Channel 0 Frame ID Register */ +#define LDCMD0 (0x4400020C) /* DMA Channel 0 Command Register */ +#define FDADR1 (0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ +#define FSADR1 (0x44000214) /* DMA Channel 1 Frame Source Address Register */ +#define FIDR1 (0x44000218) /* DMA Channel 1 Frame ID Register */ +#define LDCMD1 (0x4400021C) /* DMA Channel 1 Command Register */ #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ @@ -2231,46 +2437,49 @@ typedef void (*ExcpHndlr) (void) ; */ #ifdef CONFIG_CPU_MONAHANS + +/* PXA3xx */ + /* Static Memory Controller Registers */ -#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */ -#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */ -#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */ -#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */ -#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */ -#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */ -#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */ -#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */ -#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ +#define MSC0 (0x4A000008) /* Static Memory Control Register 0 */ +#define MSC1 (0x4A00000C) /* Static Memory Control Register 1 */ +#define MECR (0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXCNFG (0x4A00001C) /* Synchronous Static Memory Control Register */ +#define MCMEM0 (0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCATT0 (0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCIO0 (0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MEMCLKCFG (0x4A000068) /* SCLK speed configuration */ +#define CSADRCFG0 (0x4A000080) /* Address Configuration for chip select 0 */ +#define CSADRCFG1 (0x4A000084) /* Address Configuration for chip select 1 */ +#define CSADRCFG2 (0x4A000088) /* Address Configuration for chip select 2 */ +#define CSADRCFG3 (0x4A00008C) /* Address Configuration for chip select 3 */ +#define CSADRCFG_P (0x4A000090) /* Address Configuration for pcmcia card interface */ +#define CSMSADRCFG (0x4A0000A0) /* Master Address Configuration Register */ +#define CLK_RET_DEL (0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ +#define ADV_RET_DEL (0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ /* Dynamic Memory Controller Registers */ -#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */ -#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */ -#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */ -#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI __REG_2(0x48100090) /* EMPI Control Register */ -#define RCOMP __REG_2(0x48100100) -#define PAD_MA __REG_2(0x48100110) -#define PAD_MDMSB __REG_2(0x48100114) -#define PAD_MDLSB __REG_2(0x48100118) -#define PAD_DMEM __REG_2(0x4810011c) -#define PAD_SDCLK __REG_2(0x48100120) -#define PAD_SDCS __REG_2(0x48100124) -#define PAD_SMEM __REG_2(0x48100128) -#define PAD_SCLK __REG_2(0x4810012C) -#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */ +#define MDCNFG (0x48100000) /* SDRAM Configuration Register 0 */ +#define MDREFR (0x48100004) /* SDRAM Refresh Control Register */ +#define FLYCNFG (0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ +#define MDMRS (0x48100040) /* MRS value to be written to SDRAM */ +#define DDR_SCAL (0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_HCAL (0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_WCAL (0x48100068) /* DDR Write Strobe Calibration Register */ +#define DMCIER (0x48100070) /* Dynamic MC Interrupt Enable Register. */ +#define DMCISR (0x48100078) /* Dynamic MC Interrupt Status Register. */ +#define DDR_DLS (0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ +#define EMPI (0x48100090) /* EMPI Control Register */ +#define RCOMP (0x48100100) +#define PAD_MA (0x48100110) +#define PAD_MDMSB (0x48100114) +#define PAD_MDLSB (0x48100118) +#define PAD_DMEM (0x4810011c) +#define PAD_SDCLK (0x48100120) +#define PAD_SDCS (0x48100124) +#define PAD_SMEM (0x48100128) +#define PAD_SCLK (0x4810012C) +#define TAI (0x48100F00) /* TAI Tavor Address Isolation Register */ /* Some frequently used bits */ #define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ @@ -2298,19 +2507,19 @@ typedef void (*ExcpHndlr) (void) ; /* Data Flash Controller Registers */ -#define NDCR __REG(0x43100000) /* Data Flash Control register */ -#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR __REG(0x43100014) /* Data Controller Status Register */ -#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */ -#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */ -#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */ -#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */ -#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */ -#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */ -#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */ +#define NDCR (0x43100000) /* Data Flash Control register */ +#define NDTR0CS0 (0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ +/* #define NDTR0CS1 (0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ +#define NDTR1CS0 (0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ +/* #define NDTR1CS1 (0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ +#define NDSR (0x43100014) /* Data Controller Status Register */ +#define NDPCR (0x43100018) /* Data Controller Page Count Register */ +#define NDBDR0 (0x4310001C) /* Data Controller Bad Block Register 0 */ +#define NDBDR1 (0x43100020) /* Data Controller Bad Block Register 1 */ +#define NDDB (0x43100040) /* Data Controller Data Buffer */ +#define NDCB0 (0x43100048) /* Data Controller Command Buffer0 */ +#define NDCB1 (0x4310004C) /* Data Controller Command Buffer1 */ +#define NDCB2 (0x43100050) /* Data Controller Command Buffer2 */ #define NDCR_SPARE_EN (0x1<<31) #define NDCR_ECC_EN (0x1<<30) @@ -2386,7 +2595,9 @@ typedef void (*ExcpHndlr) (void) ; #else /* CONFIG_CPU_MONAHANS */ -#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ +/* PXA2xx */ + +#define MEMC_BASE (0x48000000) /* Base of Memory Controller */ #define MDCNFG_OFFSET 0x0 #define MDREFR_OFFSET 0x4 #define MSC0_OFFSET 0x8 @@ -2405,29 +2616,29 @@ typedef void (*ExcpHndlr) (void) ; #define MCIO1_OFFSET 0x3C #define MDMRS_OFFSET 0x40 -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDCNFG (0x48000000) /* SDRAM Configuration Register 0 */ #define MDCNFG_DE0 0x00000001 #define MDCNFG_DE1 0x00000002 #define MDCNFG_DE2 0x00010000 #define MDCNFG_DE3 0x00020000 #define MDCNFG_DWID0 0x00000004 -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MDREFR (0x48000004) /* SDRAM Refresh Control Register */ +#define MSC0 (0x48000008) /* Static Memory Control Register 0 */ +#define MSC1 (0x4800000C) /* Static Memory Control Register 1 */ +#define MSC2 (0x48000010) /* Static Memory Control Register 2 */ +#define MECR (0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR (0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG (0x4800001C) /* Synchronous Static Memory Control Register */ +#define SXMRS (0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 (0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 (0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 (0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 (0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 (0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 (0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS (0x48000040) /* MRS value to be written to SDRAM */ +#define BOOT_DEF (0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ #define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ #define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ @@ -2448,7 +2659,7 @@ typedef void (*ExcpHndlr) (void) ; #if defined(CONFIG_PXA27X) -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ +#define ARB_CNTRL (0x48000048) /* Arbiter Control Register */ #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ @@ -2460,80 +2671,41 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_CPU_MONAHANS */ - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -/* General Purpose I/O */ - -#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -/* Core Clock */ - -#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -/* Memory controller */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */ +#endif /* CONFIG_PXA27X */ /* LCD registers */ -#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ -#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */ -#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */ -#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */ -#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */ -#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */ -#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */ -#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */ - -#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */ -#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */ -#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */ -#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */ -#define CCR __REG(0x44000090) /* Cursor Control Register */ - -#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */ -#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */ +#define LCCR4 (0x44000010) /* LCD Controller Control Register 4 */ +#define LCCR5 (0x44000014) /* LCD Controller Control Register 5 */ +#define FBR0 (0x44000020) /* DMA Channel 0 Frame Branch Register */ +#define FBR1 (0x44000024) /* DMA Channel 1 Frame Branch Register */ +#define FBR2 (0x44000028) /* DMA Channel 2 Frame Branch Register */ +#define FBR3 (0x4400002C) /* DMA Channel 3 Frame Branch Register */ +#define FBR4 (0x44000030) /* DMA Channel 4 Frame Branch Register */ +#define FDADR2 (0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ +#define FSADR2 (0x44000224) /* DMA Channel 2 Frame Source Address Register */ +#define FIDR2 (0x44000228) /* DMA Channel 2 Frame ID Register */ +#define LDCMD2 (0x4400022C) /* DMA Channel 2 Command Register */ +#define FDADR3 (0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ +#define FSADR3 (0x44000234) /* DMA Channel 3 Frame Source Address Register */ +#define FIDR3 (0x44000238) /* DMA Channel 3 Frame ID Register */ +#define LDCMD3 (0x4400023C) /* DMA Channel 3 Command Register */ +#define FDADR4 (0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ +#define FSADR4 (0x44000244) /* DMA Channel 4 Frame Source Address Register */ +#define FIDR4 (0x44000248) /* DMA Channel 4 Frame ID Register */ +#define LDCMD4 (0x4400024C) /* DMA Channel 4 Command Register */ +#define FDADR5 (0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ +#define FSADR5 (0x44000254) /* DMA Channel 5 Frame Source Address Register */ +#define FIDR5 (0x44000258) /* DMA Channel 5 Frame ID Register */ +#define LDCMD5 (0x4400025C) /* DMA Channel 5 Command Register */ + +#define OVL1C1 (0x44000050) /* Overlay 1 Control Register 1 */ +#define OVL1C2 (0x44000060) /* Overlay 1 Control Register 2 */ +#define OVL2C1 (0x44000070) /* Overlay 2 Control Register 1 */ +#define OVL2C2 (0x44000080) /* Overlay 2 Control Register 2 */ +#define CCR (0x44000090) /* Cursor Control Register */ + +#define FBR5 (0x44000110) /* DMA Channel 5 Frame Branch Register */ +#define FBR6 (0x44000114) /* DMA Channel 6 Frame Branch Register */ #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ @@ -2572,16 +2744,16 @@ typedef void (*ExcpHndlr) (void) ; /* Keypad controller */ -#define KPC __REG(0x41500000) /* Keypad Interface Control register */ -#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ -#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */ -#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */ -#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ +#define KPC (0x41500000) /* Keypad Interface Control register */ +#define KPDK (0x41500008) /* Keypad Interface Direct Key register */ +#define KPREC (0x41500010) /* Keypad Intefcace Rotary Encoder register */ +#define KPMK (0x41500018) /* Keypad Intefcace Matrix Key register */ +#define KPAS (0x41500020) /* Keypad Interface Automatic Scan register */ +#define KPASMKP0 (0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ +#define KPASMKP1 (0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ +#define KPASMKP2 (0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ +#define KPASMKP3 (0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ +#define KPKDI (0x41500048) /* Keypad Interface Key Debounce Interval register */ #define KPC_AS (0x1 << 30) /* Automatic Scan bit */ #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ @@ -2623,15 +2795,15 @@ typedef void (*ExcpHndlr) (void) ; #define KPASMKPx_SO (0x1 << 31) #define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR __REG(0x40F00034) -#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ -#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ +#define PSLR (0x40F00034) +#define PSTR (0x40F00038) /* Power Manager Standby Configuration Reg */ +#define PSNR (0x40F0003C) /* Power Manager Sense Configuration Reg */ +#define PVCR (0x40F00040) /* Power Manager Voltage Change Control Reg */ +#define PKWR (0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ +#define PKSR (0x40F00054) /* Power Manager KB Level-Detect Status Reg */ +#define OSMR4 (0x40A00080) /* */ +#define OSCR4 (0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 (0x40A000C0) /* */ #endif /* CONFIG_PXA27X */ diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index 84ec38e..ad83f66 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/arch/hardware.h> #include <netdev.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -65,28 +66,29 @@ int dram_init (void) #ifdef CONFIG_CMD_USB int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); while (UHCHR & UHCHR_FSBIR); - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(0x200); - UHCRHDA |= 0x100; + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); /* enable port 2 */ - UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); return 0; } @@ -98,14 +100,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c index 21eb655..c4a93f9 100644 --- a/board/cradle/cradle.c +++ b/board/cradle/cradle.c @@ -28,6 +28,7 @@ #include <asm/arch/pxa-regs.h> #include <common.h> #include <netdev.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -92,8 +93,8 @@ set_led (int led, int color) int shift = led * 2; unsigned long mask = 0x3 << shift; - CRADLE_LED_CLR_REG = mask; /* clear bits */ - CRADLE_LED_SET_REG = (color << shift); /* set bits */ + writel(mask, GPCR2); /* clear bits */ + writel((color << shift), GPSR2); /* set bits */ udelay (5000); } diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S index 6b5cfb9..39964b6 100644 --- a/board/cradle/lowlevel_init.S +++ b/board/cradle/lowlevel_init.S @@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE .endm .macro SET_LED val - ldr r6, =CRADLE_LED_CLR_REG + ldr r6, =GPCR2 ldr r7, =0 str r7, [r6] - ldr r6, =CRADLE_LED_SET_REG + ldr r6, =GPSR2 ldr r7, =\val str r7, [r6] .endm diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c index 0a6c13d..6eed9ad 100644 --- a/board/csb226/csb226.c +++ b/board/csb226/csb226.c @@ -26,6 +26,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -108,23 +109,23 @@ void csb226_set_led(int led, int state) switch(led) { case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; + writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; + writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0); } break; case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; + writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; + writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0); } break; case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; + writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; + writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0); } break; } diff --git a/board/delta/delta.c b/board/delta/delta.c index 68c39d2..df23076 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -28,6 +28,7 @@ #include <malloc.h> #include <command.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd"; static void get_pressed_keys(uchar *s) { unsigned long val; - val = GPLR3; + val = readl(GPLR3); if(val & (1<<31)) *s++ = KEYBD_KP_DKIN0; @@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s) static void keys_init() { - CKENB |= CKENB_7_GPIO; + writel(readl(CKENB) | CKENB_7_GPIO, CKENB); udelay(100); /* Configure GPIOs */ - GPIO127 = 0xa840; /* KP_DKIN0 */ - GPIO114 = 0xa840; /* KP_DKIN1 */ - GPIO125 = 0xa840; /* KP_DKIN2 */ - GPIO118 = 0xa840; /* KP_DKIN5 */ + writel(0xa840, GPIO127); /* KP_DKIN0 */ + writel(0xa840, GPIO114); /* KP_DKIN1 */ + writel(0xa840, GPIO125); /* KP_DKIN2 */ + writel(0xa840, GPIO118); /* KP_DKIN5 */ /* Configure GPIOs as inputs */ - GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22); - GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22); + writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3); + writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3); udelay(100); } @@ -283,11 +284,11 @@ int dram_init (void) void i2c_init_board() { - CKENB |= (CKENB_4_I2C); + writel(readl(CKENB) | (CKENB_4_I2C), CKENB); /* setup I2C GPIO's */ - GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ - GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ + writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */ + writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */ } /* initialize the DA9030 Power Controller */ @@ -295,20 +296,20 @@ static void init_DA9030() { uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; - CKENB |= CKENB_7_GPIO; + writel(readl(CKENB) | CKENB_7_GPIO, CKENB); udelay(100); /* Rising Edge on EXTON to reset DA9030 */ - GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */ - GPDR0 |= (1<<17); /* GPIO17 is output */ - GSDR0 = (1<<17); - GPCR0 = (1<<17); /* drive GPIO17 low */ - GPSR0 = (1<<17); /* drive GPIO17 high */ + writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */ + writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */ + writel((1<<17), GSDR0); + writel((1<<17), GPCR0); /* drive GPIO17 low */ + writel((1<<17), GPSR0); /* drive GPIO17 high */ #if CONFIG_SYS_DA9030_EXTON_DELAY udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */ #endif - GPCR0 = (1<<17); /* drive GPIO17 low */ + writel((1<<17), GPCR0); /* drive GPIO17 low */ /* reset the watchdog and go active (0xec) */ val = (SYS_CONTROL_A_HWRES_ENABLE | diff --git a/board/delta/nand.c b/board/delta/nand.c index 85a6ba2..57553e2 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -26,6 +26,7 @@ #include <nand.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> #ifdef CONFIG_SYS_DFC_DEBUG1 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) @@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { long_buf = (unsigned long*) &buf[i]; - NDDB = *long_buf; + writel(*long_buf, NDDB); } } if(rest) { @@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { long_buf = (unsigned long*) &buf[i]; - *long_buf = NDDB; + *long_buf = readl(NDDB); } } @@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd) unsigned long dummy; if(bytes_read < 0) { - read_buf = NDDB; - dummy = NDDB; + read_buf = readl(NDDB); + dummy = readl(NDDB); bytes_read = 0; } byte = (unsigned char) (read_buf>>(8 * bytes_read++)); @@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) /* calculate delta between OSCR values start and now */ static unsigned long get_delta(unsigned long start) { - unsigned long cur = OSCR; + unsigned long cur = readl(OSCR); if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); @@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start) /* delay function, this doesn't belong here */ static void wait_us(unsigned long us) { - unsigned long start = OSCR; + unsigned long start = readl(OSCR); us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000); while (get_delta(start) < us) { @@ -202,14 +203,14 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { - NDCR &= ~NDCR_ND_RUN; + writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR); wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ static unsigned long dfc_wait_event(unsigned long event) { - unsigned long ndsr, timeout, start = OSCR; + unsigned long ndsr, timeout, start = readl(OSCR); if(!event) return 0xff000000; @@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event) * OSCR_CLK_FREQ, 1000); while(1) { - ndsr = NDSR; + ndsr = readl(NDSR); if(ndsr & event) { - NDSR |= event; + writel(readl(NDSR) | event, NDSR); break; } if(get_delta(start) > timeout) { @@ -243,11 +244,11 @@ static void dfc_new_cmd(void) while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ - NDSR = 0xFFF; + writel(0xfff, NDSR); /* set NDCR[NDRUN] */ - if(!(NDCR & NDCR_ND_RUN)) - NDCR |= NDCR_ND_RUN; + if(!(readl(NDCR) & NDCR_ND_RUN)) + writel(readl(NDCR) | NDCR_ND_RUN, NDCR); status = dfc_wait_event(NDSR_WRCMDREQ); @@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, } write_cmd: - NDCB0 = ndcb0; - NDCB0 = ndcb1; - NDCB0 = ndcb2; + writel(ndcb0, NDCB0); + writel(ndcb1, NDCB0); + writel(ndcb2, NDCB0); /* wait_event: */ dfc_wait_event(event); @@ -372,36 +373,36 @@ static void dfc_gpio_init(void) DFC_DEBUG2("Setting up DFC GPIO's.\n"); /* no idea what is done here, see zylonite.c */ - GPIO4 = 0x1; - - DF_ALE_WE1 = 0x00000001; - DF_ALE_WE2 = 0x00000001; - DF_nCS0 = 0x00000001; - DF_nCS1 = 0x00000001; - DF_nWE = 0x00000001; - DF_nRE = 0x00000001; - DF_IO0 = 0x00000001; - DF_IO8 = 0x00000001; - DF_IO1 = 0x00000001; - DF_IO9 = 0x00000001; - DF_IO2 = 0x00000001; - DF_IO10 = 0x00000001; - DF_IO3 = 0x00000001; - DF_IO11 = 0x00000001; - DF_IO4 = 0x00000001; - DF_IO12 = 0x00000001; - DF_IO5 = 0x00000001; - DF_IO13 = 0x00000001; - DF_IO6 = 0x00000001; - DF_IO14 = 0x00000001; - DF_IO7 = 0x00000001; - DF_IO15 = 0x00000001; - - DF_nWE = 0x1901; - DF_nRE = 0x1901; - DF_CLE_NOE = 0x1900; - DF_ALE_WE1 = 0x1901; - DF_INT_RnB = 0x1900; + writel(0x1, GPIO4); + + writel(0x00000001, DF_ALE_nWE1); + writel(0x00000001, DF_ALE_nWE2); + writel(0x00000001, DF_nCS0); + writel(0x00000001, DF_nCS1); + writel(0x00000001, DF_nWE); + writel(0x00000001, DF_nRE); + writel(0x00000001, DF_IO0); + writel(0x00000001, DF_IO8); + writel(0x00000001, DF_IO1); + writel(0x00000001, DF_IO9); + writel(0x00000001, DF_IO2); + writel(0x00000001, DF_IO10); + writel(0x00000001, DF_IO3); + writel(0x00000001, DF_IO11); + writel(0x00000001, DF_IO4); + writel(0x00000001, DF_IO12); + writel(0x00000001, DF_IO5); + writel(0x00000001, DF_IO13); + writel(0x00000001, DF_IO6); + writel(0x00000001, DF_IO14); + writel(0x00000001, DF_IO7); + writel(0x00000001, DF_IO15); + + writel(0x1901, DF_nWE); + writel(0x1901, DF_nRE); + writel(0x1900, DF_CLE_nOE); + writel(0x1901, DF_ALE_nWE1); + writel(0x1900, DF_INT_RnB); } /* @@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand) dfc_gpio_init(); /* turn on the NAND Controller Clock (104 MHz @ D0) */ - CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA); #undef CONFIG_SYS_TIMING_TIGHT #ifndef CONFIG_SYS_TIMING_TIGHT @@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand) tRP_high = 0; } - NDTR0CS0 = (tCH << 19) | + writel((tCH << 19) | (tCS << 16) | (tWH << 11) | (tWP << 8) | (tRP_high << 6) | (tRH << 3) | - (tRP << 0); + (tRP << 0), + NDTR0CS0); - NDTR1CS0 = (tR << 16) | + writel((tR << 16) | (tWHR << 4) | - (tAR << 0); + (tAR << 0), + NDTR1CS0); /* If it doesn't work (unlikely) think about: * - ecc enable @@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand) */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - NDCR = (NDCR_SPARE_EN | /* use the spare area */ + writel(NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ (2 << 16) | /* read id count = 7 ???? mk@tbd */ @@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand) NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ - NDCR_WRCMDREQM); /* write command request ir masked */ + NDCR_WRCMDREQM, /* write command request ir masked */ + NDCR); /* wait 10 us due to cmd buffer clear reset */ diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index 3412f10..2c51125 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <asm/arch/pxa-regs.h> #include <asm/mach-types.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -48,20 +49,21 @@ int i2c_init_board(void) /* disable I2C controller first, otherwhise it thinks we want to */ /* talk to the slave port... */ - icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); + icr = readl(ICR); + writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR); /* set gpio pin low _before_ we change direction to output */ - GPCR(70) = GPIO_bit(70); + writel(GPIO_bit(70), GPCR(70)); /* now toggle between output=low and high-impedance */ for (i = 0; i < 20; i++) { - GPDR(70) |= GPIO_bit(70); /* output */ + writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */ udelay(10); - GPDR(70) &= ~GPIO_bit(70); /* input */ + writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */ udelay(10); } - ICR = icr; + writel(icr, ICR); return 0; } @@ -76,7 +78,7 @@ int misc_init_r(void) char *str; /* determine if the software update key is pressed during startup */ - if (GPLR0 & 0x00000800) { + if (readl(GPLR0) & 0x00000800) { printf("using bootcmd_normal (sw-update button not pressed)\n"); str = getenv("bootcmd_normal"); } else { diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index a54a95d..7e4e7df 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -33,6 +33,7 @@ #include <common.h> #include <netdev.h> #include <command.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,14 +57,14 @@ int board_init (void) /* set PWM for LCD */ /* a value that works is 60Hz, 77% duty cycle */ - CKEN |= CKEN0_PWM0; - PWM_CTRL0 = 0x3f; - PWM_PERVAL0 = 0x3ff; - PWM_PWDUTY0 = 792; + writel(readl(CKEN) | CKEN0_PWM0, CKEN); + writel(0x3f, PWM_CTRL0); + writel(0x3ff, PWM_PERVAL0); + writel(792, PWM_PWDUTY0); /* clear reset to AC97 codec */ - CKEN |= CKEN2_AC97; - GCR = GCR_COLD_RST; + writel(readl(CKEN) | CKEN2_AC97, CKEN); + writel(GCR_COLD_RST, GCR); /* enable LCD backlight */ /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */ @@ -102,11 +103,11 @@ int dram_init (void) void delay_c(void) { /* reset OSCR to 0 */ - OSCR = 0; - while(OSCR > 0x10000) + writel(0, OSCR); + while(readl(OSCR) > 0x10000) ; - while(OSCR < 0xd4000) + while(readl(OSCR) < 0xd4000) ; } @@ -114,12 +115,12 @@ void blink_c(void) { int led_bit = (1<<10); - GPDR0 = led_bit; - GPCR0 = led_bit; + writel(led_bit, GPDR0); + writel(led_bit, GPCR0); delay_c(); - GPSR0 = led_bit; + writel(led_bit, GPSR0); delay_c(); - GPCR0 = led_bit; + writel(led_bit, GPCR0); } int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 8c11456..b051e35 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -34,6 +34,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> #include <netdev.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -57,25 +58,26 @@ extern struct serial_device serial_stuart_device; int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (readl(UHCHR) & UHCHR_FSBIR); - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(RH_A_NPS); - UHCRHDA |= RH_A_PSM; + writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA); + writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); return 0; } @@ -87,14 +89,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 18e47e2..e203bfd 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -31,6 +31,8 @@ #include <common.h> #include <asm/arch/hardware.h> #include <netdev.h> +#include <serial.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -75,28 +77,29 @@ int dram_init (void) int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (readl(UHCHR) & UHCHR_FSBIR); - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(0x200); - UHCRHDA |= 0x100; + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); /* enable port 2 */ - UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); return 0; } @@ -108,14 +111,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c index fe4b6a9..6e41ea6 100644 --- a/board/wepep250/wepep250.c +++ b/board/wepep250/wepep250.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,13 +34,13 @@ int board_init (void) * Setup GPIO stuff to get serial working */ #if defined( CONFIG_FFUART ) - GPDR1 = 0x80; - GAFR1_L = 0x8010; + writel(0x80, GPDR1); + writel(0x8010, GAFR1_L); #elif defined( CONFIG_BTUART ) - GPDR1 = 0x800; - GAFR1_L = 0x900000; + writel(0x800, GPDR1); + writel(0x900000, GAFR1_L); #endif - PSSR = 0x20; + writel(0x20, PSSR); return 0; } diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 14d1d76..f7edc4c 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -28,6 +28,7 @@ #include <serial.h> #include <asm/arch/hardware.h> #include <spi.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set) { /* GPIO 13 */ if (set) - GPSR0 = (1 << 13); + writel((1 << 13), GPSR0); else - GPCR0 = (1 << 13); + writel((1 << 13), GPCR0); } void zipitz2_spi_scl(int set) { /* GPIO 22 */ if (set) - GPCR0 = (1 << 22); + writel((1 << 22), GPCR0); else - GPSR0 = (1 << 22); + writel((1 << 22), GPSR0); } unsigned char zipitz2_spi_read(void) { /* GPIO 40 */ - return !!(GPLR1 & (1 << 8)); + return !!(readl(GPLR1) & (1 << 8)); } int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { /* GPIO 88 low */ - GPCR2 = (1 << 24); + writel((1 << 24), GPCR2); } void spi_cs_deactivate(struct spi_slave *slave) { /* GPIO 88 high */ - GPSR2 = (1 << 24); + writel((1 << 24), GPSR2); } @@ -176,20 +177,20 @@ void lcd_start(void) unsigned char dummy[3] = { 0, 0, 0 }; /* PWM2 AF */ - GAFR0_L |= 0x00800000; + writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); /* Enable clock to all PWM */ - CKEN |= 0x3; + writel(readl(CKEN) | 0x3, CKEN); /* Configure PWM2 */ - PWM_CTRL2 = 0x4f; - PWM_PWDUTY2 = 0x2ff; - PWM_PERVAL2 = 792; + writel(0x4f, PWM_CTRL2); + writel(0x2ff, PWM_PWDUTY2); + writel(792, PWM_PERVAL2); /* Toggle the reset pin to reset the LCD */ - GPSR0 = (1 << 19); + writel((1 << 19), GPSR0); udelay(100000); - GPCR0 = (1 << 19); + writel((1 << 19), GPCR0); udelay(20000); - GPSR0 = (1 << 19); + writel((1 << 19), GPSR0); udelay(20000); /* Program the LCD init sequence */ @@ -208,6 +209,6 @@ void lcd_start(void) udelay(lcd_data[i].mdelay * 1000); } - GPSR0 = (1 << 11); + writel((1 << 11), GPSR0); } #endif diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index 7cad1ac..c4203df 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -21,6 +21,7 @@ */ #include <common.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NAND) @@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { long_buf = (unsigned long*) &buf[i]; - NDDB = *long_buf; + writel(*long_buf, NDDB); } } if(rest) { @@ -125,7 +126,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { long_buf = (unsigned long*) &buf[i]; - *long_buf = NDDB; + *long_buf = readl(NDDB); } } @@ -171,8 +172,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd) unsigned long dummy; if(bytes_read < 0) { - read_buf = NDDB; - dummy = NDDB; + read_buf = readl(NDDB); + dummy = readl(NDDB); bytes_read = 0; } byte = (unsigned char) (read_buf>>(8 * bytes_read++)); @@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) /* calculate delta between OSCR values start and now */ static unsigned long get_delta(unsigned long start) { - unsigned long cur = OSCR; + unsigned long cur = readl(OSCR); if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); @@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start) /* delay function, this doesn't belong here */ static void wait_us(unsigned long us) { - unsigned long start = OSCR; + unsigned long start = readl(OSCR); us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000); while (get_delta(start) < us) { @@ -207,14 +208,14 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { - NDCR &= ~NDCR_ND_RUN; + writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR); wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ static unsigned long dfc_wait_event(unsigned long event) { - unsigned long ndsr, timeout, start = OSCR; + unsigned long ndsr, timeout, start = readl(OSCR); if(!event) return 0xff000000; @@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event) * OSCR_CLK_FREQ, 1000); while(1) { - ndsr = NDSR; + ndsr = readl(NDSR); if(ndsr & event) { - NDSR |= event; + writel(readl(NDSR) | event, NDSR); break; } if(get_delta(start) > timeout) { @@ -248,11 +249,11 @@ static void dfc_new_cmd(void) while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ - NDSR = 0xFFF; + writel(0xFFF, NDSR); /* set NDCR[NDRUN] */ - if(!(NDCR & NDCR_ND_RUN)) - NDCR |= NDCR_ND_RUN; + if(!(readl(NDCR) & NDCR_ND_RUN)) + writel(readl(NDCR) | NDCR_ND_RUN, NDCR); status = dfc_wait_event(NDSR_WRCMDREQ); @@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, } write_cmd: - NDCB0 = ndcb0; - NDCB0 = ndcb1; - NDCB0 = ndcb2; + writel(ndcb0, NDCB0); + writel(ndcb1, NDCB0); + writel(ndcb2, NDCB0); /* wait_event: */ dfc_wait_event(event); @@ -377,36 +378,36 @@ static void dfc_gpio_init(void) DFC_DEBUG2("Setting up DFC GPIO's.\n"); /* no idea what is done here, see zylonite.c */ - GPIO4 = 0x1; - - DF_ALE_WE1 = 0x00000001; - DF_ALE_WE2 = 0x00000001; - DF_nCS0 = 0x00000001; - DF_nCS1 = 0x00000001; - DF_nWE = 0x00000001; - DF_nRE = 0x00000001; - DF_IO0 = 0x00000001; - DF_IO8 = 0x00000001; - DF_IO1 = 0x00000001; - DF_IO9 = 0x00000001; - DF_IO2 = 0x00000001; - DF_IO10 = 0x00000001; - DF_IO3 = 0x00000001; - DF_IO11 = 0x00000001; - DF_IO4 = 0x00000001; - DF_IO12 = 0x00000001; - DF_IO5 = 0x00000001; - DF_IO13 = 0x00000001; - DF_IO6 = 0x00000001; - DF_IO14 = 0x00000001; - DF_IO7 = 0x00000001; - DF_IO15 = 0x00000001; - - DF_nWE = 0x1901; - DF_nRE = 0x1901; - DF_CLE_NOE = 0x1900; - DF_ALE_WE1 = 0x1901; - DF_INT_RnB = 0x1900; + writel(0x1, GPIO4); + + writel(0x00000001, DF_ALE_nWE1); + writel(0x00000001, DF_ALE_nWE2); + writel(0x00000001, DF_nCS0); + writel(0x00000001, DF_nCS1); + writel(0x00000001, DF_nWE); + writel(0x00000001, DF_nRE); + writel(0x00000001, DF_IO0); + writel(0x00000001, DF_IO8); + writel(0x00000001, DF_IO1); + writel(0x00000001, DF_IO9); + writel(0x00000001, DF_IO2); + writel(0x00000001, DF_IO10); + writel(0x00000001, DF_IO3); + writel(0x00000001, DF_IO11); + writel(0x00000001, DF_IO4); + writel(0x00000001, DF_IO12); + writel(0x00000001, DF_IO5); + writel(0x00000001, DF_IO13); + writel(0x00000001, DF_IO6); + writel(0x00000001, DF_IO14); + writel(0x00000001, DF_IO7); + writel(0x00000001, DF_IO15); + + writel(0x1901, DF_nWE); + writel(0x1901, DF_nRE); + writel(0x1900, DF_CLE_nOE); + writel(0x1901, DF_ALE_nWE1); + writel(0x1900, DF_INT_RnB); } /* @@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand) dfc_gpio_init(); /* turn on the NAND Controller Clock (104 MHz @ D0) */ - CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA); #undef CONFIG_SYS_TIMING_TIGHT #ifndef CONFIG_SYS_TIMING_TIGHT @@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand) tRP_high = 0; } - NDTR0CS0 = (tCH << 19) | + writel((tCH << 19) | (tCS << 16) | (tWH << 11) | (tWP << 8) | (tRP_high << 6) | (tRH << 3) | - (tRP << 0); + (tRP << 0), + NDTR0CS0); - NDTR1CS0 = (tR << 16) | + writel((tR << 16) | (tWHR << 4) | - (tAR << 0); + (tAR << 0), + NDTR1CS0); /* If it doesn't work (unlikely) think about: * - ecc enable @@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand) */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - NDCR = (NDCR_SPARE_EN | /* use the spare area */ + writel(NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ (2 << 16) | /* read id count = 7 ???? mk@tbd */ @@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand) NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ - NDCR_WRCMDREQM); /* write command request ir masked */ + NDCR_WRCMDREQM, /* write command request ir masked */ + NDCR); /* wait 10 us due to cmd buffer clear reset */ diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index 8776903..729f164 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -27,6 +27,7 @@ #include <asm/errno.h> #include <asm/arch/hardware.h> #include <part.h> +#include <asm/io.h> #include "pxa_mmc.h" @@ -59,18 +60,18 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl, cmdat | wide); - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK); while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ; - MMC_CMD = cmd; - MMC_ARGH = argh; - MMC_ARGL = argl; - MMC_CMDAT = cmdat | wide; - MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; - MMC_STRPCL = MMC_STRPCL_START_CLK; + writel(cmd, MMC_CMD); + writel(argh, MMC_ARGH); + writel(argl, MMC_ARGL); + writel(cmdat | wide, MMC_CMDAT); + writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK); + writel(MMC_STRPCL_START_CLK, MMC_STRPCL); while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ; - status = MMC_STAT; + status = readl(MMC_STAT); debug("MMC status 0x%08x\n", status); if (status & MMC_STAT_TIME_OUT_RESPONSE) { return 0; @@ -80,10 +81,10 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) * Did I mention this is Sick. We always need to * discard the upper 8 bits of the first 16-bit word. */ - a = (MMC_RES & 0xffff); + a = (readl(MMC_RES) & 0xffff); for (i = 0; i < 4; i++) { - b = (MMC_RES & 0xffff); - c = (MMC_RES & 0xffff); + b = (readl(MMC_RES) & 0xffff); + c = (readl(MMC_RES) & 0xffff); resp[i] = (a << 24) | (b << 8) | (c >> 8); a = c; debug("MMC resp[%d] = %#08x\n", i, resp[i]); @@ -115,37 +116,37 @@ mmc_block_read(uchar * dst, ulong src, ulong len) /* send read command */ argh = src >> 16; argl = src & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_RDTO = 0xffff; - MMC_NOB = 1; - MMC_BLKLEN = len; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(0xffff, MMC_RDTO); + writel(1, MMC_NOB); + writel(len, MMC_BLKLEN); mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); - MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; + writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK); while (len) { if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) int i; for (i = min(len, 32); i; i--) { - *dst++ = *((volatile uchar *)&MMC_RXFIFO); + *dst++ = readb(MMC_RXFIFO); len--; } #else - *dst++ = MMC_RXFIFO; + *dst++ = readb(MMC_RXFIFO); len--; #endif } - status = MMC_STAT; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; } } - MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; - status = MMC_STAT; + writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) ; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; @@ -176,37 +177,37 @@ mmc_block_write(ulong dst, uchar * src, int len) /* send write command */ argh = dst >> 16; argl = dst & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_NOB = 1; - MMC_BLKLEN = len; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(1, MMC_NOB); + writel(len, MMC_BLKLEN); mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); - MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; + writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK); while (len) { if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { int i, bytes = min(32, len); for (i = 0; i < bytes; i++) { - MMC_TXFIFO = *src++; + writel(*src++, MMC_TXFIFO); } if (bytes < 32) { - MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL; + writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF); } len -= bytes; } - status = MMC_STAT; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; } } - MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; - MMC_I_MASK = ~MMC_I_MASK_PRG_DONE; - while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ; - status = MMC_STAT; + writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) ; + writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE)) ; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; @@ -559,13 +560,13 @@ mmc_legacy_init(int verbose) set_GPIO_mode(GPIO8_MMCCS0_MD); #endif #ifdef CONFIG_CPU_MONAHANS /* pxa3xx */ - CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1; + writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA); #else /* pxa2xx */ - CKEN |= CKEN12_MMC; /* enable MMC unit clock */ + writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */ #endif - MMC_CLKRT = MMC_CLKRT_0_3125MHZ; - MMC_RESTO = MMC_RES_TO_MAX; - MMC_SPI = MMC_SPI_DISABLE; + writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT); + writel(MMC_RES_TO_MAX, MMC_RESTO); + writel(MMC_SPI_DISABLE, MMC_SPI); /* reset */ mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); @@ -624,7 +625,7 @@ mmc_legacy_init(int verbose) mmc_decode_cid(cid_resp); } - MMC_CLKRT = 0; /* 20 MHz */ + writel(0, MMC_CLKRT); /* 20 MHz */ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index b74e439..392dde9 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -32,6 +32,7 @@ #include <watchdog.h> #include <serial.h> #include <asm/arch/pxa-regs.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -73,60 +74,60 @@ void pxa_setbrg_dev (unsigned int uart_index) switch (uart_index) { case FFUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; + writel(readl(CKENA) | CKENA_22_FFUART, CKENA); #else - CKEN |= CKEN6_FFUART; + writel(readl(CKEN) | CKEN6_FFUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + writel(0, FFIER); /* Disable for now */ + writel(0, FFFCR); /* No fifos enabled */ /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR); + writel(quot & 0xff, FFDLL); + writel(quot >> 8, FFDLH); + writel(LCR_WLS0 | LCR_WLS1, FFLCR); - FFIER = IER_UUE; /* Enable FFUART */ + writel(IER_UUE, FFIER); /* Enable FFUART */ break; case BTUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; + writel(readl(CKENA) | CKENA_21_BTUART, CKENA); #else - CKEN |= CKEN7_BTUART; + writel(readl(CKEN) | CKEN7_BTUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - BTIER = 0; - BTFCR = 0; + writel(0, BTIER); + writel(0, BTFCR); /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_DLAB, BTLCR); + writel(quot & 0xff, BTDLL); + writel(quot >> 8, BTDLH); + writel(LCR_WLS0 | LCR_WLS1, BTLCR); - BTIER = IER_UUE; /* Enable BFUART */ + writel(IER_UUE, BTIER); /* Enable BFUART */ break; case STUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; + writel(readl(CKENA) | CKENA_23_STUART, CKENA); #else - CKEN |= CKEN5_STUART; + writel(readl(CKEN) | CKEN5_STUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - STIER = 0; - STFCR = 0; + writel(0, STIER); + writel(0, STFCR); /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_DLAB, STLCR); + writel(quot & 0xff, STDLL); + writel(quot >> 8, STDLH); + writel(LCR_WLS0 | LCR_WLS1, STLCR); - STIER = IER_UUE; /* Enable STUART */ + writel(IER_UUE, STIER); /* Enable STUART */ break; default: @@ -158,19 +159,19 @@ void pxa_putc_dev (unsigned int uart_index,const char c) /* wait for room in the tx FIFO on FFUART */ while ((FFLSR & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; + writel(c, FFTHR); break; case BTUART_INDEX: while ((BTLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; + writel(c, BTTHR); break; case STUART_INDEX: while ((STLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; + writel(c, STTHR); break; } diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 200b61e..998e179 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -339,8 +339,6 @@ #define LED_IRDA1 2 #define LED_IRDA2 4 #define LED_IRDA3 6 -#define CRADLE_LED_SET_REG GPSR2 -#define CRADLE_LED_CLR_REG GPCR2 /* SuperIO defines */ #define CRADLE_SIO_INDEX 0x2e diff --git a/include/configs/delta.h b/include/configs/delta.h index 9c46c5b..d930fb4 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -28,6 +28,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_DELTA 1 /* Delta board */ /* #define CONFIG_LCD 1 */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index d0fc138..c8aa046 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -35,6 +35,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_ZYLONITE 1 /* Zylonite board */ /* #define CONFIG_LCD 1 */ -- 1.7.1

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