September 2010 - U-Boot

[U-Boot] [PATCH] da850evm: fix linux bootparam address
by Ben Gardiner 12 Oct '10

12 Oct '10

This patch fixes the LINUX_BOOT_PARAM_ADDR define to be based off of PHYS_SDRAM_1 instead of CONFIG_SYS_MEMTEST_START. On da830 they are the same thing but on da850 the CONFIG_SYS_MEMSTART define is offset from the PHYS_SDRAM_1 start. Without this patch it is not possible to boot linux on da850 -- bootm hangs at "Uncompressing Linux... done, booting the kernel." Signed-off-by: Ben Gardiner <bengardiner(a)nanometrics.ca> CC: Sudhakar Rajashekhara <sudhakar.raj(a)ti.com> --- I'm not sure if this is a bugfix or not -- there is currently no way to load a uImage from anywhere in the da850evm config on master. But if you did modify the configuration enough to load one then your bootm command would hang at "Uncompressing Linux... done, booting the kernel." I'm submitting it for inclusion into 2010.09 since the definiion of LINUX_BOOT_PARAM_ADDR is wrong for da850. But it's OK to push off to next since you couldn't load a uImage with the default config anyways. --- include/configs/da850evm.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 1b6fe72..21db022 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -139,7 +139,7 @@ /* * Linux Information */ -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTARGS \ -- 1.7.0.4

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[U-Boot] [PATCH][NEXT] arm-reloc: don't undef CONFIG_SYS_ARM_WITHOUT_RELOC
by Ben Gardiner 12 Oct '10

12 Oct '10

There were some #undef's of CONFIG_SYS_ARM_WITHOUT_RELOC added to a few board configs as part of the arm relocation series; but these are not needed now as we do not #undef what is not #defined in the first place. Signed-off-by: Ben Gardiner <bengardiner(a)nanometrics.ca> CC: Heiko Schocher <hs(a)denx.de> --- include/configs/da850evm.h | 1 - include/configs/imx27lite-common.h | 1 - include/configs/omap3_beagle.h | 1 - include/configs/qong.h | 1 - include/configs/tx25.h | 1 - 5 files changed, 0 insertions(+), 5 deletions(-) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index d02b196..e0a3bae 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -138,7 +138,6 @@ #endif /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 812e5f2..4f7d61d 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -236,7 +236,6 @@ "mtdparts=" MTDPARTS_DEFAULT "\0" \ /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 2463be4..ce658d1 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -341,7 +341,6 @@ extern unsigned int boot_flash_type; #endif /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/qong.h b/include/configs/qong.h index 7a68b7b..b9144eb 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -283,7 +283,6 @@ extern int qong_nand_rdy(void *chip); "128k(env2),2432k(kernel),13m(ramdisk),-(user)" /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_END IRAM_SIZE diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c798570..85f166e 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -177,7 +177,6 @@ "upd=run load update\0" \ /* additions for new relocation code, must added to all boards */ -#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) -- 1.7.0.4

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[U-Boot] [PATCH] [NEXT] arm, relocation: fix typo in comment
by Heiko Schocher 12 Oct '10

12 Oct '10

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- include/configs/imx27lite-common.h | 2 +- include/configs/km_arm.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/qong.h | 2 +- include/configs/tx25.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 812e5f2..905a292 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -235,7 +235,7 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 8673e6f..faa0f50 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -180,7 +180,7 @@ int get_scl (void); #undef CONFIG_JFFS2_CMDLINE #endif -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \ CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 2463be4..21078cf 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -340,7 +340,7 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) diff --git a/include/configs/qong.h b/include/configs/qong.h index 7a68b7b..16478e6 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -282,7 +282,7 @@ extern int qong_nand_rdy(void *chip); "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ "128k(env2),2432k(kernel),13m(ramdisk),-(user)" -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c798570..7faa453 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -176,7 +176,7 @@ "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ "upd=run load update\0" \ -/* additions for new relocation code, must added to all boards */ +/* additions for new relocation code, must be added to all boards */ #undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ -- 1.7.2.3

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[U-Boot] [PATCH] cfi_flash: Fix "Unknown FLASH" error message
by Peter Tyser 12 Oct '10

12 Oct '10

From: John Schmoller <jschmoller(a)xes-inc.com> When a CFI flash chip could not be detected an error message similar to the following would be printed on bootup: FLASH: ## Unknown FLASH on Bank 1 - Size = 0x01000000 = 0 MB The printf incorrectly converted the flash size into megabytes. This patch fixes the printing of the flash size in megabytes: FLASH: ## Unknown FLASH on Bank 1 - Size = 0x01000000 = 16 MB Signed-off-by: John Schmoller <jschmoller(a)xes-inc.com> Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- drivers/mtd/cfi_flash.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 02dd27f..798902f 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2033,7 +2033,7 @@ unsigned long flash_init (void) printf ("## Unknown FLASH on Bank %d " "- Size = 0x%08lx = %ld MB\n", i+1, flash_info[i].size, - flash_info[i].size << 20); + flash_info[i].size >> 20); #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ } #ifdef CONFIG_SYS_FLASH_PROTECTION -- 1.7.0.4

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[U-Boot] [PATCH] rarp: Condtionally compile rarp support
by Peter Tyser 12 Oct '10

12 Oct '10

Most people don't use the 'rarpboot' command, so only enable it when CONFIG_CMD_RARP is defined. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- common/cmd_net.c | 2 ++ include/config_cmd_all.h | 1 + net/Makefile | 2 +- net/net.c | 11 +++++++++-- 4 files changed, 13 insertions(+), 3 deletions(-) diff --git a/common/cmd_net.c b/common/cmd_net.c index 3ffb9df..44d17db 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -54,6 +54,7 @@ U_BOOT_CMD( "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#ifdef CONFIG_CMD_RARP int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return netboot_common (RARP, cmdtp, argc, argv); @@ -64,6 +65,7 @@ U_BOOT_CMD( "boot image via network using RARP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#endif #if defined(CONFIG_CMD_DHCP) int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 746bf18..cdc5ff1 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -70,6 +70,7 @@ #define CONFIG_CMD_PORTIO /* Port I/O */ #define CONFIG_CMD_REGINFO /* Register dump */ #define CONFIG_CMD_REISER /* Reiserfs support */ +#define CONFIG_CMD_RARP /* rarpboot support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ diff --git a/net/Makefile b/net/Makefile index 4f819dd..216d1ec 100644 --- a/net/Makefile +++ b/net/Makefile @@ -32,7 +32,7 @@ COBJS-$(CONFIG_CMD_DNS) += dns.o COBJS-$(CONFIG_CMD_NET) += eth.o COBJS-$(CONFIG_CMD_NET) += net.o COBJS-$(CONFIG_CMD_NFS) += nfs.o -COBJS-$(CONFIG_CMD_NET) += rarp.o +COBJS-$(CONFIG_CMD_RARP) += rarp.o COBJS-$(CONFIG_CMD_SNTP) += sntp.o COBJS-$(CONFIG_CMD_NET) += tftp.o diff --git a/net/net.c b/net/net.c index 33fcd90..d5a5429 100644 --- a/net/net.c +++ b/net/net.c @@ -80,7 +80,9 @@ #include <net.h> #include "bootp.h" #include "tftp.h" +#ifdef CONFIG_CMD_RARP #include "rarp.h" +#endif #include "nfs.h" #ifdef CONFIG_STATUS_LED #include <status_led.h> @@ -401,11 +403,13 @@ restart: BootpRequest (); break; +#if defined(CONFIG_CMD_RARP) case RARP: RarpTry = 0; NetOurIP = 0; RarpRequest (); break; +#endif #if defined(CONFIG_CMD_PING) case PING: PingStart(); @@ -1492,6 +1496,7 @@ NetReceive(volatile uchar * inpkt, int len) } break; +#ifdef CONFIG_CMD_RARP case PROT_RARP: debug("Got RARP\n"); arp = (ARP_t *)ip; @@ -1515,7 +1520,7 @@ NetReceive(volatile uchar * inpkt, int len) (*packetHandler)(0,0,0,0); } break; - +#endif case PROT_IP: debug("Got IP\n"); /* Before we start poking the header, make sure it is there */ @@ -1729,10 +1734,12 @@ static int net_check_prereq (proto_t protocol) } /* Fall through */ - case DHCP: +#ifdef CONFIG_CMD_RARP case RARP: +#endif case BOOTP: case CDP: + case DHCP: if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) { #ifdef CONFIG_NET_MULTI extern int eth_get_dev_index (void); -- 1.7.0.4

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[U-Boot] [PATCH] da850evm: basic MII EMAC support
by Ben Gardiner 12 Oct '10

12 Oct '10

The current da850evm support in u-boot/master [1] omits any use of the davinci EMAC. This patch adds basic support for the EMAC using the MII PHY found on the baseboard of the EVM. The MAC address is read from the environment variable 'ethadd'. Note that this is different from the da850evm support in the u-boot omapl1 tree where the MAC address is read from SPI flash [2]. CC: Sandeep Paulraj <s-paulraj(a)ti.com> CC: Sudhakar Rajashekhara <sudhakar.raj(a)ti.com> [1] http://git.denx.de/?p=u-boot.git [2] http://arago-project.org/git/projects/?p=u-boot-omapl1.git --- I am submitting this patch for inclusion in v2010.12, not v2010.09 since it introduces a new feature. --- board/davinci/da8xxevm/da850evm.c | 60 +++++++++++++++++++++++++++++++++++++ include/configs/da850evm.h | 15 +++++++++ 2 files changed, 75 insertions(+), 0 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index eeb456c..30645e5 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -23,7 +23,11 @@ #include <common.h> #include <i2c.h> +#include <net.h> +#include <netdev.h> #include <asm/arch/hardware.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> #include <asm/io.h> #include "../common/misc.h" #include "common.h" @@ -48,6 +52,28 @@ static const struct pinmux_config uart_pins[] = { { pinmux(4), 2, 5 } }; +#ifdef CONFIG_DRIVER_TI_EMAC +const struct pinmux_config emac_pins[] = { + { pinmux(2), 8, 1 }, + { pinmux(2), 8, 2 }, + { pinmux(2), 8, 3 }, + { pinmux(2), 8, 4 }, + { pinmux(2), 8, 5 }, + { pinmux(2), 8, 6 }, + { pinmux(2), 8, 7 }, + { pinmux(3), 8, 0 }, + { pinmux(3), 8, 1 }, + { pinmux(3), 8, 2 }, + { pinmux(3), 8, 3 }, + { pinmux(3), 8, 4 }, + { pinmux(3), 8, 5 }, + { pinmux(3), 8, 6 }, + { pinmux(3), 8, 7 }, + { pinmux(4), 8, 0 }, + { pinmux(4), 8, 1 } +}; +#endif /* CONFIG_DRIVER_TI_EMAC */ + /* I2C pin muxer settings */ static const struct pinmux_config i2c_pins[] = { { pinmux(4), 2, 2 }, @@ -102,6 +128,14 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; +#ifdef CONFIG_DRIVER_TI_EMAC + if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) + return 1; + /* set cfgchip3 to select MII */ + writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8), + &davinci_syscfg_regs->cfgchip3); +#endif /* CONFIG_DRIVER_TI_EMAC */ + /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), @@ -109,3 +143,29 @@ int board_init(void) return 0; } + +#ifdef CONFIG_DRIVER_TI_EMAC + +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + u_int8_t mac_addr[6]; + + /* read the address from env */ + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) + return -1; + + /* provide the resulting addr to the driver */ + davinci_eth_set_mac_addr(mac_addr); + + /* finally, initialise the driver */ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 357715d..432c5e6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -26,6 +26,7 @@ /* * Board */ +#define CONFIG_DRIVER_TI_EMAC /* * SoC Configuration @@ -79,6 +80,20 @@ #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#endif + +/* * U-Boot general configuration */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -- 1.7.0.4

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[U-Boot] [PATCH] mpc5xxx_fec: add call to reset_phy() after PHY initialization
by Ilya Yanok 12 Oct '10

12 Oct '10

Some boards need their board-specific PHY quirks to be called to PHY to work normally. As mpc5xxx_fec driver uses on demand PHY initialization and can even reinit PHY during normal operation we can't count on reset_phy() call from arch/<arch>/lib/board.c (it is most likely called _before_ we init the PHY from the driver) so we need to add call to reset_phy() directly in the driver. Cc: Ben Warren <biggerbadderben(a)gmail.com> Signed-off-by: Ilya Yanok <yanok(a)emcraft.com> --- drivers/net/mpc5xxx_fec.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index c88e596..bc8c922 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -250,6 +250,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) mpc5xxx_fec_init_phy(dev, bis); /* + * Call board-specific PHY fixups (if any) + */ +#ifdef CONFIG_RESET_PHY_R + reset_phy(); +#endif + + /* * Initialize RxBD/TxBD rings */ mpc5xxx_fec_rbd_init(fec); -- 1.6.2.5

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[U-Boot] [PATCH v2] Kirkwood: print_cpuinfo fixed for valid devid revid
by Prafulla Wadaskar 12 Oct '10

12 Oct '10

From: Prafulla Wadaskar <[prafulla(a)marvell.com]> Earlier Device Identification register was used to detect the type for SoC, considering 88F6282 support to be added, It is not possible to detect the same using current algorithm. With this patch, device ID is being read using PCIE devid register, also valid chip revision ID will also be read and displayed Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: v2: Updated as per review comments for V1 debug replaced by printf, sprintf removed (??) kept as it is since we dont know future references for revid arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 34 ++++++++++++++++++++--------- arch/arm/include/asm/arch-kirkwood/cpu.h | 2 + 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 82c978b..b4a4c04 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -54,10 +54,11 @@ unsigned char get_random_hex(void) u8 outbuf[BUFLEN]; /* - * in case of 88F6281/88F6192 A0, + * in case of 88F6281/88F6282/88F6192 A0, * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and - * Does not have names at this moment (no errata available) + * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are + * reserved regs and does not have names at this moment + * (no errata available) */ writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); for (i = 0; i < BUFLEN; i++) { @@ -271,20 +272,31 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *name = "Unknown"; + char *rev; + u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; - switch (readl(KW_REG_DEVICE_ID) & 0x03) { - case 1: - name = "88F6192_A0"; + if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + return -1; + } + + switch (revid) { + case 0: + rev = "Z0"; break; case 2: - name = "88F6281_A0"; + rev = "A0"; + break; + case 3: + rev = "A1"; break; default: - printf("SoC: Unsupported Kirkwood\n"); - return -1; + rev = "??"; + break; } - printf("SoC: Kirkwood %s\n", name); + + printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index b3022a3..d28c51a 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -35,6 +35,8 @@ #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) #define SYSRST_CNT_1SEC_VAL (25*1000000) -- 1.7.2.1

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[U-Boot] [PATCH V3] mvsata_ide: adjust port init sequence
by Albert Aribaud 12 Oct '10

12 Oct '10

mvsata_ide_initialize_port(): adjust init sequence (SStatus should be checked only after all writes to SControl) and return success/failure to ide_preinit(). Also, as some tests showed init durations in the hundreds of us, raise the time-out to 01 ms to be on the safe side. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- PATCH HISTORY V1 Initial patch. V2 Fixed wrong placement of comment. Fixed wrong description (was 01 ms, should have been 10). Added Signed-off-by. V3 Replaced return status values with symbolic names. Made error status values negative. Renamed 'tout' to 'timeleft' for clarity. Replaced ternary '?:' operator with '!' and if. Patch was run through checkscript.pl with 0 errors and warnings. drivers/block/mvsata_ide.c | 42 +++++++++++++++++++++++++++++++++--------- 1 files changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 077b278..3d6993a 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -91,29 +91,48 @@ struct mvsata_port_registers { #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 /* + * Status codes to return to client callers. Currently, callers ignore + * exact value and only care for zero or nonzero, so no need to make this + * public, it is only #define'd for clarity. + * If/when standard negative codes are implemented in U-boot, then these + * #defines should be moved to, or replaced by ones from, the common list + * of status codes. + */ + +#define MVSATA_STATUS_OK 0 +#define MVSATA_STATUS_TIMEOUT -1 + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's * DET back to "no action". */ -static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) +static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) { u32 control; u32 status; - u32 tout = 50; /* wait at most 50 us for SATA reset to complete */ + u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ + /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ control = readl(&port->scontrol); control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; writel(control, &port->scontrol); - while (--tout) { + /* Toggle control DET back to 0 (normal operation) */ + control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; + writel(control, &port->scontrol); + /* wait for status DET to become 3 (device and communication OK) */ + while (--timeleft) { status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; if (status == MVSATA_SSTATUS_DET_DEVCOMM) break; udelay(1); } - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; - writel(control, &port->scontrol); + /* return success or time-out error depending on time left */ + if (!timeleft) + return MVSATA_STATUS_TIMEOUT; + return MVSATA_STATUS_OK; } /* @@ -123,18 +142,23 @@ static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int status; /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); + if (status) + return status; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); + if (status) + return status; #endif - /* return 0 as we always succeed */ - return 0; + /* return success if all ports initializations succeeded */ + return MVSATA_STATUS_OK; } -- 1.7.0.4

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[U-Boot] [PATCH V2 1/2] [NEXT] orion5x: fix relocation-incompatible code
by Albert Aribaud 11 Oct '10

11 Oct '10

Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- SUMMARY Device address window mapping code would not run from FLASH due to cutting access to BOOTCS. Fixed by reordering code. Timer initialization would write globals, thus would not run correctly from FLASH. Fixed by moving the writes to a later phase in RAM. PATCHSET HISTORY V1 Initial submission V2 Removed useless blank line in config.mk Fixed typo in config file Reordered window inits in cpu.c Added newline at end of timer.c These patches show 0 error or warning with checkpatch.pl --no-tree and have been tested on edminiv2. arch/arm/cpu/arm926ejs/orion5x/cpu.c | 78 +++++++++++++++++++----------- arch/arm/cpu/arm926ejs/orion5x/timer.c | 6 ++- arch/arm/include/asm/arch-orion5x/cpu.h | 1 + 3 files changed, 54 insertions(+), 31 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 260f88b..c36d7bf 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -77,6 +77,17 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) * * If remap function not used, remap_lo must be set as base * + * NOTES: + * + * 1) in order to avoid windows with inconsistent control and base values + * (which could prevent access to BOOTCS and hence execution from FLASH) + * always disable window before writing the base value then reenable it + * by writing the control value. + * + * 2) in order to avoid losing access to BOOTCS when disabling window 7, + * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS, + * then configure windows 6 for its own target. + * * Reference Documentation: * Mbus-L to Mbus Bridge Registers Configuration. * (Sec 25.1 and 25.3 of Datasheet) @@ -86,57 +97,64 @@ int orion5x_config_adr_windows(void) struct orion5x_win_registers *winregs = (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; - /* Window 0: PCIE MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, - ORION5X_WIN_ENABLE), &winregs[0].ctrl); +/* Disable window 0, configure it for its intended target, enable it. */ + writel(0, &winregs[0].ctrl); writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base); writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); - - /* Window 1: PCIE IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, - ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, - ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, + ORION5X_WIN_ENABLE), &winregs[0].ctrl); +/* Disable window 1, configure it for its intended target, enable it. */ + writel(0, &winregs[1].ctrl); writel(ORION5X_ADR_PCIE_IO, &winregs[1].base); writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); - - /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, + ORION5X_WIN_ENABLE), &winregs[1].ctrl); +/* Disable window 2, configure it for its intended target, enable it. */ + writel(0, &winregs[2].ctrl); + writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl); - writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); - - /* Window 3: PCI IO address space */ +/* Disable window 3, configure it for its intended target, enable it. */ + writel(0, &winregs[3].ctrl); + writel(ORION5X_ADR_PCI_IO, &winregs[3].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl); - writel(ORION5X_ADR_PCI_IO, &winregs[3].base); - - /* Window 4: DEV_CS0 address space */ +/* Disable window 4, configure it for its intended target, enable it. */ + writel(0, &winregs[4].ctrl); + writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl); - writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); - - /* Window 5: DEV_CS1 address space */ +/* Disable window 5, configure it for its intended target, enable it. */ + writel(0, &winregs[5].ctrl); + writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl); - writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); - - /* Window 6: DEV_CS2 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, - ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, +/* Disable window 6, configure it for FLASH, enable it. */ + writel(0, &winregs[6].ctrl); + writel(ORION5X_ADR_BOOTROM, &winregs[6].base); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[6].ctrl); - writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); - - /* Window 7: BOOT Memory address space */ +/* Disable window 7, configure it for FLASH, enable it. */ + writel(0, &winregs[7].ctrl); + writel(ORION5X_ADR_BOOTROM, &winregs[7].base); writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl); - writel(ORION5X_ADR_BOOTROM, &winregs[7].base); +/* Disable window 6, configure it for its intended target, enable it. */ + writel(0, &winregs[6].ctrl); + writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, + ORION5X_WIN_ENABLE), &winregs[6].ctrl); return 0; } @@ -265,6 +283,8 @@ int arch_misc_init(void) writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); + /* initialize timer */ + timer_init_r(); return 0; } #endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c index 115448f..089ef47 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c @@ -173,9 +173,11 @@ int timer_init(void) cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); writel(cntmrctrl, CNTMR_CTRL_REG); + return 0; +} +void timer_init_r(void) +{ /* init the timestamp and lastdec value */ reset_timer_masked(); - - return 0; } diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 6ce02a9..c84efaf 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -255,5 +255,6 @@ void reset_cpu(unsigned long ignored); u32 orion5x_device_id(void); u32 orion5x_device_rev(void); unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +void timer_init_r(void); #endif /* __ASSEMBLY__ */ #endif /* _ORION5X_CPU_H */ -- 1.7.0.4

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