May 2010 - U-Boot

[U-Boot] Please pull u-boot-coldfire/master
by TsiChung Liew 28 May '10

28 May '10

The following changes since commit c4976807cbbabd281f45466ac5e47e5639bcc9cb: Wolfgang Denk (1): Coding style cleanup, update CHANGELOG. are available in the git repository at: git://git.denx.de/u-boot-coldfire.git master Wolfgang Denk (1): Prepare v2010.06-rc1 Wolfgang Wegner (3): add missing PCS3 for MCF5445x add CONFIG_SYS_FEC_NO_SHARED_PHY for MCF5445x add CONFIG_SYS_FEC_FULL_MII for MCF5445x Makefile | 4 ++-- arch/m68k/cpu/mcf5445x/cpu_init.c | 31 +++++++++++++++++++++++++++++-- arch/m68k/include/asm/m5445x.h | 1 + 3 files changed, 32 insertions(+), 4 deletions(-)

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[U-Boot] Pull request: u-boot-usb
by Remy Bohmer 28 May '10

28 May '10

The following changes since commit 01f03bda5b22e5aeae5f02fd537da97a41485c73: Wolfgang Denk (1): Prepare v2010.06-rc1 are available in the git repository at: git://git.denx.de/u-boot-usb.git master Sergei Shtylyov (1): USB: fix create_pipe() include/usb.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)

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[U-Boot] Pull request: nand flash
by Scott Wood 28 May '10

28 May '10

The following changes since commit 01f03bda5b22e5aeae5f02fd537da97a41485c73: Wolfgang Denk (1): Prepare v2010.06-rc1 are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git master Andrew Caldwell (1): Blackfin: nand: drain the write buffer before returning drivers/mtd/nand/bfin_nand.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)

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[U-Boot] structure usage for peripheral registers
by Vipin Kumar 28 May '10

28 May '10

hi, The u-boot source has been following a strict rule to use structures to define peripheral registers for some time now I was wondering if there really is an advantage over the macro definitions which is being used in Linux until today or this is just a coding guideline to maintain consistency in the code Thanks and Regards Vipin

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[U-Boot] [PATCH] 85xx: Add is_serdes_configured() support for P2020 SERDES
by Kumar Gala 28 May '10

28 May '10

Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/Makefile | 6 ++- arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 73 +++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p2020_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f064fee..f1abf0e 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -62,11 +62,15 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o +# SERDES support +COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P2010) += p2020_serdes.o +COBJS-$(CONFIG_P2020) += p2020_serdes.o + COBJS = $(COBJS-y) COBJS += cpu.o COBJS += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c new file mode 100644 index 0000000..79fb9bb --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -0,0 +1,73 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x2] = {PCIE1, PCIE2, PCIE3, PCIE3}, + [0x4] = {PCIE1, PCIE1, PCIE3, PCIE3}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {SRIO2, SRIO1, NONE, NONE}, + [0x8] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0x9] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xa] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int i; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds1_cfg][i] == device) + return 1; + } + + return 0; +} + +void fsl_serdes_init(void) +{ +} -- 1.6.0.6

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[U-Boot] Help neede on MPC8315 I2C Interface
by vtvasan v 28 May '10

28 May '10

Hi all, i am working on MPC8315 based board and i am able to port the U-Boot with (VERSION = 2009, PATCHLEVEL = 11, SUBLEVEL = 1). In my board one Temperature sensor chip is connected and i am not able to access the chip from u-Boot. The processor is getting initialized during power-up using I2C EEPROM but once powered up U-Boot is giving time out error when ever i am trying to access the EEPROM and temperature sensor. when i probe the clock signal it is coming only when the processor is getting initialized from the EEPROM. i have disabled the the PCI interface in U-boot since in my board no PCI devices are there. U-Boot 2009.11.1 (May 28 2010 - 15:19:41) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c3, MPC8315E, Rev: 1.2 at 266.667 MHz, CSB: 133.333 MHz Board: MPC8315CTI Rev A i2c_wait: timed out i2c_wait: timed out I2C VAL = 0 I2C: Requested speed:10000, i2c_clk:133333334 FDR:0x3c, div:20480, ga:0x4, gb:0x7, a:10, b:2048, speed:6510 Tr <= 15225 ns FDR:0x3a, div:14336, ga:0x6, gb:0x6, a:14, b:1024, speed:9300 Tr <= 7545 ns divider:13333, est_div:14336, DFSR:6 FDR:0x3a, speed:9300 ready DRAM: 64 MB FLASH: 64 MB Requested speed:10000, i2c_clk:133333334 FDR:0x3c, div:20480, ga:0x4, gb:0x7, a:10, b:2048, speed:6510 Tr <= 15225 ns FDR:0x3a, div:14336, ga:0x6, gb:0x6, a:14, b:1024, speed:9300 Tr <= 7545 ns divider:13333, est_div:14336, DFSR:6 FDR:0x3a, speed:9300 In: serial Out: serial Err: serial i2c_wait: timed out DTT: 1 FAILED INIT Net: eTSEC0, eTSEC1 please help me to find out why there is no activity in MPC8315 I2C interface once U-Boot got loaded. Thanks, Vaasu. TV

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[U-Boot] s5pc1xx: Add support for Samsung Goni board
by Minkyu Kang 28 May '10

28 May '10

This patch adds support for the Samsung Goni board (S5PC110 SoC) Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/samsung/goni/Makefile | 54 ++++ board/samsung/goni/config.mk | 16 + board/samsung/goni/goni.c | 60 ++++ board/samsung/goni/lowlevel_init.S | 585 ++++++++++++++++++++++++++++++++++++ board/samsung/goni/mem_setup.S | 265 ++++++++++++++++ board/samsung/goni/onenand.c | 36 +++ include/configs/s5p_goni.h | 241 +++++++++++++++ 10 files changed, 1262 insertions(+), 0 deletions(-) create mode 100644 board/samsung/goni/Makefile create mode 100644 board/samsung/goni/config.mk create mode 100644 board/samsung/goni/goni.c create mode 100644 board/samsung/goni/lowlevel_init.S create mode 100644 board/samsung/goni/mem_setup.S create mode 100644 board/samsung/goni/onenand.c create mode 100644 include/configs/s5p_goni.h diff --git a/MAINTAINERS b/MAINTAINERS index 7f688c3..d00756f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -628,6 +628,7 @@ Simon Kagstrom <simon.kagstrom(a)netinsight.net> Minkyu Kang <mk7.kang(a)samsung.com> SMDKC100 ARM CORTEX-A8 (S5PC100 SoC) + s5p_goni ARM CORTEX-A8 (S5PC110 SoC) Nishant Kamat <nskamat(a)ti.com> diff --git a/MAKEALL b/MAKEALL index 326bde0..f1eefb6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -649,6 +649,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_zoom1 \ omap3_zoom2 \ smdkc100 \ + s5p_goni \ " ######################################################################### diff --git a/Makefile b/Makefile index e49def3..ef37b99 100644 --- a/Makefile +++ b/Makefile @@ -3179,6 +3179,9 @@ omap3_zoom2_config : unconfig smdkc100_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx +s5p_goni_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 goni samsung s5pc1xx + ######################################################################### ## XScale Systems ######################################################################### diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile new file mode 100644 index 0000000..9b4c886 --- /dev/null +++ b/board/samsung/goni/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := goni.o onenand.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(SOBJS) $(OBJS) + $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/goni/config.mk b/board/samsung/goni/config.mk new file mode 100644 index 0000000..2da9ca1 --- /dev/null +++ b/board/samsung/goni/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2008 # Samsung Elecgtronics +# Kyungmin Park <kyungmin.park(a)samsung.com> +# + +# On S5PC100 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x38000000 to 0x40000000 (128MiB) +# +# On S5PC110 we use the 128 MiB OneDRAM bank at +# +# 0x30000000 to 0x35000000 (80MiB) +# 0x40000000 to 0x50000000 (256MiB) +# +TEXT_BASE = 0x34800000 diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c new file mode 100644 index 0000000..0defb7b --- /dev/null +++ b/board/samsung/goni/goni.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2008-2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* Workaround: it will be removed when mach-types is updated */ +#ifndef MACH_TYPE_GONI +#define MACH_TYPE_GONI 2862 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_GONI; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("Board:\tGoni\n"); + return 0; +} +#endif diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S new file mode 100644 index 0000000..4b72992 --- /dev/null +++ b/board/samsung/goni/lowlevel_init.S @@ -0,0 +1,585 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/power.h> + +/* + * Register usages: + * + * r5 has zero always + * r7 has S5PC100 GPIO base, 0xE0300000 + * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively + * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on + */ + +_TEXT_BASE: + .word TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + mov r11, lr + + /* r5 has always zero */ + mov r5, #0 + + ldr r7, =S5PC100_GPIO_BASE + ldr r8, =S5PC100_GPIO_BASE + /* Read CPU ID */ + ldr r2, =S5PC1XX_PRO_ID + ldr r0, [r2] + mov r1, #0x00010000 + and r0, r0, r1 + cmp r0, r5 + beq 100f + ldr r8, =S5PC110_GPIO_BASE +100: + /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */ + cmp r7, r8 + beq skip_check_didle @ Support C110 only + + ldr r0, =S5PC110_RST_STAT + ldr r1, [r0] + and r1, r1, #0x000D0000 + cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP + beq didle_wakeup + cmp r7, r8 + +skip_check_didle: + addeq r0, r8, #0x280 @ S5PC100_GPIO_J4 + addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4 + ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET + bic r1, r1, #(0xf << 4) @ 1 * 4-bit + orr r1, r1, #(0x1 << 4) + str r1, [r0, #0x0] @ GPIO_CON_OFFSET + + ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET +#ifdef CONFIG_ONENAND_IPL + orr r1, r1, #(1 << 1) @ 1 * 1-bit +#else + bic r1, r1, #(1 << 1) +#endif + str r1, [r0, #0x4] @ GPIO_DAT_OFFSET + + /* Don't setup at s5pc100 */ + beq 100f + + /* + * Initialize Async Register Setting for EVT1 + * Because we are setting EVT1 as the default value of EVT0, + * setting EVT0 as well does not make things worse. + * Thus, for the simplicity, we set for EVT0, too + * + * The "Async Registers" are: + * 0xE0F0_0000 + * 0xE1F0_0000 + * 0xF180_0000 + * 0xF190_0000 + * 0xF1A0_0000 + * 0xF1B0_0000 + * 0xF1C0_0000 + * 0xF1D0_0000 + * 0xF1E0_0000 + * 0xF1F0_0000 + * 0xFAF0_0000 + */ + ldr r0, =0xe0f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xe1f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1800000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1900000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1a00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1b00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1c00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1d00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1e00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xf1f00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + ldr r0, =0xfaf00000 + ldr r1, [r0] + bic r1, r1, #0x1 + str r1, [r0] + + /* + * Diable ABB block to reduce sleep current at low temperature + * Note that it's hidden register setup don't modify it + */ + ldr r0, =0xE010C300 + ldr r1, =0x00800000 + str r1, [r0] + +100: + /* IO retension release */ + ldreq r0, =S5PC100_OTHERS @ 0xE0108200 + ldrne r0, =S5PC110_OTHERS @ 0xE010E000 + ldr r1, [r0] + ldreq r2, =(1 << 31) @ IO_RET_REL + ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + orr r1, r1, r2 + /* Do not release retention here for S5PC110 */ + streq r1, [r0] + +#ifndef CONFIG_ONENAND_IPL + /* Disable Watchdog */ + ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000 + ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000 + str r5, [r0] + + /* setting SRAM */ + ldreq r0, =S5PC100_SROMC_BASE + ldrne r0, =S5PC110_SROMC_BASE + ldr r1, =0x9 + str r1, [r0] +#endif + + /* S5PC100 has 3 groups of interrupt sources */ + ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000 + ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000 + add r1, r0, #0x00100000 + add r2, r0, #0x00200000 + + /* Disable all interrupts (VIC0, VIC1 and VIC2) */ + mvn r3, #0x0 + str r3, [r0, #0x14] @ INTENCLEAR + str r3, [r1, #0x14] @ INTENCLEAR + str r3, [r2, #0x14] @ INTENCLEAR + +#ifndef CONFIG_ONENAND_IPL + /* Set all interrupts as IRQ */ + str r5, [r0, #0xc] @ INTSELECT + str r5, [r1, #0xc] @ INTSELECT + str r5, [r2, #0xc] @ INTSELECT + + /* Pending Interrupt Clear */ + str r5, [r0, #0xf00] @ INTADDRESS + str r5, [r1, #0xf00] @ INTADDRESS + str r5, [r2, #0xf00] @ INTADDRESS +#endif + +#ifndef CONFIG_ONENAND_IPL + /* for UART */ + bl uart_asm_init + + bl internal_ram_init +#endif + +#ifdef CONFIG_ONENAND_IPL + /* init system clock */ + bl system_clock_init + + /* OneNAND Sync Read Support at S5PC110 only + * RM[15] : Sync Read + * BRWL[14:12] : 7 CLK + * BL[11:9] : Continuous + * VHF[3] : Very High Frequency Enable (Over 83MHz) + * HF[2] : High Frequency Enable (Over 66MHz) + * WM[1] : Sync Write + */ + cmp r7, r8 + ldrne r1, =0xE006 + ldrne r0, =0xB001E442 + strneh r1, [r0] + + /* + * GCE[26] : Gated Clock Enable + * RPE[17] : Enables Read Prefetch + */ + ldrne r1, =((1 << 26) | (1 << 17) | 0xE006) + ldrne r0, =0xB0600000 + strne r1, [r0, #0x100] @ ONENAND_IF_CTRL + ldrne r1, =0x1212 + strne r1, [r0, #0x108] + + /* Board detection to set proper memory configuration */ + cmp r7, r8 + moveq r9, #1 /* r9 has 1Gib default at s5pc100 */ + movne r9, #2 /* r9 has 2Gib default at s5pc110 */ + + ldr r2, =0xE0200200 + ldr r4, [r2, #0x48] + + bic r1, r4, #(0x3F << 4) /* PULLUP_DISABLE: 3 * 2-bit */ + bic r1, r1, #(0x3 << 2) /* PULLUP_DISABLE: 2 * 2-bit */ + bic r1, r1, #(0x3 << 14) /* PULLUP_DISABLE: 2 * 2-bit */ + str r1, [r2, #0x48] + /* For write completion */ + nop + nop + + ldr r3, [r2, #0x44] + and r1, r3, #(0x7 << 2) + mov r1, r1, lsr #2 + cmp r1, #0x5 + moveq r9, #3 + cmp r1, #0x6 + moveq r9, #1 + cmp r1, #0x7 + moveq r9, #2 + and r0, r3, #(0x1 << 1) + mov r0, r0, lsr #1 + orr r1, r1, r0, lsl #3 + cmp r1, #0x8 + moveq r9, #3 + and r1, r3, #(0x7 << 2) + mov r1, r1, lsr #2 + and r0, r3, #(0x1 << 7) + mov r0, r0, lsr #7 + orr r1, r1, r0, lsl #3 + cmp r1, #0x9 + moveq r9, #3 + str r4, [r2, #0x48] /* Restore PULLUP configuration */ + + bl mem_ctrl_asm_init + + /* Wakeup support. Don't know if it's going to be used, untested. */ + ldreq r0, =S5PC100_RST_STAT + ldrne r0, =S5PC110_RST_STAT + ldr r1, [r0] + biceq r1, r1, #0xfffffff7 + moveq r2, #(1 << 3) + bicne r1, r1, #0xfffeffff + movne r2, #(1 << 16) + cmp r1, r2 + bne 1f +wakeup: + /* turn off L2 cache */ + bl l2_cache_disable + + cmp r7, r8 + ldreq r0, =0xC100 + ldrne r0, =0xC110 + + /* invalidate L2 cache also */ + bl invalidate_dcache + + /* turn on L2 cache */ + bl l2_cache_enable + + cmp r7, r8 + /* Load return address and jump to kernel */ + ldreq r0, =S5PC100_INFORM0 + ldrne r0, =S5PC110_INFORM0 + + /* r1 = physical address of s5pc1xx_cpu_resume function */ + ldr r1, [r0] + + /* Jump to kernel (sleep-s5pc1xx.S) */ + mov pc, r1 + nop + nop +#else + cmp r7, r8 + /* Clear wakeup status register */ + ldreq r0, =S5PC100_WAKEUP_STAT + ldrne r0, =S5PC110_WAKEUP_STAT + ldr r1, [r0] + str r1, [r0] + + /* IO retension release */ + ldreq r0, =S5PC100_OTHERS @ 0xE0108200 + ldrne r0, =S5PC110_OTHERS @ 0xE010E000 + ldr r1, [r0] + ldreq r2, =(1 << 31) @ IO_RET_REL + ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)) + orr r1, r1, r2 + str r1, [r0] + +#endif + b 1f + +didle_wakeup: + /* Wait when APLL is locked */ + ldr r0, =0xE0100100 @ S5PC110_APLL_CON +lockloop: + ldr r1, [r0] + and r1, r1, #(1 << 29) + cmp r1, #(1 << 29) + bne lockloop + + ldr r0, =S5PC110_INFORM0 + ldr r1, [r0] + mov pc, r1 + nop + nop + nop + nop + nop + +1: + mov lr, r11 + mov pc, lr + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f +100: + /* Set Lock Time */ + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x000] @ S5PC100_APLL_LOCK + str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK + str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK + str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK + + /* S5P_APLL_CON */ + ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz) + str r1, [r0, #0x100] + /* S5P_MPLL_CON */ + ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz) + str r1, [r0, #0x104] + /* S5P_EPLL_CON */ + ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz) + str r1, [r0, #0x108] + /* S5P_HPLL_CON */ + ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96 + str r1, [r0, #0x10C] + + ldr r1, [r0, #0x300] + ldr r2, =0x00003fff + bic r1, r1, r2 + ldr r2, =0x00011301 + + orr r1, r1, r2 + str r1, [r0, #0x300] + ldr r1, [r0, #0x304] + ldr r2, =0x00011110 + orr r1, r1, r2 + str r1, [r0, #0x304] + ldr r1, =0x00000001 + str r1, [r0, #0x308] + + /* Set Source Clock */ + ldr r1, =0x00001111 @ A, M, E, HPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 + + b 200f +110: + ldr r0, =0xE010C000 @ S5PC110_PWR_CFG + + /* Set OSC_FREQ value */ + ldr r1, =0xf + str r1, [r0, #0x100] @ S5PC110_OSC_FREQ + + /* Set MTC_STABLE value */ + ldr r1, =0xffffffff + str r1, [r0, #0x110] @ S5PC110_MTC_STABLE + + /* Set CLAMP_STABLE value */ + ldr r1, =0x3ff03ff + str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE + + ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + + /* Set Clock divider */ + ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 + str r1, [r0, #0x300] + ldr r1, =0x11110111 @ UART[3210]: MMC[3210] + str r1, [r0, #0x310] + + /* Set Lock Time */ + ldr r1, =0x2cf @ Locktime : 30us + str r1, [r0, #0x000] @ S5PC110_APLL_LOCK + ldr r1, =0xe10 @ Locktime : 0xe10 = 3600 + str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK + str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK + str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK + + /* S5PC110_APLL_CON */ + ldr r1, =0x80C80601 @ 800MHz + str r1, [r0, #0x100] + /* S5PC110_MPLL_CON */ + ldr r1, =0x829B0C01 @ 667MHz + str r1, [r0, #0x108] + /* S5PC110_EPLL_CON */ + ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2 + str r1, [r0, #0x110] + /* S5PC110_VPLL_CON */ + ldr r1, =0x806C0603 @ 54MHz + str r1, [r0, #0x120] + + /* Set Source Clock */ + ldr r1, =0x10001111 @ A, M, E, VPLL Muxing + str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0 + + /* OneDRAM(DMC0) clock setting */ + ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL + str r1, [r0, #0x218] @ S5PC110_CLK_SRC6 + ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1 + str r1, [r0, #0x318] @ S5PC110_CLK_DIV6 + + /* XCLKOUT = XUSBXTI 24MHz */ + add r2, r0, #0xE000 @ S5PC110_OTHERS + ldr r1, [r2] + orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI + str r1, [r2] + + /* CLK_IP0 */ + ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5] + str r1, [r0, #0x460] @ S5PC110_CLK_IP0 + + /* CLK_IP1 */ + ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16] + @ NANDXL[24] + str r1, [r0, #0x464] @ S5PC110_CLK_IP1 + + /* CLK_IP2 */ + ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9] + @ HOSTIF[10] HSMMC0[16] + @ HSMMC2[18] VIC[27:24] + str r1, [r0, #0x468] @ S5PC110_CLK_IP2 + + /* CLK_IP3 */ + ldr r1, =0x8eff038c @ I2C[8:6] + @ SYSTIMER[16] UART0[17] + @ UART1[18] UART2[19] + @ UART3[20] WDT[22] + @ PWM[23] GPIO[26] SYSCON[27] + str r1, [r0, #0x46c] @ S5PC110_CLK_IP3 + + /* CLK_IP4 */ + ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5] + str r1, [r0, #0x470] @ S5PC110_CLK_IP3 + +200: + /* wait at least 200us to stablize all clock */ + mov r2, #0x10000 +1: subs r2, r2, #1 + bne 1b + + mov pc, lr + +#ifndef CONFIG_ONENAND_IPL +internal_ram_init: + ldreq r0, =0xE3800000 + ldrne r0, =0xF1500000 + ldr r1, =0x0 + str r1, [r0] + + mov pc, lr +#endif + +#ifndef CONFIG_ONENAND_IPL +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* set GPIO to enable UART0-UART4 */ + mov r0, r8 + ldr r1, =0x22222222 + str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET + ldr r1, =0x00002222 + str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET + + /* Check S5PC100 */ + cmp r7, r8 + bne 110f + + /* UART_SEL GPK0[5] at S5PC100 */ + add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET + ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit + orr r1, r1, #(0x1 << 20) @ Output + str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit + orr r1, r1, #(0x2 << 10) @ Pull-up enabled + str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit + str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + + b 200f +110: + /* + * Note that the following address + * 0xE020'0360 is reserved address at S5PC100 + */ + /* UART_SEL MP0_5[7] at S5PC110 */ + add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET + ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit + orr r1, r1, #(0x1 << 28) @ Output + str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET + + ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit + orr r1, r1, #(0x2 << 14) @ Pull-up enabled + str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET + + ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit + str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET +200: + mov pc, lr +#endif diff --git a/board/samsung/goni/mem_setup.S b/board/samsung/goni/mem_setup.S new file mode 100644 index 0000000..c4d2845 --- /dev/null +++ b/board/samsung/goni/mem_setup.S @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2009 Samsung Electrnoics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + cmp r7, r8 + + ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 + ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 + ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 + + /* DLL parameter setting */ + ldr r1, =0x50101000 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + ldr r1, =0x000000f4 + str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET + strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET + ldreq r1, =0x0 + streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET + + /* DLL on */ + ldr r1, =0x50101002 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* DLL start */ + ldr r1, =0x50101003 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + mov r2, #0x4000 +wait: subs r2, r2, #0x1 + cmp r2, #0x0 + bne wait + + cmp r7, r8 + /* Force value locking for DLL off */ + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* DLL off */ + ldr r1, =0x50101009 + str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET + strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET + + /* auto refresh off */ + ldr r1, =0xff001010 | (1 << 7) + ldr r2, =0xff001010 | (1 << 7) + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r2, [r6, #0x000] @ CONCONTROL_OFFSET + + /* + * Burst Length 4, 2 chips, 32-bit, LPDDR + * OFF: dynamic self refresh, force precharge, dynamic power down off + */ + ldr r1, =0x00212100 + ldr r2, =0x00212100 + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* + * Note: + * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) + * So finally Bank1 OneDRAM should address start at at 0x3000'0000 + */ + + /* + * DMC0: CS0 : S5PC100/S5PC110 + * 0x30 -> 0x30000000 + * 0xf8 -> 0x37FFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + ldr r3, =0x30f80222 + ldr r4, =0x40f00222 +swap_memory: + str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET + str r4, [r0, #0x00C] @ dummy write + + /* + * DMC1: CS0 : S5PC110 + * 0x40 -> 0x40000000 + * 0xf8 -> 0x47FFFFFF (1Gib) + * 0x40 -> 0x40000000 + * 0xf0 -> 0x4FFFFFFF (2Gib) + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits - Col (1Gib) + * [11:8 ] 3: 10 bits - Col (2Gib) + * [ 7:4 ] 2: 14 bits - Row + * [ 3:0 ] 2: 4 banks + */ + /* Default : 2GiB */ + ldr r4, =0x40f01322 @ 2Gib: MCP B + ldr r5, =0x50f81312 @ dummy: MCP D + cmp r9, #1 + ldreq r4, =0x40f81222 @ 1Gib: MCP A + cmp r9, #3 + ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D + cmp r9, #4 + ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E + + cmp r7, r8 + strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET + strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET + + /* + * DMC0: CS1: S5PC100 + * 0x38 -> 0x38000000 + * 0xf8 -> 0x3fFFFFFF + * [15:12] 0: Linear + * [11:8 ] 2: 9 bits + * [ 7:4 ] 2: 14 bits + * [ 3:0 ] 2: 4 banks + */ + eoreq r3, r3, #0x08000000 + streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET + + ldr r1, =0x20000000 + str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET + strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET + + /* + * S5PC100: + * DMC: CS0: 166MHz + * CS1: 166MHz + * S5PC110: + * DMC0: CS0: 166MHz + * DMC1: CS0: 200MHz + * + * 7.8us * 200MHz %LE %LONG1560(0x618) + * 7.8us * 166MHz %LE %LONG1294(0x50E) + * 7.8us * 133MHz %LE %LONG1038(0x40E), + * 7.8us * 100MHz %LE %LONG780(0x30C), + */ + ldr r1, =0x0000050E + str r1, [r0, #0x030] @ TIMINGAREF_OFFSET + ldrne r1, =0x00000618 + strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET + + ldr r1, =0x14233287 + str r1, [r0, #0x034] @ TIMINGROW_OFFSET + ldrne r1, =0x182332c8 + strne r1, [r6, #0x034] @ TIMINGROW_OFFSET + + ldr r1, =0x12130005 + str r1, [r0, #0x038] @ TIMINGDATA_OFFSET + ldrne r1, =0x13130005 + strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET + + ldr r1, =0x0E140222 + str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET + ldrne r1, =0x0E180222 + strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET + + /* chip0 Deselect */ + ldr r1, =0x07000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 PALL */ + ldr r1, =0x01000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 REFA */ + ldr r1, =0x05000000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip0 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 MRS */ + ldr r1, =0x00000032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip0 EMRS */ + ldr r1, =0x00020020 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 Deselect */ + ldr r1, =0x07100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 PALL */ + ldr r1, =0x01100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 REFA */ + ldr r1, =0x05100000 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + /* chip1 REFA */ + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 MRS */ + ldr r1, =0x00100032 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* chip1 EMRS */ + ldr r1, =0x00120020 + str r1, [r0, #0x010] @ DIRECTCMD_OFFSET + strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET + + /* auto refresh on */ + ldr r1, =0xFF002030 | (1 << 7) + str r1, [r0, #0x000] @ CONCONTROL_OFFSET + strne r1, [r6, #0x000] @ CONCONTROL_OFFSET + + /* PwrdnConfig */ + ldr r1, =0x00100002 + str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET + strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET + + ldr r1, =0x00212113 + str r1, [r0, #0x004] @ MEMCONTROL_OFFSET + strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET + + /* Skip when S5PC110 */ + bne 1f + + /* Check OneDRAM access area at s5pc100 */ + ldreq r3, =0x38f80222 + ldreq r1, =0x37ffff00 + str r3, [r1] + ldr r2, [r1] + cmp r2, r3 + beq swap_memory +1: + mov pc, lr + + .ltorg diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c new file mode 100644 index 0000000..8d3769b --- /dev/null +++ b/board/samsung/goni/onenand.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2008-2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include <linux/mtd/samsung_onenand.h> +#include <onenand_uboot.h> + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; +} diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h new file mode 100644 index 0000000..4f6b798 --- /dev/null +++ b/include/configs/s5p_goni.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Configuation settings for the SAMSUNG Universal (s5pc100) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ +#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ +#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ +#define CONFIG_MACH_GONI 1 /* working with Goni */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* input clock of PLL: has 24MHz input clock at S5PC110 */ +#define CONFIG_SYS_CLK_FREQ_C110 24000000 + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x30000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* + * Size of malloc() pool + * 1MB = 0x100000, 0x100000 = 1024 * 1024 + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */ + /* initial data */ +/* + * select serial console configuration + */ +#define CONFIG_SERIAL2 1 /* use SERIAL2 */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_BAUDRATE 115200 + +/* It should define before config_cmd_default.h */ +#define CONFIG_SYS_NO_FLASH 1 +/*********************************************************** + * Command definition + ***********************************************************/ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_BOOTD +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_ECHO +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_NET +#undef CONFIG_XYZMODEM +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_ONENAND +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS + +/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ +#define MTDIDS_DEFAULT "onenand0=samsung-onenand" +#define MTDPARTS_DEFAULT "mtdparts=samsung-onenand:1m(bootloader)"\ + ",256k(params)"\ + ",2816k(config)"\ + ",8m(csa)"\ + ",7m(kernel)"\ + ",1m(log)"\ + ",12m(modem)"\ + ",60m(qboot)"\ + ",-(UBI)\0" + +#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT + +#define CONFIG_BOOTCOMMAND "run ubifsboot" + +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ + " ${console} ${meminfo}" + +#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" + +#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \ + " rootfstype=cramfs " CONFIG_COMMON_BOOT + +#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ + " onenand write 0x32008000 0x0 0x100000\0" + +#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6" + +#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc" + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_UPDATEB \ + "updatek=" \ + "onenand erase 0xc00000 0x600000;" \ + "onenand write 0x31008000 0xc00000 0x600000\0" \ + "updateu=" \ + "onenand erase 0x01560000 0x1eaa0000;" \ + "onenand write 0x32000000 0x1260000 0x8C0000\0" \ + "bootk=" \ + "onenand read 0x30007FC0 0xc00000 0x600000;" \ + "bootm 0x30007FC0\0" \ + "flashboot=" \ + "set bootargs root=/dev/mtdblock${bootblock} " \ + "rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \ + "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ + "ubifsboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + CONFIG_COMMON_BOOT "; run bootk\0" \ + "tftpboot=" \ + "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ + CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \ + "bootm 0x30007FC0\0" \ + "ramboot=" \ + "set bootargs " CONFIG_RAMDISK_BOOT \ + " initrd=0x33000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "set bootargs root=${mmcblk} rootfstype=${rootfstype}" \ + CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \ + CONFIG_COMMON_BOOT "; run bootk\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "verify=n\0" \ + "rootfstype=cramfs\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "mtdparts=" MTDPARTS_DEFAULT \ + "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ + "mmcblk=/dev/mmcblk1p1\0" \ + "bootblock=9\0" \ + "ubiblock=8\0" \ + "ubi=enabled\0" \ + "opts=always_resume=1" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Goni # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ + +/* Goni has 2 banks of DRAM, but swap the bank */ +#define CONFIG_NR_DRAM_BANKS 3 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ +#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ +#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC1 Bank #1 */ +#define PHYS_SDRAM_3_SIZE (128 << 20) /* 256 MB in Bank #1 */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */ +#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */ + +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_SAMSUNG_ONENAND 1 +#define CONFIG_SYS_ONENAND_BASE 0xB0000000 + +#define CONFIG_DOS_PARTITION 1 + +#endif /* __CONFIG_H */ -- 1.6.3.3

1 0

[U-Boot] No network in Linux on Olimex SAM9_L9260 (Atmel AT91SAM9260EK)
by Thorsten Mühlfelder 28 May '10

28 May '10

Hi, I'm using an Olimex SAM9_L9260 based board here, which currently uses an U-Boot 1.2 delivered by Olimex. Sadly this U-Boot version always marks it's enviroment area as bad block on each write (probably it is patched by Olimex to work with an old Atmel Sam-Ba version, that has the same error and is a different story). So I've decided to compile a new U-Boot. My Toolchain is Codesourcery 2010q1 on a 32 bit Slackware Linux and I've used U-Boot 2010.03 sources. The board runs a 2.6.24-rt kernel with patch for Olimex support. As the Olimex board is heavily based on the Atmel AT91SAM9260EK board I've decided to build U-Boot for this one. I only had to tweak the machine type so that Linux can be started. On Linux bootup I've noticed that the board is not able to get an IP via DHCP with the new bootloader. On my research for the problem I've found out that U-Boot won't detect any PHY. Google search returned that I have to modify board/atmel/at91sam9260ek/at91sam9260ek.c for the PHY on the Olimex board: from rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); to rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01); After that U-Boot detects a "macb" but still no DHCP answer in Linux. I've tried the old 1.2 bootloader again and DHCP works fine. So my questions for now are: 1. Does U-Boot have to detect the PHY and initialize it or is it just needed for network bootup? 2. After endless compile sessions (I never compiled u-boot before) I'm completely out of any idea what I can try now to get network in Linux working. Any suggestions? :-) It would be really great to receive some help because this board has already driven me mad because of the Atmel Sam-Ba flas tool bugs I've mentioned before. ;-) Thanks in advance.

3 4

[U-Boot] [PATCH] nios2: remove EP1C20, EP1S10, EP1S40 boards
by Thomas Chou 28 May '10

28 May '10

The example configuration files of nios2-generic board can generated binary to run on the EP1C20, EP1S10, and EP1S40 boards. So the three boards can be removed. With nios2-generic approach, the fpga parameter header file can be generated from hardware designs using tools. Porting u-boot for nios2 boards is simplified. Vendors can supply their fpga parameter file or patches to add a new nios2-generic board instance. There is no need to include other boards support for nios2 in the u-boot mainline. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- MAINTAINERS | 3 - MAKEALL | 3 - Makefile | 9 -- board/altera/ep1c20/Makefile | 55 ----------- board/altera/ep1c20/config.mk | 31 ------ board/altera/ep1c20/ep1c20.c | 52 ---------- board/altera/ep1s10/Makefile | 55 ----------- board/altera/ep1s10/config.mk | 31 ------ board/altera/ep1s10/ep1s10.c | 52 ---------- board/altera/ep1s40/Makefile | 55 ----------- board/altera/ep1s40/config.mk | 31 ------ board/altera/ep1s40/ep1s40.c | 47 --------- include/configs/EP1C20.h | 214 ----------------------------------------- include/configs/EP1S10.h | 207 --------------------------------------- include/configs/EP1S40.h | 207 --------------------------------------- 15 files changed, 0 insertions(+), 1052 deletions(-) delete mode 100644 board/altera/ep1c20/Makefile delete mode 100644 board/altera/ep1c20/config.mk delete mode 100644 board/altera/ep1c20/ep1c20.c delete mode 100644 board/altera/ep1s10/Makefile delete mode 100644 board/altera/ep1s10/config.mk delete mode 100644 board/altera/ep1s10/ep1s10.c delete mode 100644 board/altera/ep1s40/Makefile delete mode 100644 board/altera/ep1s40/config.mk delete mode 100644 board/altera/ep1s40/ep1s40.c delete mode 100644 include/configs/EP1C20.h delete mode 100644 include/configs/EP1S10.h delete mode 100644 include/configs/EP1S40.h diff --git a/MAINTAINERS b/MAINTAINERS index 46e051b..bc9fad1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -855,9 +855,6 @@ Scott McNutt <smcnutt(a)psyent.com> PCI5441 Nios-II PK1C20 Nios-II - EP1C20 Nios-II - EP1S10 Nios-II - EP1S40 Nios-II nios2-generic Nios-II ######################################################################### diff --git a/MAKEALL b/MAKEALL index 216b89b..90bfd09 100755 --- a/MAKEALL +++ b/MAKEALL @@ -819,9 +819,6 @@ LIST_nios=" \ ######################################################################### LIST_nios2=" \ - EP1C20 \ - EP1S10 \ - EP1S40 \ PCI5441 \ PK1C20 \ nios2-generic \ diff --git a/Makefile b/Makefile index af6e1ee..3802b17 100644 --- a/Makefile +++ b/Makefile @@ -3523,15 +3523,6 @@ DK1S10_config: unconfig ## Nios-II ######################################################################### -EP1C20_config : unconfig - @$(MKCONFIG) EP1C20 nios2 nios2 ep1c20 altera - -EP1S10_config : unconfig - @$(MKCONFIG) EP1S10 nios2 nios2 ep1s10 altera - -EP1S40_config : unconfig - @$(MKCONFIG) EP1S40 nios2 nios2 ep1s40 altera - PK1C20_config : unconfig @$(MKCONFIG) PK1C20 nios2 nios2 pk1c20 psyent diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile deleted file mode 100644 index acad2aa..0000000 --- a/board/altera/ep1c20/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).a - -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk deleted file mode 100644 index dab2740..0000000 --- a/board/altera/ep1c20/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt(a)psyent.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c deleted file mode 100644 index 82900f7..0000000 --- a/board/altera/ep1c20/ep1c20.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1C20\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile deleted file mode 100644 index acad2aa..0000000 --- a/board/altera/ep1s10/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).a - -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk deleted file mode 100644 index dab2740..0000000 --- a/board/altera/ep1s10/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt(a)psyent.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c deleted file mode 100644 index cf886da..0000000 --- a/board/altera/ep1s10/ep1s10.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1S10\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile deleted file mode 100644 index acad2aa..0000000 --- a/board/altera/ep1s40/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).a - -COMOBJS := ../common/AMDLV065D.o ../common/epled.o - -COBJS := $(BOARD).o $(COMOBJS) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk deleted file mode 100644 index dab2740..0000000 --- a/board/altera/ep1s40/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2005, Psyent Corporation <www.psyent.com> -# Scott McNutt <smcnutt(a)psyent.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0x01fc0000 - -PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c deleted file mode 100644 index 6395de7..0000000 --- a/board/altera/ep1s40/ep1s40.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -int checkboard (void) -{ - puts ("BOARD : Altera EP-1S40\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h deleted file mode 100644 index 3920d35..0000000 --- a/include/configs/EP1C20.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1C20 1 /* EP1C20 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for - * epcs device access is enabled. The base address is the epcs - * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. - * The register base is currently at offset 0x600 from the memory base. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- leds are, after all, - * board-specific, no? - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#undef CONFIG_CMD_BOOTD -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h deleted file mode 100644 index bfbf8c1..0000000 --- a/include/configs/EP1S10.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S10 1 /* EP1S10 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h deleted file mode 100644 index 4d905fe..0000000 --- a/include/configs/EP1S40.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * (C) Copyright 2005, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*------------------------------------------------------------------------ - * BOARD/CPU - *----------------------------------------------------------------------*/ -#define CONFIG_EP1S40 1 /* EP1S40 board */ -#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ - -#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ - -/*------------------------------------------------------------------------ - * CACHE -- the following will support II/s and II/f. The II/s does not - * have dcache, so the cache instructions will behave as NOPs. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ -#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ -#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ -#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ - -/*------------------------------------------------------------------------ - * MEMORY BASE ADDRESSES - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ - -/*------------------------------------------------------------------------ - * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET - -/*------------------------------------------------------------------------ - * FLASH (AM29LV065D) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ - -/*------------------------------------------------------------------------ - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) - -/*------------------------------------------------------------------------ - * CONSOLE - *----------------------------------------------------------------------*/ -#define CONFIG_ALTERA_UART 1 /* Use altera uart */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ -#else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ -#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ - -/*------------------------------------------------------------------------ - * EPCS Device -- None for stratix. - *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE - -/*------------------------------------------------------------------------ - * DEBUG - *----------------------------------------------------------------------*/ -#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ - -/*------------------------------------------------------------------------ - * TIMEBASE -- - * - * The high res timer defaults to 1 msec. Since it includes the period - * registers, the interrupt frequency can be reduced using TMRCNT. - * If the default period is acceptable, TMRCNT can be left undefined. - * TMRMS represents the desired mecs per tick (msecs per interrupt). - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_HZ 1000 /* Always 1000 */ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec) */ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) - -/*------------------------------------------------------------------------ - * STATUS LED -- Provides a simple blinking led. For Nios2 each board - * must implement its own led routines -- since leds are board-specific. - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ -#define CONFIG_STATUS_LED /* Enable status driver */ - -#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ -#define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ - -/*------------------------------------------------------------------------ - * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... - * and really doesn't need any additional clutter. So I choose the lazy - * way out to avoid changes there -- define the base address to ensure - * cache bypass so there's no need to monkey with inx/outx macros. - *----------------------------------------------------------------------*/ -#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 /* Using SMC91c111 */ -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ - -#define CONFIG_ETHADDR 08:00:3e:26:0a:5b -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.2.21 -#define CONFIG_SERVERIP 192.168.2.16 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - - -/*------------------------------------------------------------------------ - * MISC - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* Provide extended help*/ -#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ -#define CONFIG_SYS_MAXARGS 16 /* Max command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 - -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " - -#endif /* __CONFIG_H */ -- 1.6.6.1

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[U-Boot] old nios arch removal
by Thomas Chou 28 May '10

28 May '10

Dear Scott, The old nios arch is obsolete and the build has been broken for a long time. Shall we remove it from u-boot? Best regards, Thomas

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