November 2010 - U-Boot

[U-Boot] [PATCH] pl01x: use C structs and readl/writel
by Rabin Vincent 30 Nov '10

30 Nov '10

Use C structs for registers, and use readl/writel instead of custom accessors. Acked-by: Michael Brandt <michael.brandt(a)stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent(a)stericsson.com> --- drivers/serial/serial_pl01x.c | 56 ++++++++++++++++++++++------------------ drivers/serial/serial_pl01x.h | 41 ++++++++++++++++-------------- 2 files changed, 53 insertions(+), 44 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index c645cef..d2609d6 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -29,12 +29,10 @@ #include <common.h> #include <watchdog.h> +#include <asm/io.h> #include "serial_pl01x.h" -#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) -#define IO_READ(addr) (*(volatile unsigned int *)(addr)) - /* * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 @@ -49,16 +47,22 @@ static void pl01x_putc (int portnum, char c); static int pl01x_getc (int portnum); static int pl01x_tstc (int portnum); +static struct pl01x_regs *pl01x_get_regs(int portnum) +{ + return (struct pl01x_regs *) port[portnum]; +} + #ifdef CONFIG_PL010_SERIAL int serial_init (void) { + struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); unsigned int divisor; /* ** First, disable everything. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + writel(0, &regs->pl010_cr); /* ** Set baud rate @@ -89,20 +93,18 @@ int serial_init (void) divisor = UART_PL010_BAUD_38400; } - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, - ((divisor & 0xf00) >> 8)); - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm); + writel(divisor & 0xff, &regs->pl010_lcrl); /* ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, - (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh); /* ** Finally, enable the UART */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + writel(UART_PL010_CR_UARTEN, &regs->pl010_cr); return 0; } @@ -113,6 +115,7 @@ int serial_init (void) int serial_init (void) { + struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); unsigned int temp; unsigned int divider; unsigned int remainder; @@ -121,7 +124,7 @@ int serial_init (void) /* ** First, disable everything. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + writel(0, &regs->pl011_cr); /* ** Set baud rate @@ -135,21 +138,20 @@ int serial_init (void) temp = (8 * remainder) / baudRate; fraction = (temp >> 1) + (temp & 1); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + writel(divider, &regs->pl011_ibrd); + writel(fraction, &regs->pl011_fbrd); /* ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, - (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, + &regs->pl011_lcrh); /* ** Finally, enable the UART */ - IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, - (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | - UART_PL011_CR_RXE)); + writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, + &regs->pl011_cr); return 0; } @@ -187,28 +189,31 @@ void serial_setbrg (void) static void pl01x_putc (int portnum, char c) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); + /* Wait until there is space in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) + while (readl(&regs->fr) & UART_PL01x_FR_TXFF) WATCHDOG_RESET(); /* Send the character */ - IO_WRITE (port[portnum] + UART_PL01x_DR, c); + writel(c, &regs->dr); } static int pl01x_getc (int portnum) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); unsigned int data; /* Wait until there is data in the FIFO */ - while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) + while (readl(&regs->fr) & UART_PL01x_FR_RXFE) WATCHDOG_RESET(); - data = IO_READ (port[portnum] + UART_PL01x_DR); + data = readl(&regs->dr); /* Check for an error flag */ if (data & 0xFFFFFF00) { /* Clear the error */ - IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + writel(0xFFFFFFFF, &regs->ecr); return -1; } @@ -217,7 +222,8 @@ static int pl01x_getc (int portnum) static int pl01x_tstc (int portnum) { + struct pl01x_regs *regs = pl01x_get_regs(portnum); + WATCHDOG_RESET(); - return !(IO_READ (port[portnum] + UART_PL01x_FR) & - UART_PL01x_FR_RXFE); + return !(readl(&regs->fr) & UART_PL01x_FR_RXFE); } diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index 5f20fdd..b670c24 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -29,10 +29,28 @@ * Definitions common to both PL010 & PL011 * */ -#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ -#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ -#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ -#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#ifndef __ASSEMBLY__ +/* + * We can use a combined structure for PL010 and PL011, because they overlap + * only in common registers. + */ +struct pl01x_regs { + u32 dr; /* 0x00 Data register */ + u32 ecr; /* 0x04 Error clear register (Write) */ + u32 pl010_lcrh; /* 0x08 Line control register, high byte */ + u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ + u32 pl010_lcrl; /* 0x10 Line control register, low byte */ + u32 pl010_cr; /* 0x14 Control register */ + u32 fr; /* 0x18 Flag register (Read only) */ + u32 reserved; + u32 ilpr; /* 0x20 IrDA low-power counter register */ + u32 pl011_ibrd; /* 0x24 Integer baud rate register */ + u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ + u32 pl011_lcrh; /* 0x2C Line control register */ + u32 pl011_cr; /* 0x30 Control register */ +}; +#endif #define UART_PL01x_RSR_OE 0x08 #define UART_PL01x_RSR_BE 0x04 @@ -50,14 +68,6 @@ * PL010 definitions * */ -#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ -#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ -#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ -#define UART_PL010_CR 0x14 /* Control register. */ -#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ -#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ -#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ - #define UART_PL010_CR_LPE (1 << 7) #define UART_PL010_CR_RTIE (1 << 6) #define UART_PL010_CR_TIE (1 << 5) @@ -93,13 +103,6 @@ * PL011 definitions * */ -#define UART_PL011_IBRD 0x24 -#define UART_PL011_FBRD 0x28 -#define UART_PL011_LCRH 0x2C -#define UART_PL011_CR 0x30 -#define UART_PL011_IMSC 0x38 -#define UART_PL011_PERIPH_ID0 0xFE0 - #define UART_PL011_LCRH_SPS (1 << 7) #define UART_PL011_LCRH_WLEN_8 (3 << 5) #define UART_PL011_LCRH_WLEN_7 (2 << 5) -- 1.7.0

2 1

[U-Boot] [PATCH] add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fns
by Wolfgang Wegner 30 Nov '10

30 Nov '10

Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner(a)astro-kom.de> --- All other FPGA drivers already support such an abort function - it seems Spartan3 serial load was a bit neglected (only discovered this because it messed up things on my board after a failed FPGA load). drivers/fpga/spartan3.c | 6 ++++++ include/spartan3.h | 1 + 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 7a89b56..1dd6f26 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -366,6 +366,8 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) CONFIG_FPGA_DELAY (); if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); + if (*fn->abort) + (*fn->abort) (cookie); return FPGA_FAIL; } } while (!(*fn->init) (cookie)); @@ -380,6 +382,8 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) CONFIG_FPGA_DELAY (); if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); + if (*fn->abort) + (*fn->abort) (cookie); return FPGA_FAIL; } } while ((*fn->init) (cookie)); @@ -394,6 +398,8 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) while DONE is low (inactive) */ if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { puts ("** CRC error during FPGA load.\n"); + if (*fn->abort) + (*fn->abort) (cookie); return (FPGA_FAIL); } val = data [bytecount ++]; diff --git a/include/spartan3.h b/include/spartan3.h index d5a589d..0f0b400 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -58,6 +58,7 @@ typedef struct { Xilinx_wr_fn wr; Xilinx_post_fn post; Xilinx_bwr_fn bwr; /* block write function */ + Xilinx_abort_fn abort; } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes -- 1.5.6.5

2 1

[U-Boot] [PATCH v2] powerpc/85xx: Add support for booting from NAND on MPC8572DS
by Kumar Gala 30 Nov '10

30 Nov '10

Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing <b24347(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Removed CONFIG_SYS_SPL as its not used and copied for older code board/freescale/mpc8572ds/config.mk | 6 + board/freescale/mpc8572ds/tlb.c | 14 +++- boards.cfg | 1 + include/configs/MPC8572DS.h | 115 ++++++++++++++++++--- nand_spl/board/freescale/mpc8572ds/Makefile | 133 ++++++++++++++++++++++++ nand_spl/board/freescale/mpc8572ds/nand_boot.c | 82 +++++++++++++++ 6 files changed, 335 insertions(+), 16 deletions(-) create mode 100644 nand_spl/board/freescale/mpc8572ds/Makefile create mode 100644 nand_spl/board/freescale/mpc8572ds/nand_boot.c diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 5413921..6cea41c 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -23,4 +23,10 @@ # # mpc8572ds board # +ifndef NAND_SPL +ifeq ($(CONFIG_NAND), y) +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +endif +endif + RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 6a2a0b5..575bdb5 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. @@ -85,6 +85,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, + CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 2209676..a994c8a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -472,6 +472,7 @@ MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freesca MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT +MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011 P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 1ee95ae..9d2e209 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -33,6 +33,25 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_NAND +#define CONFIG_NAND_U_BOOT +#define CONFIG_RAMBOOT_NAND +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else +#define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -41,10 +60,6 @@ #define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -81,10 +96,21 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ @@ -93,6 +119,12 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 @@ -177,8 +209,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 @@ -193,7 +228,12 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#else +#undef CONFIG_SYS_RAMBOOT +#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -246,6 +286,8 @@ #define PIXIS_VWATCH 0x24 /* Watchdog Register */ #define PIXIS_LED 0x25 /* LED Register */ +#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ + /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ @@ -277,12 +319,22 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ @@ -293,6 +345,17 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -308,9 +371,17 @@ | OR_FCM_TRLX \ | OR_FCM_EHTR) +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ - +#endif #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ @@ -341,6 +412,9 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -546,14 +620,25 @@ /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024)\ + + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif + #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile new file mode 100644 index 0000000..e2181e9 --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -0,0 +1,133 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# Copyright 2009-2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8572ds/nand_boot.c b/nand_spl/board/freescale/mpc8572ds/nand_boot.c new file mode 100644 index 0000000..7ca4d4d --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/nand_boot.c @@ -0,0 +1,82 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> + +u32 sysclk_tbl[] = { + 33333000, 39999600, 49999500, 66666000, + 83332500, 99999000, 133332000, 166665000 +}; + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, bus_clk, sys_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + /* for FPGA */ + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); +#else +#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined +#endif + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} -- 1.7.2.3

2 2

[U-Boot] [PATCH v2] hwconfig: Fix dummy initialization of {board, cpu}_hwconfig
by Kumar Gala 30 Nov '10

30 Nov '10

Since board_hwconfig & cpu_hwconfig are defined as weak and dont have a default value they will get put into the BSS if they aren't defined elsewhere. This is problematic as we try to utilize hwconfig before we've relocated and thus BSS isn't setup. Instead of giving dummy values in the board files that utilize this feature, we can just initialize the variables to an empty string and thus move them out of the BSS if they aren't defined elsewhere. Also made board_hwconfig & cpu_hwconfig arrays to reduce size associated with string pointers vs arrays. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Incorporate Jocke about use of arrays vs pointers board/freescale/mpc8641hpcn/mpc8641hpcn.c | 3 --- board/freescale/p2020ds/p2020ds.c | 3 --- common/hwconfig.c | 4 ++-- 3 files changed, 2 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 812111d..882ff0b 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -60,9 +60,6 @@ int checkboard(void) return 0; } -const char *board_hwconfig = "foo:bar=baz"; -const char *cpu_hwconfig = "foo:bar=baz"; - phys_size_t initdram(int board_type) { diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b507677..b05ef98 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -69,9 +69,6 @@ int checkboard(void) return 0; } -const char *board_hwconfig = "foo:bar=baz"; -const char *cpu_hwconfig = "foo:bar=baz"; - phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; diff --git a/common/hwconfig.c b/common/hwconfig.c index 3c9759f..752bfc3 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -68,8 +68,8 @@ next: return NULL; } -const char *cpu_hwconfig __attribute__((weak)); -const char *board_hwconfig __attribute__((weak)); +const char cpu_hwconfig[] __attribute__((weak)) = ""; +const char board_hwconfig[] __attribute__((weak)) = ""; #define HWCONFIG_PRE_RELOC_BUF_SIZE 128 -- 1.7.2.3

2 1

[U-Boot] DA850 USB support
by Paulraj, Sandeep 30 Nov '10

30 Nov '10

Looks like this patch got missed http://patchwork.ozlabs.org/patch/71817/ It adds USB support for DA850 --Sandeep

1 0

[U-Boot] Please pull u-boot-ti/next
by s-paulraj＠ti.com 30 Nov '10

30 Nov '10

The following changes since commit c87f6457bb9cb465e9630b00b4c824847a62c6c5: Mike Frysinger (1): ext2: constify file/dir names are available in the git repository at: git://git.denx.de/u-boot-ti.git next Stefano Babic (3): da850: Enable SPI Flash Davinci 8xx: Move common functions to share code Davinci: add support for the ea20 board Sudhakar Rajashekhara (2): da8xx: Add cpu_is_da8xx macros da850: Add RMII support for EMAC Sughosh Ganu (3): Move and rename common headers from under Remove board_init_f function from nand_boot.c Add board support for hawkboard MAINTAINERS | 6 + .../arm/include/asm/arch-davinci/davinci_misc.h | 15 ++ arch/arm/include/asm/arch-davinci/hardware.h | 37 ++++- board/davinci/common/Makefile | 2 +- board/davinci/common/davinci_pinmux.c | 105 ++++++++++ board/davinci/common/misc.c | 99 ++++------ board/davinci/da8xxevm/Makefile | 2 +- board/davinci/da8xxevm/common.c | 55 ------ board/davinci/da8xxevm/common.h | 30 --- board/davinci/da8xxevm/da830evm.c | 3 +- board/davinci/da8xxevm/da850evm.c | 115 +++++++++++- board/davinci/da8xxevm/hawkboard.c | 68 +++++++ board/davinci/da8xxevm/hawkboard_nand_spl.c | 157 +++++++++++++++ board/davinci/dm355evm/dm355evm.c | 2 +- board/davinci/dm355leopard/dm355leopard.c | 2 +- board/davinci/dm365evm/dm365evm.c | 2 +- board/davinci/dvevm/dvevm.c | 2 +- board/davinci/ea20/Makefile | 53 +++++ board/davinci/ea20/ea20.c | 196 +++++++++++++++++++ board/davinci/schmoogie/schmoogie.c | 2 +- board/davinci/sffsdr/sffsdr.c | 2 +- board/davinci/sonata/sonata.c | 2 +- board/samsung/smdk6400/smdk6400_nand_spl.c | 37 ++++ boards.cfg | 4 + doc/README.hawkboard | 93 +++++++++ drivers/net/davinci_emac.c | 41 ++++- include/configs/da850evm.h | 29 +++ include/configs/ea20.h | 192 ++++++++++++++++++ include/configs/hawkboard.h | 206 ++++++++++++++++++++ nand_spl/board/davinci/da8xxevm/Makefile | 141 +++++++++++++ nand_spl/board/davinci/da8xxevm/u-boot.lds | 75 +++++++ nand_spl/board/samsung/smdk6400/Makefile | 6 +- nand_spl/nand_boot.c | 9 +- 33 files changed, 1615 insertions(+), 175 deletions(-) rename board/davinci/common/misc.h => arch/arm/include/asm/arch-davinci/davinci_misc.h (80%) create mode 100644 board/davinci/common/davinci_pinmux.c delete mode 100644 board/davinci/da8xxevm/common.c delete mode 100644 board/davinci/da8xxevm/common.h create mode 100644 board/davinci/da8xxevm/hawkboard.c create mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c create mode 100644 board/davinci/ea20/Makefile create mode 100644 board/davinci/ea20/ea20.c create mode 100644 board/samsung/smdk6400/smdk6400_nand_spl.c create mode 100644 doc/README.hawkboard create mode 100644 include/configs/ea20.h create mode 100644 include/configs/hawkboard.h create mode 100644 nand_spl/board/davinci/da8xxevm/Makefile create mode 100644 nand_spl/board/davinci/da8xxevm/u-boot.lds

2 1

[U-Boot] Please pull u-boot-samsung/master
by Minkyu Kang 30 Nov '10

30 Nov '10

Please pull u-boot-samsung/master. Thanks. The following changes since commit 464ce9489b848f9dfde74da5715b6d1b5db46a5e: Minkyu Kang (1): Merge branch 'master' of git://git.denx.de/u-boot-arm are available in the git repository at: git://git.denx.de/u-boot-samsung master Minkyu Kang (3): S5P: smdkc100: fix for relocation S5P: goni: fix for relocation ARMV7: S5P: timer: get the count_value from register when call udelay arch/arm/cpu/armv7/s5p-common/timer.c | 18 +++++++++--------- board/samsung/goni/goni.c | 10 ++++++++-- board/samsung/smdkc100/smdkc100.c | 10 +++++++--- include/configs/s5p_goni.h | 2 ++ include/configs/smdkc100.h | 2 ++ 5 files changed, 28 insertions(+), 14 deletions(-)

2 1

[U-Boot] Pull request: u-boot-sh
by Nobuhiro Iwamatsu 30 Nov '10

30 Nov '10

Hi, Wolfgang, Please pull from u-boot-sh.git. The following changes since commit d0d2271f8c62e830ec65fb069b6d12dd708e3e2f: Prepare v2010.12-rc2 (2010-11-28 19:48:11 +0100) are available in the git repository at: ssh+git://git.denx.de/u-boot-sh.git master Nobuhiro Iwamatsu (2): sh: Fix build in start.S sh: r7780mp: Remove CONFIG_DRIVER_NE2000 from config arch/sh/cpu/sh2/start.S | 8 ++++---- arch/sh/cpu/sh3/start.S | 8 ++++---- arch/sh/cpu/sh4/start.S | 10 +++++----- include/configs/r7780mp.h | 1 - 4 files changed, 13 insertions(+), 14 deletions(-) -- Nobuhiro Iwamatsu iwamatsu at {nigauri.org / debian.org} GPG ID: 40AD1FA6

2 1

[U-Boot] Please pull u-boot-ti/master
by s-paulraj＠ti.com 30 Nov '10

30 Nov '10

The following changes since commit d0d2271f8c62e830ec65fb069b6d12dd708e3e2f: Wolfgang Denk (1): Prepare v2010.12-rc2 are available in the git repository at: git://git.denx.de/u-boot-ti.git master Dirk Behme (4): OMAP4: SDP4430: Disable CMD_NFS OMAP3: SDP3430: Fix ARM relocation support OMAP3: Zoom1: Fix ARM relocation support OMAP3: Zoom2: Fix ARM relocation support Enric Balletbo i Serra (1): ARMV7: OMAP3: Fix build failure for igep0030 machine Sanjeev Premi (1): omap3evm: Use GENERATED_GBL_DATA_SIZE Vaibhav Hiremath (3): AM3517:Fix for ARM Relocation support AM3517:Build FIX: undef CONFIG_CMD_NFS support AM3517:EMIF4: fix SDRAM size to 256Mb arch/arm/cpu/armv7/omap3/emif4.c | 5 +++-- board/logicpd/am3517evm/config.mk | 2 +- board/logicpd/zoom1/config.mk | 2 +- board/logicpd/zoom2/config.mk | 2 +- board/ti/sdp3430/config.mk | 2 +- include/configs/am3517_evm.h | 7 +++++++ include/configs/igep0030.h | 1 + include/configs/omap3_evm.h | 6 +++++- include/configs/omap3_sdp3430.h | 6 ++++++ include/configs/omap3_zoom1.h | 6 ++++++ include/configs/omap3_zoom2.h | 6 ++++++ include/configs/omap4_sdp4430.h | 1 + 12 files changed, 39 insertions(+), 7 deletions(-)

2 1

[U-Boot] Please pull u-boot-ti/master
by s-paulraj＠ti.com 30 Nov '10

30 Nov '10

Wolfgang, Albert, Sorry I don't know who will accept my pull request so addressing both of you. Please pull u-boot-ti/master. Regards, Sandeep The following changes since commit d0d2271f8c62e830ec65fb069b6d12dd708e3e2f: Wolfgang Denk (1): Prepare v2010.12-rc2 are available in the git repository at: git://git.denx.de/u-boot-ti.git master Dirk Behme (1): OMAP4: SDP4430: Disable CMD_NFS Enric Balletbo i Serra (1): ARMV7: OMAP3: Fix build failure for igep0030 machine Sanjeev Premi (1): omap3evm: Use GENERATED_GBL_DATA_SIZE Vaibhav Hiremath (3): AM3517:Fix for ARM Relocation support AM3517:Build FIX: undef CONFIG_CMD_NFS support AM3517:EMIF4: fix SDRAM size to 256Mb arch/arm/cpu/armv7/omap3/emif4.c | 5 +++-- board/logicpd/am3517evm/config.mk | 2 +- include/configs/am3517_evm.h | 7 +++++++ include/configs/igep0030.h | 1 + include/configs/omap3_evm.h | 6 +++++- include/configs/omap4_sdp4430.h | 1 + 6 files changed, 18 insertions(+), 4 deletions(-)

2 1