October 2010 - U-Boot

[U-Boot] [PATCH 1/2] Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate
by Tanmay Upadhyay 15 Oct '10

15 Oct '10

This patch modifies existing OpenRD-Base support to deal with all the three OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate). Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> --- MAKEALL | 2 + board/Marvell/openrd/Makefile | 56 ++++++++++ board/Marvell/openrd/config.mk | 33 ++++++ board/Marvell/openrd/kwbimage.cfg | 168 ++++++++++++++++++++++++++++++ board/Marvell/openrd/openrd.c | 169 +++++++++++++++++++++++++++++++ board/Marvell/openrd/openrd.h | 50 +++++++++ board/Marvell/openrd_base/Makefile | 56 ---------- board/Marvell/openrd_base/config.mk | 33 ------ board/Marvell/openrd_base/kwbimage.cfg | 168 ------------------------------ board/Marvell/openrd_base/openrd_base.c | 149 --------------------------- board/Marvell/openrd_base/openrd_base.h | 46 --------- boards.cfg | 4 +- include/configs/openrd.h | 113 +++++++++++++++++++++ include/configs/openrd_base.h | 92 +++-------------- include/configs/openrd_client.h | 50 +++++++++ include/configs/openrd_ultimate.h | 50 +++++++++ 16 files changed, 708 insertions(+), 531 deletions(-) create mode 100644 board/Marvell/openrd/Makefile create mode 100644 board/Marvell/openrd/config.mk create mode 100644 board/Marvell/openrd/kwbimage.cfg create mode 100644 board/Marvell/openrd/openrd.c create mode 100644 board/Marvell/openrd/openrd.h delete mode 100644 board/Marvell/openrd_base/Makefile delete mode 100644 board/Marvell/openrd_base/config.mk delete mode 100644 board/Marvell/openrd_base/kwbimage.cfg delete mode 100644 board/Marvell/openrd_base/openrd_base.c delete mode 100644 board/Marvell/openrd_base/openrd_base.h create mode 100644 include/configs/openrd.h create mode 100644 include/configs/openrd_client.h create mode 100644 include/configs/openrd_ultimate.h diff --git a/MAKEALL b/MAKEALL index 1b506d6..11fbf48 100755 --- a/MAKEALL +++ b/MAKEALL @@ -431,6 +431,8 @@ LIST_ARM9=" \ omap5912osk \ omap730p2 \ openrd_base \ + openrd_client \ + openrd_ultimate \ rd6281a \ sbc2410x \ scb9328 \ diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile new file mode 100644 index 0000000..aad05d8 --- /dev/null +++ b/board/Marvell/openrd/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2009 +# Net Insight <www.netinsight.net> +# Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> +# +# Based on sheevaplug: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := openrd.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/openrd/config.mk b/board/Marvell/openrd/config.mk new file mode 100644 index 0000000..8ae355e --- /dev/null +++ b/board/Marvell/openrd/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2009 +# Net Insight <www.netinsight.net> +# Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> +# +# Based on sheevaplug: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg new file mode 100644 index 0000000..757eb28 --- /dev/null +++ b/board/Marvell/openrd/kwbimage.cfg @@ -0,0 +1,168 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strength reduced +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) + +DATA 0xFFD0149C 0x0000E40f # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c new file mode 100644 index 0000000..3953282 --- /dev/null +++ b/board/Marvell/openrd/openrd.c @@ -0,0 +1,169 @@ +/* + * Modified Simon's work to deal with all the three variants of + * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Modified-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> + * + * Based on sheevaplug.c: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "openrd.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(OPENRD_OE_VAL_LOW, + OPENRD_OE_VAL_HIGH, + OPENRD_OE_LOW, OPENRD_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, /* Alt UART1_TXD */ + MPP14_SD_D0, /* Alt UART1_RXD */ + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_TSMP9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, /* UART1 / SD sel */ + MPP35_TDM_CH0_TX_QL, + MPP36_TDM_SPI_CS1, + MPP37_TDM_CH2_TX_QL, + MPP38_TDM_CH2_RX_QL, + MPP39_AUDIO_I2SBCLK, + MPP40_AUDIO_I2SDO, + MPP41_AUDIO_I2SLRC, + MPP42_AUDIO_I2SMCLK, + MPP43_AUDIO_I2SDI, + MPP44_AUDIO_EXTCLK, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_TDM_CH0_RX_QL, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_OPENRD; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116/MV88E1121 PHY */ +void mv_phy_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, PGADR_REG, 2); + miiphy_read(name, devadr, MAC_CTRL_REG, &reg); + reg |= (RGMII_RXTM_CTRL | RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MAC_CTRL_REG, reg); + miiphy_write(name, devadr, PGADR_REG, 0); + + /* reset the phy */ + if (!miiphy_reset(name, devadr)) + printf("%s Initialized on %s\n", PHY_NO, name); +} + +void reset_phy(void) +{ + mv_phy_init("egiga0"); + +#ifdef OPENRD_CLIENT + /* Kirkwood ethernet driver is written with the assumption that in case + * of multiple PHYs, their addresses are consecutive. But unfortunately + * in case of OpenRD-Client, PHY addresses are not consecutive.*/ + miiphy_write("egiga1", 0xEE, 0xEE, 24); +#endif + +#if defined(OPENRD_CLIENT) || defined(OPENRD_ULTIMATE) + /* configure and initialize both PHY's */ + mv_phy_init("egiga1"); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h new file mode 100644 index 0000000..2fe2e19 --- /dev/null +++ b/board/Marvell/openrd/openrd.h @@ -0,0 +1,50 @@ +/* + * Modified Simon's work to deal with all the three variants of + * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Modified-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __OPENRD_H +#define __OPENRD_H + +#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ +#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ +#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ +#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ + +/* PHY related */ +#define MAC_CTRL_REG 21 +#define PGADR_REG 22 +#define RGMII_TXTM_CTRL (1 << 4) +#define RGMII_RXTM_CTRL (1 << 5) + +#endif /* __OPENRD_H */ diff --git a/board/Marvell/openrd_base/Makefile b/board/Marvell/openrd_base/Makefile deleted file mode 100644 index 3ef0b9b..0000000 --- a/board/Marvell/openrd_base/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2009 -# Net Insight <www.netinsight.net> -# Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> -# -# Based on sheevaplug: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := openrd_base.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/Marvell/openrd_base/config.mk b/board/Marvell/openrd_base/config.mk deleted file mode 100644 index 8ae355e..0000000 --- a/board/Marvell/openrd_base/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2009 -# Net Insight <www.netinsight.net> -# Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> -# -# Based on sheevaplug: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -TEXT_BASE = 0x00600000 - -# Kirkwood Boot Image configuration file -KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/openrd_base/kwbimage.cfg b/board/Marvell/openrd_base/kwbimage.cfg deleted file mode 100644 index 757eb28..0000000 --- a/board/Marvell/openrd_base/kwbimage.cfg +++ /dev/null @@ -1,168 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -# MA 02110-1301 USA -# -# Refer docs/README.kwimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand -NAND_ECC_MODE default -NAND_PAGE_SIZE 0x0800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1b1b1b9b - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register -# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x37543000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x000000cc # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs1width=x8 -# bit7-6: 11, Cs1size=1Gb -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000C52 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000042 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strength reduced -# bit2: 0, DDR ODT control lsd (disabled) -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, (disabled) -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb -DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 - -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 -# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 -# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. -# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) - -DATA 0xFFD0149C 0x0000E40f # CPU ODT Control -# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 -# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm -# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm -# bit14: 1, M_STARTBURST_IN ODT: Enabled -# bit15: 1, DDR IO ODT Unit: Use ODT block -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c deleted file mode 100644 index d006b2d..0000000 --- a/board/Marvell/openrd_base/openrd_base.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> - * - * Based on sheevaplug.c: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <miiphy.h> -#include <asm/arch/kirkwood.h> -#include <asm/arch/mpp.h> -#include "openrd_base.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* - * default gpio configuration - * There are maximum 64 gpios controlled through 2 sets of registers - * the below configuration configures mainly initial LED status - */ - kw_config_gpio(OPENRD_OE_VAL_LOW, - OPENRD_OE_VAL_HIGH, - OPENRD_OE_LOW, OPENRD_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_SD_CLK, - MPP13_SD_CMD, /* Alt UART1_TXD */ - MPP14_SD_D0, /* Alt UART1_RXD */ - MPP15_SD_D1, - MPP16_SD_D2, - MPP17_SD_D3, - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GPIO, - MPP29_TSMP9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GPIO, /* UART1 / SD sel */ - MPP35_TDM_CH0_TX_QL, - MPP36_TDM_SPI_CS1, - MPP37_TDM_CH2_TX_QL, - MPP38_TDM_CH2_RX_QL, - MPP39_AUDIO_I2SBCLK, - MPP40_AUDIO_I2SDO, - MPP41_AUDIO_I2SLRC, - MPP42_AUDIO_I2SMCLK, - MPP43_AUDIO_I2SDI, - MPP44_AUDIO_EXTCLK, - MPP45_TDM_PCLK, - MPP46_TDM_FS, - MPP47_TDM_DRX, - MPP48_TDM_DTX, - MPP49_TDM_CH0_RX_QL, - 0 - }; - - kirkwood_mpp_conf(kwmpp_config); - - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h deleted file mode 100644 index f3daf17..0000000 --- a/board/Marvell/openrd_base/openrd_base.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __OPENRD_BASE_H -#define __OPENRD_BASE_H - -#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ -#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ -#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ -#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __OPENRD_BASE_H */ diff --git a/boards.cfg b/boards.cfg index 62ffa42..35a38c3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -246,7 +246,9 @@ da830evm arm arm926ejs da8xxevm davinci davinci da850evm arm arm926ejs da8xxevm davinci davinci guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood -openrd_base arm arm926ejs - Marvell kirkwood +openrd_base arm arm926ejs openrd Marvell kirkwood +openrd_client arm arm926ejs openrd Marvell kirkwood +openrd_ultimate arm arm926ejs openrd Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 diff --git a/include/configs/openrd.h b/include/configs/openrd.h new file mode 100644 index 0000000..c4dcad6 --- /dev/null +++ b/include/configs/openrd.h @@ -0,0 +1,113 @@ +/* + * Modified openrd_base.h to deal with all the three variants of + * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Modified-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_H +#define _CONFIG_OPENRD_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_IDE + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#endif /* _CONFIG_OPENRD_H */ diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index cfdd09c..4f9ea80 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -1,4 +1,10 @@ /* + * Modified Simon's work to deal with all the three variants of + * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Modified-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * * (C) Copyright 2009 * Net Insight <www.netinsight.net> * Written-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> @@ -30,91 +36,21 @@ #ifndef _CONFIG_OPENRD_BASE_H #define _CONFIG_OPENRD_BASE_H -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nOpenRD_base" - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_MACH_OPENRD_BASE /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include <config_cmd_default.h> -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_IDE - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#else -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x60000 -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" +#include <configs/openrd.h> -#define MTDIDS_DEFAULT "nand0=nand_mtd" -#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ - "0x400000@0x100000(uImage),"\ - "0x1fb00000@0x500000(rootfs)" +#define CONFIG_IDENT_STRING "\nOpenRD-Base" -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ - "mtdids="MTDIDS_DEFAULT"\0" \ - "mtdparts="MTDPARTS_DEFAULT"\0" +/* Machine type */ +#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_BASE /* * Ethernet Driver configuration */ #ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0x8 +/* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 0} +#define CONFIG_PHY_BASE_ADR 0x8 +#define PHY_NO "88E1116" #endif /* CONFIG_CMD_NET */ -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/openrd_client.h b/include/configs/openrd_client.h new file mode 100644 index 0000000..98d516a --- /dev/null +++ b/include/configs/openrd_client.h @@ -0,0 +1,50 @@ +/* + * Created to deal with all the three variants of OpenRD boards + * (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Written-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_CLIENT_H +#define _CONFIG_OPENRD_CLIENT_H + +#include <configs/openrd.h> + +#define CONFIG_IDENT_STRING "\nOpenRD-Client" + +/* Machine type */ +#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_CLIENT + +/* board/openrd/openrd.c needs this */ +#define OPENRD_CLIENT + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +/* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 1} +#define CONFIG_PHY_BASE_ADR 0x8 +#define PHY_NO "88E1116" +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_OPENRD_CLIENT_H */ diff --git a/include/configs/openrd_ultimate.h b/include/configs/openrd_ultimate.h new file mode 100644 index 0000000..4d20717 --- /dev/null +++ b/include/configs/openrd_ultimate.h @@ -0,0 +1,50 @@ +/* + * Created to deal with all the three variants of OpenRD boards + * (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate) + * + * eInfochips <www.einfochips.com> + * Written-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_ULTIMATE_H +#define _CONFIG_OPENRD_ULTIMATE_H + +#include <configs/openrd.h> + +#define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" + +/* Machine type */ +#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_ULTIMATE + +/* board/openrd/openrd.c needs this */ +#define OPENRD_ULTIMATE + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +/* enable port 0 only */ +#define CONFIG_MVGBE_PORTS {1, 1} +#define CONFIG_PHY_BASE_ADR 0x0 +#define PHY_NO "88E1121" +#endif /* CONFIG_CMD_NET */ + +#endif /* _CONFIG_OPENRD_ULTIMATE_H */ -- 1.6.6.1

2 1

[U-Boot] Fwd: Help with replacing u-boot and kernel on a released HW...
by Naresh Mehta 15 Oct '10

15 Oct '10

Hi List, I am not able to attach the files. But they haven't been changed from the original versions so hopefully, I still can be helped! BR; Naresh ---------- Forwarded message ---------- From: <u-boot-owner(a)lists.denx.de> Date: Wed, Oct 13, 2010 at 11:40 AM Subject: Help with replacing u-boot and kernel on a released HW... To: nareshtechs(a)gmail.com Message rejected. No base64 encoded MIME text parts allowed. ---------- Forwarded message ---------- From: Naresh Mehta <nareshtechs(a)gmail.com> To: u-boot(a)lists.denx.de Date: Wed, 13 Oct 2010 11:40:43 +0200 Subject: Help with replacing u-boot and kernel on a released HW... Hi List, I have a monta-vista linux based smartphone (Garmin Asus G60). It runs u-boot and kernel 2.6.21. Since it is a released HW and from the u-boot code, I can see that there are no ways to stop the existing u-boot to boot the default kernel installed. There is a possibility to do a region update from the memory card on boot-up. Looking at the code, there is also a possibility to do a recover region i.e. according to the comment it says, download Garmin region from USB. Both the above methods basically run the same command "tffs_load 3 0x80007FC0;bootm 0x80007FC0". The tffs_load is attached in the email. I have tried to put a bootable .bin file with a modified u-boot and kernel but it does not seem to get loaded. I have tried loading the kernel at 0x80007FC0, 0x80000000 and 0x0. I am out of ideas on how I could get the modified u-boot and kernel on the device. Any pointers would be greatly appreciated. Just to be clear on how I create the bootable .bin: - Compile u-boot for montana board (used for this device) - Compile the kernel with montana_dev_defconfig and some kernel debug options enabled - Generate a bootable image from vmlinux with different load address configurations as described above - cat u-boot.bin and the bootable image to form a .bin file - Place the file on the sdcard and re-boot. I am now out of ideas. BTW, the HW consists of OMAP2430 and associated components with an Ericsson U360 modem. I am attaching the montana.h file for further reference which will give some overview of the G60 HW. My final goal is to load Android on this device but for that I need new u-boot and modified kernel to get loaded first. Cheers, -- BR; Naresh visit me at: http://www.naresh.se/ -- BR; Naresh visit me at: http://www.naresh.se/

2 1

[U-Boot] [PATCH] Ensure gd->ram_size end stays on 4k page boundary when 'hiding' RAM
by Gray Remlin 15 Oct '10

15 Oct '10

Signed-off-by: Gray Remlin <g_remlin(a)rocketmail.com> --- arch/arm/lib/board.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 22bd2c9..c1b21f5 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -531,8 +531,9 @@ void board_init_f (ulong bootflag) * arch/powerpc with bootwrapper support, that recalculate the * memory size from the SDRAM controller setup will have to * get fixed. + * Ensure gd->ram_size end is still on a 4k page boundary. */ - gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; + gd->ram_size -= ((CONFIG_SYS_MEM_TOP_HIDE + 0xFFF) & ~(0xFFF)); #endif addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; --

2 1

[U-Boot] [PATCH] Support sending DHCP client options
by Gray Remlin 15 Oct '10

15 Oct '10

Signed-off-by: Gray Remlin <g_remlin(a)rocketmail.com> --- common/cmd_nvedit.c | 3 ++ net/bootp.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 0 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 3d30c32..2094e8e 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -224,6 +224,9 @@ int _do_env_set (int flag, int argc, char * const argv[]) if (ep) { /* variable exists */ #ifndef CONFIG_ENV_OVERWRITE if ((strcmp (name, "serial#") == 0) || +#if defined(CONFIG_BOOTP_OPTIONS) + (strcmp(name, "dhcp_vendor-class-identifier") == 0) || +#endif /* CONFIG_BOOTP_OPTIONS */ ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp (ep->data,MK_STR(CONFIG_ETHADDR)) != 0) diff --git a/net/bootp.c b/net/bootp.c index 1289e3b..9e687b0 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -68,6 +68,54 @@ extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ #endif +#if defined(CONFIG_BOOTP_OPTIONS) /* check environment for dhcp client options */ + +/* + * The vendor-specifiable options should not be changeable + * unless CONFIG_ENV_OVERWRITE has been defined, however + * user-specifiable options should be changeable regardless + */ +u8 dhcp_options_prep(u8 **ep) +{ + u8 *e = *ep; + char *ptr; + + debug("DHCP Client options start\n"); + + /* vendor-specifiable identification string */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + debug("dhcp_vendor-class-identifier=%s\n",ptr); + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + /* user-specifiable identification string */ + if ((ptr = getenv("dhcp_dhcp-client-identifier"))) { + debug("dhcp_dhcp-client-identifier=%s\n",ptr); + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + /* user-specifiable identification string */ + if ((ptr = getenv("dhcp_user-class"))) { + debug("dhcp_user-class=%s\n",ptr); + *e++ = 77; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + debug("DHCP Client options end\n"); + *ep = e; + return e; +} + +#endif /* CONFIG_BOOTP_OPTIONS */ + #endif static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) @@ -412,6 +460,10 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R } #endif +#if defined(CONFIG_BOOTP_OPTIONS) + dhcp_options_prep (&e); +#endif + #if defined(CONFIG_BOOTP_VENDOREX) if ((x = dhcp_vendorex_prep (e))) return x - start; --

1 0

[U-Boot] [PATCH] Fix potential empty Parameter Request List
by Gray Remlin 15 Oct '10

15 Oct '10

Signed-off-by: Gray Remlin <g_remlin(a)rocketmail.com> --- net/bootp.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-) diff --git a/net/bootp.c b/net/bootp.c index e679f8b..1289e3b 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -417,8 +417,21 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R return x - start; #endif +/* + * RFC2132: An empty Parameter Request List is not legitimate, + * it must have at minimum one request. + */ +#if defined(CONFIG_BOOTP_SUBNETMASK) || \ + defined(CONFIG_BOOTP_TIMEOFFSET) || \ + defined(CONFIG_BOOTP_GATEWAY) || \ + defined(CONFIG_BOOTP_DNS) || \ + defined(CONFIG_BOOTP_HOSTNAME) || \ + defined(CONFIG_BOOTP_BOOTFILESIZE) || \ + defined(CONFIG_BOOTP_BOOTPATH) || \ + defined(CONFIG_BOOTP_NISDOMAIN) || \ + defined(CONFIG_BOOTP_NTPSERVER) *e++ = 55; /* Parameter Request List */ - cnt = e++; /* Pointer to count of requested items */ + cnt = e++; /* Pointer to count of requested items */ *cnt = 0; #if defined(CONFIG_BOOTP_SUBNETMASK) *e++ = 1; /* Subnet Mask */ @@ -456,6 +469,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R *e++ = 42; *cnt += 1; #endif +#endif *e++ = 255; /* End of the list */ /* Pad to minimal length */ --

1 0

[U-Boot] [PATCH 1/1] IMX: rename mx51 to mx5
by Jason Liu 15 Oct '10

15 Oct '10

Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu <r64343(a)freescale.com> --- arch/arm/cpu/armv7/{mx51 => mx5}/Makefile | 0 arch/arm/cpu/armv7/{mx51 => mx5}/clock.c | 44 ++++++++++---------- arch/arm/cpu/armv7/{mx51 => mx5}/iomux.c | 4 +- arch/arm/cpu/armv7/{mx51 => mx5}/lowlevel_init.S | 0 arch/arm/cpu/armv7/{mx51 => mx5}/soc.c | 24 +++++----- arch/arm/cpu/armv7/{mx51 => mx5}/speed.c | 0 arch/arm/cpu/armv7/{mx51 => mx5}/timer.c | 10 ++-- arch/arm/cpu/armv7/{mx51 => mx5}/u-boot.lds | 0 .../asm/{arch-mx51 => arch-mx5}/asm-offsets.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/clock.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/crm_regs.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/imx-regs.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/iomux.h | 10 ++-- .../mx51_pins.h => arch-mx5/mx5x_pins.h} | 8 ++-- .../asm/{arch-mx51 => arch-mx5}/sys_proto.h | 3 +- board/freescale/mx51evk/mx51evk.c | 4 +- boards.cfg | 2 +- include/configs/mx51evk.h | 7 ++- 18 files changed, 59 insertions(+), 57 deletions(-) diff --git a/arch/arm/cpu/armv7/mx51/Makefile b/arch/arm/cpu/armv7/mx5/Makefile similarity index 100% rename from arch/arm/cpu/armv7/mx51/Makefile rename to arch/arm/cpu/armv7/mx5/Makefile diff --git a/arch/arm/cpu/armv7/mx51/clock.c b/arch/arm/cpu/armv7/mx5/clock.c old mode 100644 new mode 100755 similarity index 84% rename from arch/arm/cpu/armv7/mx51/clock.c rename to arch/arm/cpu/armv7/mx5/clock.c index a27227d..840ee92 --- a/arch/arm/cpu/armv7/mx51/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void) reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >> MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_HCLK_FREQ); return freq / (reg + 1); } @@ -84,14 +84,14 @@ static u32 get_periph_clk(void) reg = __raw_readl(&mxc_ccm->cbcdr); if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) - return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); + return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_HCLK_FREQ); reg = __raw_readl(&mxc_ccm->cbcmr); switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { case 0: - return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); + return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_HCLK_FREQ); case 1: - return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); + return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_HCLK_FREQ); default: return 0; } @@ -146,15 +146,15 @@ static u32 get_uart_clk(void) MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { case 0x0: freq = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ); + CONFIG_HCLK_FREQ); break; case 0x1: freq = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_MX51_HCLK_FREQ); + CONFIG_HCLK_FREQ); break; case 0x2: freq = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_MX51_HCLK_FREQ); + CONFIG_HCLK_FREQ); break; default: return 66500000; @@ -181,7 +181,7 @@ u32 get_lp_apm(void) u32 ccsr = __raw_readl(&mxc_ccm->ccsr); if (((ccsr >> 9) & 1) == 0) - ret_val = CONFIG_MX51_HCLK_FREQ; + ret_val = CONFIG_HCLK_FREQ; else ret_val = ((32768 * 1024)); @@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void) switch (clk_sel) { case 0: ret_val = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ) / + CONFIG_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); break; case 1: ret_val = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_MX51_HCLK_FREQ) / + CONFIG_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); break; case 2: ret_val = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_MX51_HCLK_FREQ) / + CONFIG_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1)); break; default: @@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return imx_get_cspiclk(); case MXC_FEC_CLK: return decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ); + CONFIG_HCLK_FREQ); default: break; } @@ -269,16 +269,16 @@ u32 imx_get_fecclk(void) /* * Dump some core clockes. */ -int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u32 freq; - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll1: %dMHz\n", freq / 1000000); - freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll2: %dMHz\n", freq / 1000000); - freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll3: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_HCLK_FREQ); + printf("pll1: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_HCLK_FREQ); + printf("pll2: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_HCLK_FREQ); + printf("pll3: %dMHz\n", freq / 1000000); printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); @@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] /***************************************************/ U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks, - "display mx51 clocks\n", + clockinfo, CONFIG_SYS_MAXARGS, 1, do_showclocks, + "display clocks\n", "" ); diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c similarity index 98% rename from arch/arm/cpu/armv7/mx51/iomux.c rename to arch/arm/cpu/armv7/mx5/iomux.c index 62b2954..43cfc69 100644 --- a/arch/arm/cpu/armv7/mx51/iomux.c +++ b/arch/arm/cpu/armv7/mx5/iomux.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx51_pins.h> +#include <asm/arch/mx5x_pins.h> #include <asm/arch/iomux.h> #include <asm/arch/sys_proto.h> diff --git a/arch/arm/cpu/armv7/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S similarity index 100% rename from arch/arm/cpu/armv7/mx51/lowlevel_init.S rename to arch/arm/cpu/armv7/mx5/lowlevel_init.S diff --git a/arch/arm/cpu/armv7/mx51/soc.c b/arch/arm/cpu/armv7/mx5/soc.c old mode 100644 new mode 100755 similarity index 82% rename from arch/arm/cpu/armv7/mx51/soc.c rename to arch/arm/cpu/armv7/mx5/soc.c index f22ebe9..f4c0bde --- a/arch/arm/cpu/armv7/mx51/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,26 +35,25 @@ u32 get_cpu_rev(void) { - int reg; - int system_rev; + int system_rev = CONFIG_CPU_TYPE << 8; + int reg = __raw_readl(ROM_SI_REV); - reg = __raw_readl(ROM_SI_REV); switch (reg) { case 0x02: - system_rev = 0x51000 | CHIP_REV_1_1; + system_rev |= CHIP_REV_1_1; break; case 0x10: if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) - system_rev = 0x51000 | CHIP_REV_2_5; + system_rev |= CHIP_REV_2_5; else - system_rev = 0x51000 | CHIP_REV_2_0; + system_rev |= CHIP_REV_2_0; break; case 0x20: - system_rev = 0x51000 | CHIP_REV_3_0; + system_rev |= CHIP_REV_3_0; break; return system_rev; default: - system_rev = 0x51000 | CHIP_REV_1_0; + system_rev |= CHIP_REV_1_0; break; } return system_rev; @@ -67,9 +66,10 @@ int print_cpuinfo(void) u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n", - (cpurev & 0xF0) >> 4, - (cpurev & 0x0F) >> 4, + printf("CPU: Freescale i.MX%d family rev%d.%d at %d MHz\n", + (cpurev & 0xFF00) >> 8, + (cpurev & 0x00F0) >> 4, + (cpurev & 0x000F) >> 4, mxc_get_clock(MXC_ARM_CLK) / 1000000); return 0; } diff --git a/arch/arm/cpu/armv7/mx51/speed.c b/arch/arm/cpu/armv7/mx5/speed.c similarity index 100% rename from arch/arm/cpu/armv7/mx51/speed.c rename to arch/arm/cpu/armv7/mx5/speed.c diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx5/timer.c old mode 100644 new mode 100755 similarity index 90% rename from arch/arm/cpu/armv7/mx51/timer.c rename to arch/arm/cpu/armv7/mx5/timer.c index 110edbf..100643d --- a/arch/arm/cpu/armv7/mx51/timer.c +++ b/arch/arm/cpu/armv7/mx5/timer.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -75,18 +75,18 @@ void reset_timer(void) void reset_timer_masked(void) { ulong val = __raw_readl(&cur_gpt->counter); - lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); + lastinc = val / (CONFIG_CLK32 / CONFIG_SYS_HZ); timestamp = 0; } ulong get_timer_masked(void) { ulong val = __raw_readl(&cur_gpt->counter); - val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); + val /= (CONFIG_CLK32 / CONFIG_SYS_HZ); if (val >= lastinc) timestamp += (val - lastinc); else - timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ)) + timestamp += ((0xFFFFFFFF / (CONFIG_CLK32 / CONFIG_SYS_HZ)) - lastinc) + val; lastinc = val; return timestamp; @@ -106,7 +106,7 @@ void set_timer(ulong t) void __udelay(unsigned long usec) { unsigned long now, start, tmo; - tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000; + tmo = usec * (CONFIG_CLK32 / 1000) / 1000; if (!tmo) tmo = 1; diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds similarity index 100% rename from arch/arm/cpu/armv7/mx51/u-boot.lds rename to arch/arm/cpu/armv7/mx5/u-boot.lds diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h similarity index 100% rename from arch/arm/include/asm/arch-mx51/asm-offsets.h rename to arch/arm/include/asm/arch-mx5/asm-offsets.h diff --git a/arch/arm/include/asm/arch-mx51/clock.h b/arch/arm/include/asm/arch-mx5/clock.h similarity index 100% rename from arch/arm/include/asm/arch-mx51/clock.h rename to arch/arm/include/asm/arch-mx5/clock.h diff --git a/arch/arm/include/asm/arch-mx51/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h similarity index 100% rename from arch/arm/include/asm/arch-mx51/crm_regs.h rename to arch/arm/include/asm/arch-mx5/crm_regs.h diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h similarity index 100% rename from arch/arm/include/asm/arch-mx51/imx-regs.h rename to arch/arm/include/asm/arch-mx5/imx-regs.h diff --git a/arch/arm/include/asm/arch-mx51/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h similarity index 97% rename from arch/arm/include/asm/arch-mx51/iomux.h rename to arch/arm/include/asm/arch-mx5/iomux.h index a41c387..4eabee7 100644 --- a/arch/arm/include/asm/arch-mx51/iomux.h +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,13 +20,13 @@ * MA 02111-1307 USA */ -#ifndef __MACH_MX51_IOMUX_H__ -#define __MACH_MX51_IOMUX_H__ +#ifndef __MACH_MX5_IOMUX_H__ +#define __MACH_MX5_IOMUX_H__ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx51_pins.h> +#include <asm/arch/mx5x_pins.h> typedef unsigned int iomux_pin_name_t; @@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); void mxc_iomux_set_input(iomux_input_select_t input, u32 config); -#endif /* __MACH_MX51_IOMUX_H__ */ +#endif /* __MACH_MX5_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h similarity index 99% rename from arch/arm/include/asm/arch-mx51/mx51_pins.h rename to arch/arm/include/asm/arch-mx5/mx5x_pins.h index ca26f41..a73187e 100644 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,8 +20,8 @@ * MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ -#define __ASM_ARCH_MXC_MX51_PINS_H__ +#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__ +#define __ASM_ARCH_MX5_MX5X_PINS_H__ #ifndef __ASSEMBLY__ @@ -371,4 +371,4 @@ enum iomux_pins { }; #endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ +#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h old mode 100644 new mode 100755 similarity index 93% rename from arch/arm/include/asm/arch-mx51/sys_proto.h rename to arch/arm/include/asm/arch-mx5/sys_proto.h index bf500a8..ab771f7 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -24,7 +24,8 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#define is_soc_type(rev)((((get_cpu_rev() & 0xFF00)) >> 8) - rev) +u32 get_cpu_rev(void); #endif diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c old mode 100644 new mode 100755 index 75d642b..4b52536 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> -#include <asm/arch/mx51_pins.h> +#include <asm/arch/mx5x_pins.h> #include <asm/arch/iomux.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> diff --git a/boards.cfg b/boards.cfg index 9226424..e144281 100644 --- a/boards.cfg +++ b/boards.cfg @@ -46,7 +46,7 @@ pm9263 arm arm926ejs - ronetix at91 jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood -mx51evk arm armv7 mx51evk freescale mx51 +mx51evk arm armv7 mx51evk freescale mx5 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h old mode 100644 new mode 100755 index 86a4731..363af3d --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. * * Configuration settings for the MX51EVK Board * @@ -28,10 +28,11 @@ /* High Level Configuration Options */ #define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_CPU_TYPE 51 #define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_HCLK_FREQ 24000000 +#define CONFIG_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- 1.7.0.4

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[U-Boot] [PATCH 2/2] Kirkwood: OpenRD: Initialize MPPs during early init
by Tanmay Upadhyay 15 Oct '10

15 Oct '10

This patch adds board_early_init_f function for OpenRD boards. The function initializes MPPs so that peripherals can work at early stage. Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> --- board/Marvell/openrd/openrd.c | 6 +++++- include/configs/openrd.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 3953282..2d34a24 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) +int board_early_init_f(void) { /* * default gpio configuration @@ -108,7 +108,11 @@ int board_init(void) }; kirkwood_mpp_conf(kwmpp_config); + return 0; +} +int board_init(void) +{ /* * arch number of board */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index c4dcad6..850dbae 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -110,4 +110,6 @@ #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET #endif /*CONFIG_MVSATA_IDE*/ +/* board_early_init_f function in openrd.c initializes all MPP settings */ +#define CONFIG_BOARD_EARLY_INIT_F #endif /* _CONFIG_OPENRD_H */ -- 1.6.6.1

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[U-Boot] [PATCH] Kirkwood: bugfix: DRAM size initialization
by Tanmay Upadhyay 15 Oct '10

15 Oct '10

If start of any DRAM bank is greater than total DDR size, remaining DDR bank sizes were left un-initialized in dram_init function. This could break other functions who uses array 'gd->bd->bi_dram'.Kirkwood network driver is one example. Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay(a)einfochips.com> --- arch/arm/cpu/arm926ejs/kirkwood/dram.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 7439c87..cb396d1 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -81,6 +81,13 @@ int dram_init(void) gd->ram_size += gd->bd->bi_dram[i].size; } + + for (; i < CONFIG_NR_DRAM_BANKS; i++) { + /* If above loop terminated prematurely, we need to set + * remaining bank sizes as 0 */ + gd->bd->bi_dram[i].size = 0; + } + return 0; } -- 1.6.6.1

2 2

[U-Boot] (no subject)
by WESTERN UNION TRANSFER 15 Oct '10

15 Oct '10

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1 0

[U-Boot] [PATCH] armv7, beagle: Second SDRAM bank don;t work
by Heiko Schocher 15 Oct '10

15 Oct '10

since commit 3667cbeed5e3c4067e624e52a916b1ebb02c8f05 on beagle board the second sdram bank didn;t longer work. Since this patch sdram settings just get copied from bank a, but CMD_NOP, CMD_PRECHARGE, CMD_AUTOREFRESH are not executed and after that mr register is also not updated. This patch adds this for the bank b. Signed-off-by: Heiko Schocher <hs(a)denx.de> cc: Steve Sakoman <steve(a)sakoman.com> cc: Sandeep Paulraj <s-paulraj(a)ti.com> cc: Wolfgang Denk <wd(a)denx.de> --- Wolfgang, this patch should also be added to u-boot-arm elf_reloc arch/arm/cpu/armv7/omap3/sdrc.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 2719bb5..3087096 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -149,6 +149,13 @@ void do_sdrc_init(u32 cs, u32 early) &sdrc_actim_base1->ctrla); writel(readl(&sdrc_actim_base0->ctrlb), &sdrc_actim_base1->ctrlb); + + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(readl(&sdrc_base->cs[CS0].mr), + &sdrc_base->cs[CS1].mr); } /* -- 1.7.2.3

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