October 2010 - U-Boot

[U-Boot] [RFCv2 3/3] omap3evm: Add quick boot configurations
by Sanjeev Premi 29 Oct '10

29 Oct '10

This patch adds 2 configurations for quick boot on the omap3evm - based on chosen boot media. Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- boards.cfg | 2 + include/configs/omap3_evm_quick_mmc.h | 53 ++++++++++++++++++++++++++++++++ include/configs/omap3_evm_quick_nand.h | 48 +++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 include/configs/omap3_evm_quick_mmc.h create mode 100644 include/configs/omap3_evm_quick_nand.h diff --git a/boards.cfg b/boards.cfg index 6c2a667..e976afb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -387,6 +387,8 @@ omap3_zoom1 arm armv7 zoom1 logicpd omap3 omap3_zoom2 arm armv7 zoom2 logicpd omap3 omap3_beagle arm armv7 beagle ti omap3 omap3_evm arm armv7 evm ti omap3 +omap3_evm_quick_mmc arm armv7 evm ti omap3 +omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 igep0020 arm armv7 igep0020 isee omap3 igep0030 arm armv7 igep0030 isee omap3 diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h new file mode 100644 index 0000000..e760e90 --- /dev/null +++ b/include/configs/omap3_evm_quick_mmc.h @@ -0,0 +1,53 @@ +/* + * Configuration settings for quick boot on OMAP3 EVM. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author : + * Sanjeev Premi <premi(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __OMAP3_EVM_QUICK_MMC_H +#define __OMAP3_EVM_QUICK_MMC_H + +#include "omap3_evm_common.h" + +/* + * Generic config options + */ +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_ENV_IS_NOWHERE 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "bootfile=uImage\0" + +/* + * Environment and boot command + */ +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "mmc init; " \ + "fatload mmc 0 0x80000000 uImage; " \ + "bootm 0x80000000;" + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200n8 " \ + "mem=128M quiet noinitrd" \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait " + +#endif /* __OMAP3_EVM_QUICK_MMC_H */ + + diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h new file mode 100644 index 0000000..dccf67f --- /dev/null +++ b/include/configs/omap3_evm_quick_nand.h @@ -0,0 +1,48 @@ +/* + * Configuration settings for quick boot on OMAP3 EVM. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author : + * Sanjeev Premi <premi(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __OMAP3_EVM_QUICK_NAND_H +#define __OMAP3_EVM_QUICK_NAND_H + +#include "omap3_evm_common.h" + +/* + * Generic config options + */ +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_ENV_IS_NOWHERE 1 + +/* + * Environment and boot command + */ +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "nand read.i 0x80000000 280000 500000; " \ + "bootm 0x80000000;" + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200n8 " \ + "mem=128M quiet noinitrd" \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2 " + +#endif /* __OMAP3_EVM_QUICK_NAND_H */ + + -- 1.7.2.2

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[U-Boot] [RFCv2 2/3] omap3evm: move common config options to new file
by Sanjeev Premi 29 Oct '10

29 Oct '10

This patch moves common config options to a new file. Common options can now be included in other board configs for this evm. Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- include/configs/omap3_evm.h | 210 ++-------------------------------- include/configs/omap3_evm_common.h | 226 ++++++++++++++++++++++++++++++++++++ 2 files changed, 234 insertions(+), 202 deletions(-) create mode 100644 include/configs/omap3_evm_common.h diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 0cb12db..295a93d 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -1,6 +1,8 @@ /* - * (C) Copyright 2006-2008 - * Texas Instruments. + * Configuration settings for the TI OMAP3 EVM board. + * + * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/ + * * Author : * Manikandan Pillai <mani.pillai(a)ti.com> * Derived from Beagle Board and 3430 SDP code by @@ -9,8 +11,6 @@ * * Manikandan Pillai <mani.pillai(a)ti.com> * - * Configuration settings for the TI OMAP3 EVM board. - * * See file CREDITS for list of people who contributed to this * project. * @@ -30,192 +30,10 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __OMAP3EVM_CONFIG_H +#define __OMAP3EVM_CONFIG_H -/* - * High level configuration options - */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_EVM 1 /* working with EVM */ -#define CONFIG_SDRC 1 /* chip has SDRC controller */ -#define CONFIG_OMAP3_MICRON_DDR 1 -#define CONFIG_TWL4030_POWER 1 - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> - -#undef CONFIG_USE_IRQ /* no support for IRQs */ - -/* - * Clock related definitions - */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ - /* initial data */ -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif - -/* - * Physical Memory Map - * Note 1: CS1 may or may not be populated - * Note 2: SDRAM size is expected to be at least 32MB - */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* Limits for memtest */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ -/* - * SDRAM Bank Allocation method - */ -#define SDRC_R_B_C 1 - -/* - * Default load address - */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * Size of Console IO Buffer - */ -#define CONFIG_SYS_CBSIZE 256 - -/* - * Size of print buffer - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Size of bootarg buffer - */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * I2C - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - -/* - * PISMO support - */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -/* Max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 - -/* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -#define CONFIG_SYS_FLASH_BASE boot_flash_base - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR boot_flash_env_addr - -/* - * Start location of environment - */ -#define ONENAND_ENV_OFFSET 0x260000 -#define SMNAND_ENV_OFFSET 0x260000 - -/* - * NAND - */ -/* Physical address to access NAND */ -#define CONFIG_SYS_NAND_ADDR NAND_BASE - -/* Physical address to access NAND at CS0 */ -#define CONFIG_SYS_NAND_BASE NAND_BASE - -/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Timeout values (in ticks) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) - -#define CONFIG_SYS_JFFS2_MEM_NAND -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* Start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -/* Size of jffs2 partition */ -#define CONFIG_JFFS2_PART_SIZE 0xf980000 - -#define CONFIG_SYS_NO_FLASH +#include "omap3_evm_common.h" /* * MMC @@ -264,22 +82,11 @@ #endif /* CONFIG_USB_OMAP3 */ -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - /* * U-boot features */ #define CONFIG_SYS_LONGHELP 1 #define CONFIG_SYS_HUSH_PARSER 1 -#define CONFIG_SYS_PROMPT "OMAP3_EVM # " -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 @@ -346,7 +153,6 @@ extern unsigned int boot_flash_type; * Environment and boot command */ #define CONFIG_BOOTDELAY 10 -#define CONFIG_BOOTFILE uImage #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ @@ -382,4 +188,4 @@ extern unsigned int boot_flash_type; "fi; " \ "else run nandboot; fi" -#endif /* __CONFIG_H */ +#endif /* __OMAP3EVM_CONFIG_H */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h new file mode 100644 index 0000000..3ac11f4 --- /dev/null +++ b/include/configs/omap3_evm_common.h @@ -0,0 +1,226 @@ +/* + * Common configuration settings for the TI OMAP3 EVM board. + * + * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __OMAP3_EVM_COMMON_H +#define __OMAP3_EVM_COMMON_H + +/* + * High level configuration options + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_EVM 1 /* working with EVM */ +#define CONFIG_SDRC 1 /* chip has SDRC controller */ +#define CONFIG_OMAP3_MICRON_DDR 1 +#define CONFIG_TWL4030_POWER 1 +#define CONFIG_BOOTFILE uImage + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#undef CONFIG_USE_IRQ /* no support for IRQs */ + +/* + * Clock related definitions + */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/* + * Physical Memory Map + * Note 1: CS1 may or may not be populated + * Note 2: SDRAM size is expected to be at least 32MB + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* Limits for memtest */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ +/* + * SDRAM Bank Allocation method + */ +#define SDRC_R_B_C 1 + +/* + * Default load address + */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* + * Size of Console IO Buffer + */ +#define CONFIG_SYS_CBSIZE 256 + +/* + * Size of print buffer + */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Size of bootarg buffer + */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* + * I2C + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * PISMO support + */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +/* Max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 520 + +/* Max number of flash banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/* + * Start location of environment + */ +#define ONENAND_ENV_OFFSET 0x260000 +#define SMNAND_ENV_OFFSET 0x260000 + +/* + * NAND + */ +/* Physical address to access NAND */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE + +/* Physical address to access NAND at CS0 */ +#define CONFIG_SYS_NAND_BASE NAND_BASE + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Timeout values (in ticks) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) + +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* Start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +/* Size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 + +#define CONFIG_SYS_NO_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +/* + * Common U-boot definitions + */ +#define CONFIG_SYS_PROMPT "OMAP3_EVM # " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - \ + CONFIG_SYS_GBL_DATA_SIZE) + + +#endif /* __OMAP3_EVM_COMMON_H */ -- 1.7.2.2

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[U-Boot] [RFCv2 1/3] omap3evm: Reorder related config options
by Sanjeev Premi 29 Oct '10

29 Oct '10

This patch brings related config options together. Some formatting changes were also done for consistent look-n-feel after the movement. The patch doesn't make/include any other functional change. Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- include/configs/omap3_evm.h | 404 ++++++++++++++++++++++--------------------- 1 files changed, 210 insertions(+), 194 deletions(-) diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index e925f3b..0cb12db 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -34,47 +34,79 @@ #define __CONFIG_H /* - * High Level Configuration Options + * High level configuration options */ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_EVM 1 /* working with EVM */ +#define CONFIG_SDRC 1 /* chip has SDRC controller */ +#define CONFIG_OMAP3_MICRON_DDR 1 +#define CONFIG_TWL4030_POWER 1 -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> +#undef CONFIG_USE_IRQ /* no support for IRQs */ + /* - * Display CPU and Board information + * Clock related definitions */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -/* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /* * Size of malloc() pool */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ + /* Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ /* - * Hardware drivers + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/* + * Physical Memory Map + * Note 1: CS1 may or may not be populated + * Note 2: SDRAM size is expected to be at least 32MB + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* Limits for memtest */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ +/* + * SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/* + * Default load address + */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* * NS16550 Configuration @@ -90,23 +122,112 @@ * select serial console configuration */ #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} + +/* + * Size of Console IO Buffer + */ +#define CONFIG_SYS_CBSIZE 256 + +/* + * Size of print buffer + */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Size of bootarg buffer + */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* + * I2C + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * PISMO support + */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +/* Max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 520 + +/* Max number of flash banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/* + * Start location of environment + */ +#define ONENAND_ENV_OFFSET 0x260000 +#define SMNAND_ENV_OFFSET 0x260000 + +/* + * NAND + */ +/* Physical address to access NAND */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE + +/* Physical address to access NAND at CS0 */ +#define CONFIG_SYS_NAND_BASE NAND_BASE + +/* Max number of NAND devices */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Timeout values (in ticks) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) + +#define CONFIG_SYS_JFFS2_MEM_NAND +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* Start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +/* Size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 + +#define CONFIG_SYS_NO_FLASH + +/* + * MMC + */ #define CONFIG_MMC 1 #define CONFIG_OMAP3_MMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - -/* USB - * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard +/* + * USB + * + * Enable CONFIG_MUSB_HCD for Host functionalities e.g. MSC, keyboard * Enable CONFIG_MUSB_UDD for Device functionalities. */ #define CONFIG_USB_OMAP3 1 @@ -124,7 +245,7 @@ #ifdef CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL -#define CONFIG_PREBOOT "usb start" +#define CONFIG_PREBOOT "usb start" #endif /* CONFIG_USB_KEYBOARD */ #endif /* CONFIG_MUSB_HCD */ @@ -143,7 +264,39 @@ #endif /* CONFIG_USB_OMAP3 */ -/* commands to include */ +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +/* + * U-boot features + */ +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT "OMAP3_EVM # " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_MAXARGS 16 /* max args for a command */ + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_MISC_INIT_R 1 + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_AUTO_COMPLETE 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Common commands + */ #include <config_cmd_default.h> #define CONFIG_CMD_EXT2 /* EXT2 Support */ @@ -161,41 +314,39 @@ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 - /* - * TWL4030 + * Additional definitions that depend on chosen commands */ -#define CONFIG_TWL4030_POWER 1 +/* NAND */ +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_ENV_IS_IN_ONENAND 1 +#endif -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ +/* Ethernet (SMSC9115 from SMSC9118 family) */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +/* BOOTP fields */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 -/* Environment information */ -#define CONFIG_BOOTDELAY 10 +#endif /* (CONFIG_CMD_NET) */ -#define CONFIG_BOOTFILE uImage +/* + * Environment and boot command + */ +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTFILE uImage #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ @@ -231,139 +382,4 @@ "fi; " \ "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT "OMAP3_EVM # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command */ - /* args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ -#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE boot_flash_base - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -#define CONFIG_ENV_IS_IN_NAND -#elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_ENV_IS_IN_ONENAND 1 -#endif -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off -#define CONFIG_ENV_ADDR boot_flash_env_addr - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#ifndef __ASSEMBLY__ -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - -/*---------------------------------------------------------------------------- - * SMSC9115 Ethernet from SMSC9118 family - *---------------------------------------------------------------------------- - */ -#if defined(CONFIG_CMD_NET) - -#define CONFIG_NET_MULTI -#define CONFIG_SMC911X -#define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 - -#endif /* (CONFIG_CMD_NET) */ - -/* - * BOOTP fields - */ - -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 - #endif /* __CONFIG_H */ -- 1.7.2.2

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[U-Boot] [STATUS] v2010.12-rc1 released
by Wolfgang Denk 29 Oct '10

29 Oct '10

Hello everybody: * U-Boot v2010.12-rc1 was released on Wed, 27 Oct 2010. * Release "v2010.12" i scheduled in 47 days - on December 13, 2010. For details please see http://www.denx.de/wiki/U-Boot/ReleaseCycle Please help testing, and check if all your relevant patches have been included. Current status is a pretty mixed. Most architectures are in a reasonable state, giving the current point in the release cycle. ARM is different - ARM was in the epicentre of a large earthquake, and clean-up operations are still somewhat in the beginnings. I hope many people join the efforts and fix all the currently broken boards. Thanks in advance to everybody who lends a helping hand. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de You could end up being oddly sad and full of a strange, diffuse com- passion which would lead you to believe that it might be a good idea to wipe out the whole human race and start again with amoebas. - Terry Pratchett, _Guards! Guards!_

3 3

[U-Boot] [PATCH 2/3 V4] Remove board_nand_init from nand_boot.c
by Sughosh Ganu 29 Oct '10

29 Oct '10

Remove the board_init_f function from nand_spl/nand_boot.c. This function is to be defined by all boards using the nand_spl functionality in their individual board directory. Currently this function was being used by the smdk6400 board. Added the board specific function definition. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- Changes since V3: * Removed the board_init_f function from the nand_boot.c instead of adding a weak declaration. * Added a corresponding function definition for the smdk6400 board. The changes for smdk6400 have not been tested as it is currently broken due to the relocation and ELF-RELOC changes. board/samsung/smdk6400/smdk6400_nand_spl.c | 37 ++++++++++++++++++++++++++++ nand_spl/board/samsung/smdk6400/Makefile | 6 ++++- nand_spl/nand_boot.c | 8 ------ 3 files changed, 42 insertions(+), 9 deletions(-) create mode 100644 board/samsung/smdk6400/smdk6400_nand_spl.c diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c new file mode 100644 index 0000000..a023284 --- /dev/null +++ b/board/samsung/smdk6400/smdk6400_nand_spl.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +void board_init_f(unsigned long bootflag) +{ + relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, + CONFIG_SYS_TEXT_BASE); +} diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile index 2111e57..18cee10 100644 --- a/nand_spl/board/samsung/smdk6400/Makefile +++ b/nand_spl/board/samsung/smdk6400/Makefile @@ -35,7 +35,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o cpu_init.o lowlevel_init.o -COBJS = nand_boot.o nand_ecc.o s3c64xx.o +COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -93,6 +93,10 @@ $(obj)s3c64xx.c: @rm -f $@ @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@ +$(obj)smdk6400_nand_spl.c: + @rm -f $@ + @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@ + ######################################################################### $(obj)%.o: $(obj)%.S diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index ccd0af2..b9fd6f5 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -221,14 +221,6 @@ static int nand_load(struct mtd_info *mtd, unsigned int offs, return 0; } -#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) -void board_init_f (ulong bootflag) -{ - relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} -#endif - /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image -- 1.7.0.4

3 2

[U-Boot] [PATCH 1/3 V4] Move and rename common headers from under board/davinci.
by Sughosh Ganu 29 Oct '10

29 Oct '10

Move the davinci common headers to the architecture specific include file path. Signed-off-by: Sughosh Ganu <urwithsughosh(a)gmail.com> --- Changes since V3: * No change in this patch of the patchset .../arm/include/asm/arch-davinci/da8xx_common.h | 0 .../arm/include/asm/arch-davinci/davinci_misc.h | 0 board/davinci/common/misc.c | 2 +- board/davinci/da8xxevm/common.c | 2 +- board/davinci/da8xxevm/da830evm.c | 4 ++-- board/davinci/da8xxevm/da850evm.c | 4 ++-- board/davinci/dm355evm/dm355evm.c | 2 +- board/davinci/dm355leopard/dm355leopard.c | 2 +- board/davinci/dm365evm/dm365evm.c | 2 +- board/davinci/dvevm/dvevm.c | 2 +- board/davinci/schmoogie/schmoogie.c | 2 +- board/davinci/sffsdr/sffsdr.c | 2 +- board/davinci/sonata/sonata.c | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) rename board/davinci/da8xxevm/common.h => arch/arm/include/asm/arch-davinci/da8xx_common.h (100%) rename board/davinci/common/misc.h => arch/arm/include/asm/arch-davinci/davinci_misc.h (100%) diff --git a/board/davinci/da8xxevm/common.h b/arch/arm/include/asm/arch-davinci/da8xx_common.h similarity index 100% rename from board/davinci/da8xxevm/common.h rename to arch/arm/include/asm/arch-davinci/da8xx_common.h diff --git a/board/davinci/common/misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h similarity index 100% rename from board/davinci/common/misc.h rename to arch/arm/include/asm/arch-davinci/davinci_misc.h diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index b60a46e..71e7822 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -29,7 +29,7 @@ #include <net.h> #include <asm/arch/hardware.h> #include <asm/io.h> -#include "misc.h" +#include <asm/arch/davinci_misc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/da8xxevm/common.c b/board/davinci/da8xxevm/common.c index 9cd5204..36bf693 100644 --- a/board/davinci/da8xxevm/common.c +++ b/board/davinci/da8xxevm/common.c @@ -20,7 +20,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> -#include "common.h" +#include <asm/arch/da8xx_common.h> #ifndef CONFIG_USE_IRQ void irq_init(void) diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 8a9f988..b6b7e37 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -40,8 +40,8 @@ #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> -#include "../common/misc.h" -#include "common.h" +#include <asm/arch/davinci_misc.h> +#include <asm/arch/da8xx_common.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index c8c5e1b..0420ad5 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -29,8 +29,8 @@ #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> -#include "../common/misc.h" -#include "common.h" +#include <asm/arch/davinci_misc.h> +#include <asm/arch/da8xx_common.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 87f284c..b9260b8 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -22,7 +22,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/nand_defs.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> #include <net.h> #include <netdev.h> diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c index e89786e..0ee0d11 100644 --- a/board/davinci/dm355leopard/dm355leopard.c +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -22,7 +22,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/gpio_defs.h> #include <asm/arch/nand_defs.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> #include <net.h> #include <netdev.h> diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 85dbe2a..bc681f7 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -24,7 +24,7 @@ #include <asm/arch/nand_defs.h> #include <asm/arch/gpio_defs.h> #include <netdev.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 073c21a..d5c851b 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -27,7 +27,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 80a0f9f..8b615a9 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -27,7 +27,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index 657cf2b..cc3ff7d 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -30,7 +30,7 @@ #include <common.h> #include <i2c.h> #include <asm/arch/hardware.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ #define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index 1dc42c4..c194290 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -28,7 +28,7 @@ #include <nand.h> #include <asm/arch/nand_defs.h> #include <asm/arch/hardware.h> -#include "../common/misc.h" +#include <asm/arch/davinci_misc.h> DECLARE_GLOBAL_DATA_PTR; -- 1.7.0.4

2 1

[U-Boot] SP810 (ARM SYSCTL) Technical Reference Manual
by Himanshu Chauhan 29 Oct '10

29 Oct '10

Hi List, Where can I get SP810 technical reference? It not there on the internet. Thanks Regards Himanshu

1 0

[U-Boot] [PATCH] ftsmc020: move ftsmc020 static mem controller to driver/mtd folder
by Macpaul Lin 29 Oct '10

29 Oct '10

Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder. This change will let other SoC which also use ftsmc020 could share the same header file. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- arch/arm/cpu/arm920t/a320/Makefile | 1 - arch/arm/cpu/arm920t/a320/ftsmc020.c | 51 ------------------ arch/arm/include/asm/arch-a320/ftsmc020.h | 79 ----------------------------- board/faraday/a320evb/a320evb.c | 4 +- drivers/mtd/Makefile | 1 + drivers/mtd/ftsmc020.c | 51 ++++++++++++++++++ drivers/mtd/ftsmc020.h | 79 +++++++++++++++++++++++++++++ include/configs/a320evb.h | 7 ++- 8 files changed, 139 insertions(+), 134 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/a320/ftsmc020.c delete mode 100644 arch/arm/include/asm/arch-a320/ftsmc020.h create mode 100644 drivers/mtd/ftsmc020.c create mode 100644 drivers/mtd/ftsmc020.h diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile index f030c53..978b99e 100644 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ b/arch/arm/cpu/arm920t/a320/Makefile @@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).a SOBJS += reset.o COBJS += timer.o -COBJS += ftsmc020.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/arm920t/a320/ftsmc020.c b/arch/arm/cpu/arm920t/a320/ftsmc020.c deleted file mode 100644 index 7646537..0000000 --- a/arch/arm/cpu/arm920t/a320/ftsmc020.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert(a)faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ftsmc020.h> - -struct ftsmc020_config { - unsigned int config; - unsigned int timing; -}; - -static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; - -static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; - -static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) -{ - if (bank > 3) { - printf("bank # %u invalid\n", bank); - return; - } - - writel(cfg->config, &smc->bank[bank].cr); - writel(cfg->timing, &smc->bank[bank].tpr); -} - -void ftsmc020_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(config); i++) - ftsmc020_setup_bank(i, &config[i]); -} diff --git a/arch/arm/include/asm/arch-a320/ftsmc020.h b/arch/arm/include/asm/arch-a320/ftsmc020.h deleted file mode 100644 index 95d9500..0000000 --- a/arch/arm/include/asm/arch-a320/ftsmc020.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert(a)faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Static Memory Controller - */ -#ifndef __FTSMC020_H -#define __FTSMC020_H - -#ifndef __ASSEMBLY__ - -struct ftsmc020 { - struct { - unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ - unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ - } bank[4]; - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ -}; - -void ftsmc020_init(void); - -#endif /* __ASSEMBLY__ */ - -/* - * Memory Bank Configuration Register - */ -#define FTSMC020_BANK_ENABLE (1 << 28) -#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) - -#define FTSMC020_BANK_WPROT (1 << 11) - -#define FTSMC020_BANK_SIZE_32K (0xb << 4) -#define FTSMC020_BANK_SIZE_64K (0xc << 4) -#define FTSMC020_BANK_SIZE_128K (0xd << 4) -#define FTSMC020_BANK_SIZE_256K (0xe << 4) -#define FTSMC020_BANK_SIZE_512K (0xf << 4) -#define FTSMC020_BANK_SIZE_1M (0x0 << 4) -#define FTSMC020_BANK_SIZE_2M (0x1 << 4) -#define FTSMC020_BANK_SIZE_4M (0x2 << 4) -#define FTSMC020_BANK_SIZE_8M (0x3 << 4) -#define FTSMC020_BANK_SIZE_16M (0x4 << 4) -#define FTSMC020_BANK_SIZE_32M (0x5 << 4) - -#define FTSMC020_BANK_MBW_8 (0x0 << 0) -#define FTSMC020_BANK_MBW_16 (0x1 << 0) -#define FTSMC020_BANK_MBW_32 (0x2 << 0) - -/* - * Memory Bank Timing Parameter Register - */ -#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) -#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) -#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) -#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) -#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) -#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) -#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) -#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) -#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) - -#endif /* __FTSMC020_H */ diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index 85b11b9..8f95272 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -21,7 +21,9 @@ #include <netdev.h> #include <asm/io.h> -#include <asm/arch/ftsmc020.h> +#ifdef CONFIG_FTSMC020 +#include "../../../drivers/mtd/ftsmc020.h" +#endif DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index cbf6f15..d445191 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_FTSMC020) += ftsmc020.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/ftsmc020.c b/drivers/mtd/ftsmc020.c new file mode 100644 index 0000000..9915f44 --- /dev/null +++ b/drivers/mtd/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include "ftsmc020.h" + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + +static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf("bank # %u invalid\n", bank); + return; + } + + writel(cfg->config, &smc->bank[bank].cr); + writel(cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(config); i++) + ftsmc020_setup_bank(i, &config[i]); +} diff --git a/drivers/mtd/ftsmc020.h b/drivers/mtd/ftsmc020.h new file mode 100644 index 0000000..95d9500 --- /dev/null +++ b/drivers/mtd/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init(void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index fcc5563..8746fbb 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -153,7 +153,10 @@ * Static memory controller configuration */ -#include <asm/arch/ftsmc020.h> +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include "../../drivers/mtd/ftsmc020.h" #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ @@ -186,7 +189,7 @@ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ } - +#endif /* CONFIG_FTSMC020 */ /*----------------------------------------------------------------------- * FLASH and environment organization */ -- 1.7.3.2

1 0

[U-Boot] [PATCH] Adds general Freescale CodeWarrior debug support
by Roy Zang 29 Oct '10

29 Oct '10

This patch adds general CodeWarrior debug support. Patch is tested on 85xx/QorIQ platforms in u-boot. CONFIG_DEBUG_CODEWARRIOR should be defined if the u-boot needs to be debugged by CodeWarrior. To use the CodeWarrior debug funciton, the make command can be just as make CONFIG_DEBUG_CODEWARRIOR=1 Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: adrian bogdan <adrian.bogdan(a)freescale.com> Cc: Wood Scott-B07421 <B07421(a)freescale.com> Cc: Kumar Gala <galak(a)kernel.crashing.org> --- config.mk | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/config.mk b/config.mk index ce8e5f2..4d4bb59 100644 --- a/config.mk +++ b/config.mk @@ -189,6 +189,10 @@ else CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes endif +ifdef CONFIG_DEBUG_CODEWARRIOR +CFLAGS += -ggdb +endif + CFLAGS += $(call cc-option,-fno-stack-protector) # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format> @@ -202,6 +206,10 @@ AFLAGS_DEBUG := -Wa,-gstabs,-S endif endif +ifdef CONFIG_DEBUG_CODEWARRIOR +AFLAGS_DEBUG := -Wa,-gdwarf2 +endif + AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) LDFLAGS += -Bstatic -T $(obj)u-boot.lds $(PLATFORM_LDFLAGS) -- 1.5.6.5

2 1

[U-Boot] Kernel OOPS on memcpy - bad memory setup?
by Kristoffer Ericson 28 Oct '10

28 Oct '10

Greetings, Getting an kernel oops after running an package manager (ipkg). Not seeing it anywhere else, but dont have any large binaries (busybox). So, I assume I have made some memory error in u-boot? Best wishes Kristoffer LOG: [ 25.195972] udevd (417): /proc/417/oom_adj is deprecated, please use /proc/417/oom_score_adj instead. [ 26.664276] Adding 34200k swap on /opt/swapfile. Priority:-1 extents:10 across:34240k [ 90.617094] Unable to handle kernel paging request at virtual address 2d429000 [ 90.764870] pgd = c7d84000 [ 90.832643] [2d429000] *pgd=00000000 [ 90.904966] Internal error: Oops: 47d87805 [#1] [ 90.984380] last sysfs file: /sys/kernel/uevent_seqnum [ 91.069037] CPU: 0 Not tainted (2.6.36-hpc+ #6) [ 91.152013] PC is at memcpy+0x30/0x29c [ 91.227604] LR is at 0x70692e6d [ 91.298029] pc : [<c031f590>] lr : [<70692e6d>] psr: 20000093 [ 91.298062] sp : c7d7fd08 ip : 72615f35 fp : c7d7fd4c [ 91.470248] r10: 00000000 r9 : c7d0c6a0 r8 : 32722d38 [ 91.551723] r7 : 2e382e35 r6 : 5f73706f r5 : 2d656c75 r4 : 646f6d2d [ 91.641784] r3 : 6c726570 r2 : 00000fc0 r1 : c0048020 r0 : 2d429000 [ 91.731741] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user [ 91.875472] Control: c7d8717f Table: c7d8717f DAC: 00000015 [ 91.961726] Process ipkg (pid: 572, stack limit = 0xc7d7e260) [ 92.047824] Stack: (0xc7d7fd08 to 0xc7d80000) [ 92.124740] fd00: c7d95c80 0000001d 0000015c c7d95d00 2d429000 c7d1245c [ 92.276297] fd20: c028f608 c7d95c80 c7d753e8 00000000 00020000 00000000 00000000 00000000 [ 92.427886] fd40: c7d7fd5c c7d7fd50 c028f65c c028f560 c7d7fd6c c7d7fd60 c02bfd50 c028f64c [ 92.581195] fd60: c7d7fd88 c7d7fd70 c030ff4c c02bfd08 c7d95c80 00020000 c7d753e8 c7d7fdb8 [ 92.734712] fd80: c7d7fd8c c031009c c030fe80 00000000 c7d753e8 00000000 00000000 00000040 [ 92.889737] fda0: 00000001 c01da494 c01da400 c7d7fdd8 c7d7fdbc c031033c c030ff7c c01da400 [ 93.046471] fdc0: c7d753e8 00000000 00000040 c7d7fdf8 c7d7fddc c0310e14 c031032c c01da400 [ 93.207687] fde0: 00000050 c01ce400 00000040 c7d7fe08 c7d7fdfc c0310e6c c0310e08 c7d7fe18 [ 93.373300] fe00: c7d7fe0c c03666d8 c0310e64 c7d7fe2c c7d7fe1c c0366730 c03666a8 c01da400 [ 93.541968] fe20: c7d7fe58 c7d7fe30 c036a22c c03666e8 c01da400 c01f4960 00000000 40000093 [ 93.715230] fe40: c036a0c0 c04b6640 c01ce400 c7d7fe80 c7d7fe5c c03664b4 c036a0cc c01fb640 [ 93.891486] fe60: 00000073 00000001 00000000 00000000 00000001 c7d7fea4 c7d7fe84 c0263160 [ 94.071438] fe80: c036633c c04b89e0 c01fb640 00000073 c04d02f4 c0142c60 c7d7fec4 c7d7fea8 [ 94.253160] fea0: c0264ebc c026313c 00000073 00000032 00000000 00000000 c7d7fef0 c7d7fec8 [ 94.436933] fec0: c0228850 c0264dc4 00000001 c7d7ffb0 00000002 00000202 00000000 c04cd984 [ 94.622731] fee0: 0000000a c7d7ff08 c7d7fef4 c0220078 c0228788 ffffffff fa050000 c7d7ff84 [ 94.810257] ff00: c7d7ff0c c02208ec c022000c c04cd960 c7d7e000 00000000 20000013 0000001a [ 94.997749] ff20: c7d7e000 00000000 00000202 00000000 c04cd984 0000000a c7d7ff84 c7d7ff88 [ 95.185309] ff40: c7d7ff54 c024097c c0240694 60000013 ffffffff c0263160 c04b6e10 0000001a [ 95.372794] ff60: 00000000 00000001 00001c7a 00000000 c7d7e000 401f5188 c7d7ff94 c7d7ff88 [ 95.560093] ff80: c024097c c024064c c7d7ffac c7d7ff98 c022007c c0240948 ffffffff fa050000 [ 95.747426] ffa0: 00000000 c7d7ffb0 c0220ae8 c022000c 0008bac8 00000000 00000041 00000001 [ 95.934715] ffc0: 00000037 00063d00 00001000 00001c7a 00000000 00021490 401f5188 0008e9e8 [ 96.122023] ffe0: 00000001 bea9badc 00001fd0 40260814 60000010 ffffffff c7ffe031 c7ffe431 [ 96.309348] Backtrace: [ 96.390184] [<c028f554>] (__bounce_end_io_read+0x0/0xec) from [<c028f65c>] (bounce_end_io_read_isa+0x1c/0x24) [ 96.585508] [<c028f640>] (bounce_end_io_read_isa+0x0/0x24) from [<c02bfd50>] (bio_endio+0x54/0x58) [ 96.775490] [<c02bfcfc>] (bio_endio+0x0/0x58) from [<c030ff4c>] (req_bio_endio+0xd8/0xfc) [ 96.961106] [<c030fe74>] (req_bio_endio+0x0/0xfc) from [<c031009c>] (blk_update_request+0x12c/0x3b0) [ 97.153259] r6:c7d753e8 r5:00020000 r4:c7d95c80 [ 97.248362] [<c030ff70>] (blk_update_request+0x0/0x3b0) from [<c031033c>] (blk_update_bidi_request+0x1c/0x6c) [ 97.444051] [<c0310320>] (blk_update_bidi_request+0x0/0x6c) from [<c0310e14>] (blk_end_bidi_request+0x18/0x5c) [ 97.641155] r7:00000040 r6:00000000 r5:c7d753e8 r4:c01da400 [ 97.743099] [<c0310dfc>] (blk_end_bidi_request+0x0/0x5c) from [<c0310e6c>] (blk_end_request+0x14/0x18) [ 97.935168] r7:00000040 r6:c01ce400 r5:00000050 r4:c01da400 [ 98.036771] [<c0310e58>] (blk_end_request+0x0/0x18) from [<c03666d8>] (ide_end_rq+0x3c/0x40) [ 98.222439] [<c036669c>] (ide_end_rq+0x0/0x40) from [<c0366730>] (ide_complete_rq+0x54/0x60) [ 98.408814] [<c03666dc>] (ide_complete_rq+0x0/0x60) from [<c036a22c>] (task_pio_intr+0x16c/0x1f0) [ 98.598631] r4:c01da400 [ 98.679114] [<c036a0c0>] (task_pio_intr+0x0/0x1f0) from [<c03664b4>] (ide_intr+0x184/0x250) [ 98.862871] [<c0366330>] (ide_intr+0x0/0x250) from [<c0263160>] (handle_IRQ_event+0x30/0xf4) [ 99.047770] [<c0263130>] (handle_IRQ_event+0x0/0xf4) from [<c0264ebc>] (handle_edge_irq+0x104/0x164) [ 99.240827] r8:c0142c60 r7:c04d02f4 r6:00000073 r5:c01fb640 r4:c04b89e0 [ 99.350444] [<c0264db8>] (handle_edge_irq+0x0/0x164) from [<c0228850>] (sa1111_irq_handler+0xd4/0xf4) [ 99.543455] r7:00000000 r6:00000000 r5:00000032 r4:00000073 [ 99.645480] [<c022877c>] (sa1111_irq_handler+0x0/0xf4) from [<c0220078>] (asm_do_IRQ+0x78/0x9c) [ 99.833488] [<c0220000>] (asm_do_IRQ+0x0/0x9c) from [<c02208ec>] (__irq_svc+0x2c/0xa0) [ 100.017497] Exception stack(0xc7d7ff0c to 0xc7d7ff54) [ 100.116493] ff00: c04cd960 c7d7e000 00000000 20000013 0000001a [ 100.300200] ff20: c7d7e000 00000000 00000202 00000000 c04cd984 0000000a c7d7ff84 c7d7ff88 [ 100.482375] ff40: c7d7ff54 c024097c c0240694 60000013 ffffffff [ 100.584664] r5:fa050000 r4:ffffffff [ 100.670851] [<c0240640>] (__do_softirq+0x0/0x110) from [<c024097c>] (irq_exit+0x40/0x48) [ 100.851666] [<c024093c>] (irq_exit+0x0/0x48) from [<c022007c>] (asm_do_IRQ+0x7c/0x9c) [ 101.030912] [<c0220000>] (asm_do_IRQ+0x0/0x9c) from [<c0220ae8>] (__irq_usr+0x48/0xc0) [ 101.210396] Exception stack(0xc7d7ffb0 to 0xc7d7fff8) [ 101.306439] ffa0: 0008bac8 00000000 00000041 00000001 [ 101.487559] ffc0: 00000037 00063d00 00001000 00001c7a 00000000 00021490 401f5188 0008e9e8 [ 101.667226] ffe0: 00000001 bea9badc 00001fd0 40260814 60000010 ffffffff [ 101.772855] r5:fa050000 r4:ffffffff [ 101.857748] Code: e92d01e0 ba000003 e8b151f8 e2522020 (e8a051f8) [ 101.971402] ---[ end trace 6605307e29c0d995 ]--- [ 102.062940] Kernel panic - not syncing: Fatal exception in interrupt [ 102.165115] Backtrace: [ 102.241096] [<c0223fd8>] (dump_backtrace+0x0/0x110) from [<c022411c>] (dump_stack+0x18/0x1c) [ 102.417506] r6:c7d7fcc0 r5:c7d7e000 r4:c04c904c [ 102.507326] [<c0224104>] (dump_stack+0x0/0x1c) from [<c023b518>] (panic+0x60/0x19c) [ 102.676799] [<c023b4b8>] (panic+0x0/0x19c) from [<c0224424>] (die+0x17c/0x1bc) [ 102.845391] r3:00010100 r2:c04974ac r1:00000000 r0:c048ed0c [ 102.943232] [<c02242a8>] (die+0x0/0x1bc) from [<c0225680>] (__do_kernel_fault+0x6c/0x90) [ 103.118470] r8:00000000 r7:47d87805 r6:c7d90780 r5:c7d7fcc0 r4:2d429000 [ 103.223741] [<c0225614>] (__do_kernel_fault+0x0/0x90) from [<c0225910>] (do_page_fault+0x26c/0x28c) [ 103.407223] r8:2d429000 r7:2d429000 r6:47d87805 r5:c7d7fcc0 r4:ffffffff [ 103.513279] [<c02256a4>] (do_page_fault+0x0/0x28c) from [<c02259d8>] (do_translation_fault+0x24/0xac) [ 103.697401] [<c02259b4>] (do_translation_fault+0x0/0xac) from [<c02202d4>] (do_DataAbort+0x40/0xa4) [ 103.880806] r6:c7d87805 r5:c04b2db8 r4:ffffffff [ 103.972998] [<c0220294>] (do_DataAbort+0x0/0xa4) from [<c02208a0>] (__dabt_svc+0x40/0x60) [ 104.151881] Exception stack(0xc7d7fcc0 to 0xc7d7fd08) [ 104.247706] fcc0: 2d429000 c0048020 00000fc0 6c726570 646f6d2d 2d656c75 5f73706f 2e382e35 [ 104.426405] fce0: 32722d38 c7d0c6a0 00000000 c7d7fd4c 72615f35 c7d7fd08 70692e6d c031f590 [ 104.606820] fd00: 20000093 ffffffff [ 104.692761] r8:32722d38 r7:2e382e35 r6:5f73706f r5:c7d7fcf4 r4:ffffffff [ 104.799707] [<c028f554>] (__bounce_end_io_read+0x0/0xec) from [<c028f65c>] (bounce_end_io_read_isa+0x1c/0x24) [ 104.991790] [<c028f640>] (bounce_end_io_read_isa+0x0/0x24) from [<c02bfd50>] (bio_endio+0x54/0x58) [ 105.179096] [<c02bfcfc>] (bio_endio+0x0/0x58) from [<c030ff4c>] (req_bio_endio+0xd8/0xfc) [ 105.363043] [<c030fe74>] (req_bio_endio+0x0/0xfc) from [<c031009c>] (blk_update_request+0x12c/0x3b0) [ 105.553088] r6:c7d753e8 r5:00020000 r4:c7d95c80 [ 105.648141] [<c030ff70>] (blk_update_request+0x0/0x3b0) from [<c031033c>] (blk_update_bidi_request+0x1c/0x6c) [ 105.842643] [<c0310320>] (blk_update_bidi_request+0x0/0x6c) from [<c0310e14>] (blk_end_bidi_request+0x18/0x5c) [ 106.038614] r7:00000040 r6:00000000 r5:c7d753e8 r4:c01da400 [ 106.140453] [<c0310dfc>] (blk_end_bidi_request+0x0/0x5c) from [<c0310e6c>] (blk_end_request+0x14/0x18) [ 106.331397] r7:00000040 r6:c01ce400 r5:00000050 r4:c01da400 [ 106.432923] [<c0310e58>] (blk_end_request+0x0/0x18) from [<c03666d8>] (ide_end_rq+0x3c/0x40) [ 106.616840] [<c036669c>] (ide_end_rq+0x0/0x40) from [<c0366730>] (ide_complete_rq+0x54/0x60) [ 106.802931] [<c03666dc>] (ide_complete_rq+0x0/0x60) from [<c036a22c>] (task_pio_intr+0x16c/0x1f0) [ 106.992778] r4:c01da400 [ 107.074042] [<c036a0c0>] (task_pio_intr+0x0/0x1f0) from [<c03664b4>] (ide_intr+0x184/0x250) [ 107.258578] [<c0366330>] (ide_intr+0x0/0x250) from [<c0263160>] (handle_IRQ_event+0x30/0xf4) [ 107.445595] [<c0263130>] (handle_IRQ_event+0x0/0xf4) from [<c0264ebc>] (handle_edge_irq+0x104/0x164) [ 107.639557] r8:c0142c60 r7:c04d02f4 r6:00000073 r5:c01fb640 r4:c04b89e0 [ 107.750323] [<c0264db8>] (handle_edge_irq+0x0/0x164) from [<c0228850>] (sa1111_irq_handler+0xd4/0xf4) [ 107.944169] r7:00000000 r6:00000000 r5:00000032 r4:00000073 [ 108.047246] [<c022877c>] (sa1111_irq_handler+0x0/0xf4) from [<c0220078>] (asm_do_IRQ+0x78/0x9c) [ 108.236274] [<c0220000>] (asm_do_IRQ+0x0/0x9c) from [<c02208ec>] (__irq_svc+0x2c/0xa0) [ 108.421183] Exception stack(0xc7d7ff0c to 0xc7d7ff54) [ 108.520790] ff00: c04cd960 c7d7e000 00000000 20000013 0000001a [ 108.705437] ff20: c7d7e000 00000000 00000202 00000000 c04cd984 0000000a c7d7ff84 c7d7ff88 [ 108.888840] ff40: c7d7ff54 c024097c c0240694 60000013 ffffffff [ 108.991688] r5:fa050000 r4:ffffffff [ 109.078653] [<c0240640>] (__do_softirq+0x0/0x110) from [<c024097c>] (irq_exit+0x40/0x48) [ 109.260573] [<c024093c>] (irq_exit+0x0/0x48) from [<c022007c>] (asm_do_IRQ+0x7c/0x9c) [ 109.440820] [<c0220000>] (asm_do_IRQ+0x0/0x9c) from [<c0220ae8>] (__irq_usr+0x48/0xc0) [ 109.621346] Exception stack(0xc7d7ffb0 to 0xc7d7fff8) [ 109.717713] ffa0: 0008bac8 00000000 00000041 00000001 [ 109.899720] ffc0: 00000037 00063d00 00001000 00001c7a 00000000 00021490 401f5188 0008e9e8 [ 110.080452] ffe0: 00000001 bea9badc 00001fd0 40260814 60000010 ffffffff [ 110.186387] r5:fa050000 r4:ffffffff

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