September 2009 - U-Boot

[U-Boot] [PATCH 2/4 v2] s5pc1xx: support onenand driver
by Minkyu Kang 09 Oct '09

09 Oct '09

This patch includes the onenand driver for s5pc100 Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- drivers/mtd/onenand/Makefile | 2 + drivers/mtd/onenand/samsung.c | 626 +++++++++++++++++++++++++++++++++++ include/linux/mtd/onenand.h | 1 + include/linux/mtd/onenand_regs.h | 4 + include/linux/mtd/samsung_onenand.h | 132 ++++++++ 5 files changed, 765 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/onenand/samsung.c create mode 100644 include/linux/mtd/samsung_onenand.h diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile index 1d35a57..9317341 100644 --- a/drivers/mtd/onenand/Makefile +++ b/drivers/mtd/onenand/Makefile @@ -26,6 +26,8 @@ include $(TOPDIR)/config.mk LIB := $(obj)libonenand.a COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o +COBJS-$(CONFIG_S3C64XX) += samsung.o +COBJS-$(CONFIG_S5PC1XX) += samsung.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c new file mode 100644 index 0000000..03dfff8 --- /dev/null +++ b/drivers/mtd/onenand/samsung.c @@ -0,0 +1,626 @@ +/* + * S3C64XX/S5PC100 OneNAND driver at U-Boot + * + * Copyright (C) 2008-2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Implementation: + * Emulate the pseudo BufferRAM + */ + +#include <common.h> +#include <malloc.h> +#include <linux/mtd/compat.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include <linux/mtd/samsung_onenand.h> + +#include <asm/io.h> +#include <asm/errno.h> + +#ifdef ONENAND_DEBUG +#define DPRINTK(format, args...) \ +do { \ + printf("%s[%d]: " format "\n", __func__, __LINE__, ##args); \ +} while (0) +#else +#define DPRINTK(...) do { } while (0) +#endif + +#define ONENAND_ERASE_STATUS 0x00 +#define ONENAND_MULTI_ERASE_SET 0x01 +#define ONENAND_ERASE_START 0x03 +#define ONENAND_UNLOCK_START 0x08 +#define ONENAND_UNLOCK_END 0x09 +#define ONENAND_LOCK_START 0x0A +#define ONENAND_LOCK_END 0x0B +#define ONENAND_LOCK_TIGHT_START 0x0C +#define ONENAND_LOCK_TIGHT_END 0x0D +#define ONENAND_UNLOCK_ALL 0x0E +#define ONENAND_OTP_ACCESS 0x12 +#define ONENAND_SPARE_ACCESS_ONLY 0x13 +#define ONENAND_MAIN_ACCESS_ONLY 0x14 +#define ONENAND_ERASE_VERIFY 0x15 +#define ONENAND_MAIN_SPARE_ACCESS 0x16 +#define ONENAND_PIPELINE_READ 0x4000 + +#if defined(CONFIG_S3C64XX) +#define MAP_00 (0x0 << 24) +#define MAP_01 (0x1 << 24) +#define MAP_10 (0x2 << 24) +#define MAP_11 (0x3 << 24) + +#elif defined(CONFIG_S5PC1XX) +#define MAP_00 (0x0 << 26) +#define MAP_01 (0x1 << 26) +#define MAP_10 (0x2 << 26) +#define MAP_11 (0x3 << 26) + +#endif + +/* The 'addr' is byte address. It makes a 16-bit word */ +#define CMD_MAP_00(addr) (MAP_00 | ((addr) << 1)) +#define CMD_MAP_01(mem_addr) (MAP_01 | (mem_addr)) +#define CMD_MAP_10(mem_addr) (MAP_10 | (mem_addr)) +#define CMD_MAP_11(addr) (MAP_11 | ((addr) << 2)) + +struct s3c_onenand { + struct mtd_info *mtd; + + void __iomem *base; + void __iomem *ahb_addr; + + int bootram_command; + + void __iomem *page_buf; + void __iomem *oob_buf; + + unsigned int (*mem_addr)(int fba, int fpa, int fsa); + + struct samsung_onenand *reg; +}; + +static struct s3c_onenand *onenand; + +static int s3c_read_cmd(unsigned int cmd) +{ + return readl(onenand->ahb_addr + cmd); +} + +static void s3c_write_cmd(int value, unsigned int cmd) +{ + writel(value, onenand->ahb_addr + cmd); +} + +/* + * 1Gb: FBA[21:12] FPA[11:6] FSA[5:4] + * 2Gb: FBA[22:12] FPA[11:6] FSA[5:4] + * 4Gb: FBA[23:12] FPA[11:6] FSA[5:4] + */ +static unsigned int s3c64xx_mem_addr(int fba, int fpa, int fsa) +{ + return (fba << 12) | (fpa << 6) | (fsa << 4); +} + +/* + * 1Gb: FBA[22:13] FPA[12:7] FSA[6:5] + * 2Gb: FBA[23:13] FPA[12:7] FSA[6:5] + * 4Gb: FBA[24:13] FPA[12:7] FSA[6:5] + */ +static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa) +{ + return (fba << 13) | (fpa << 7) | (fsa << 5); +} + +static void s3c_onenand_reset(void) +{ + unsigned long timeout = 0x10000; + int stat; + + writel(ONENAND_MEM_RESET_COLD, &onenand->reg->MEM_RESET); + while (timeout--) { + stat = readl(&onenand->reg->INT_ERR_STAT); + if (stat & RST_CMP) + break; + } + stat = readl(&onenand->reg->INT_ERR_STAT); + writel(stat, &onenand->reg->INT_ERR_ACK); + + /* Clear interrupt */ + writel(0x0, &onenand->reg->INT_ERR_ACK); + /* Clear the ECC status */ + writel(0x0, &onenand->reg->ECC_ERR_STAT); +} + +static unsigned short s3c_onenand_readw(void __iomem *addr) +{ + struct onenand_chip *this = onenand->mtd->priv; + int reg = addr - this->base; + int word_addr = reg >> 1; + int value; + + /* It's used for probing time */ + switch (reg) { + case ONENAND_REG_MANUFACTURER_ID: + return readl(&onenand->reg->MANUFACT_ID); + case ONENAND_REG_DEVICE_ID: + return readl(&onenand->reg->DEVICE_ID); + case ONENAND_REG_VERSION_ID: + return readl(&onenand->reg->FLASH_VER_ID); + case ONENAND_REG_DATA_BUFFER_SIZE: + return readl(&onenand->reg->DATA_BUF_SIZE); + case ONENAND_REG_TECHNOLOGY: + return readl(&onenand->reg->TECH); + case ONENAND_REG_SYS_CFG1: + return readl(&onenand->reg->MEM_CFG); + + /* Used at unlock all status */ + case ONENAND_REG_CTRL_STATUS: + return 0; + + case ONENAND_REG_WP_STATUS: + return ONENAND_WP_US; + + default: + break; + } + + /* BootRAM access control */ + if (reg < ONENAND_DATARAM && onenand->bootram_command) { + if (word_addr == 0) + return readl(&onenand->reg->MANUFACT_ID); + if (word_addr == 1) + return readl(&onenand->reg->DEVICE_ID); + if (word_addr == 2) + return readl(&onenand->reg->FLASH_VER_ID); + } + + value = s3c_read_cmd(CMD_MAP_11(word_addr)) & 0xffff; + printk(KERN_INFO "s3c_onenand_readw: Illegal access" + " at reg 0x%x, value 0x%x\n", word_addr, value); + return value; +} + +static void s3c_onenand_writew(unsigned short value, void __iomem *addr) +{ + struct onenand_chip *this = onenand->mtd->priv; + int reg = addr - this->base; + int word_addr = reg >> 1; + + /* It's used for probing time */ + switch (reg) { + case ONENAND_REG_SYS_CFG1: + writel(value, &onenand->reg->MEM_CFG); + return; + + case ONENAND_REG_START_ADDRESS1: + case ONENAND_REG_START_ADDRESS2: + return; + + /* Lock/lock-tight/unlock/unlock_all */ + case ONENAND_REG_START_BLOCK_ADDRESS: + return; + + default: + break; + } + + /* BootRAM access control */ + if (reg < ONENAND_DATARAM) { + if (value == ONENAND_CMD_READID) { + onenand->bootram_command = 1; + return; + } + if (value == ONENAND_CMD_RESET) { + writel(ONENAND_MEM_RESET_COLD, + &onenand->reg->MEM_RESET); + onenand->bootram_command = 0; + return; + } + } + + printk(KERN_INFO "s3c_onenand_writew: Illegal access" + " at reg 0x%x, value 0x%x\n", word_addr, value); + + s3c_write_cmd(value, CMD_MAP_11(word_addr)); +} + +static int s3c_onenand_wait(struct mtd_info *mtd, int state) +{ + unsigned int flags = INT_ACT; + unsigned int stat, ecc; + unsigned long timeout = 0x100000; + + switch (state) { + case FL_READING: + flags |= BLK_RW_CMP | LOAD_CMP; + break; + case FL_WRITING: + flags |= BLK_RW_CMP | PGM_CMP; + break; + case FL_ERASING: + flags |= BLK_RW_CMP | ERS_CMP; + break; + case FL_LOCKING: + flags |= BLK_RW_CMP; + break; + default: + break; + } + + while (timeout--) { + stat = readl(&onenand->reg->INT_ERR_STAT); + if (stat & flags) + break; + } + + /* To get correct interrupt status in timeout case */ + stat = readl(&onenand->reg->INT_ERR_STAT); + writel(stat, &onenand->reg->INT_ERR_ACK); + + /* + * In the Spec. it checks the controller status first + * However if you get the correct information in case of + * power off recovery (POR) test, it should read ECC status first + */ + if (stat & LOAD_CMP) { + ecc = readl(&onenand->reg->ECC_ERR_STAT); + if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { + printk(KERN_INFO "%s: ECC error = 0x%04x\n", + __func__, ecc); + mtd->ecc_stats.failed++; + return -EBADMSG; + } + } + + if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) { + printk(KERN_INFO "%s: controller error = 0x%04x\n", + __func__, stat); + if (stat & LOCKED_BLK) + printk(KERN_INFO "%s: it's locked error = 0x%04x\n", + __func__, stat); + + return -EIO; + } + + return 0; +} + +static int s3c_onenand_command(struct mtd_info *mtd, int cmd, + loff_t addr, size_t len) +{ + struct onenand_chip *this = mtd->priv; + unsigned int *m, *s; + int fba, fpa, fsa = 0; + unsigned int mem_addr; + int i, mcount, scount; + int index; + + fba = (int) (addr >> this->erase_shift); + fpa = (int) (addr >> this->page_shift); + fpa &= this->page_mask; + + mem_addr = onenand->mem_addr(fba, fpa, fsa); + + switch (cmd) { + case ONENAND_CMD_READ: + case ONENAND_CMD_READOOB: + case ONENAND_CMD_BUFFERRAM: + ONENAND_SET_NEXT_BUFFERRAM(this); + default: + break; + } + + index = ONENAND_CURRENT_BUFFERRAM(this); + + /* + * Emulate Two BufferRAMs and access with 4 bytes pointer + */ + m = (unsigned int *) onenand->page_buf; + s = (unsigned int *) onenand->oob_buf; + + if (index) { + m += (this->writesize >> 2); + s += (mtd->oobsize >> 2); + } + + mcount = mtd->writesize >> 2; + scount = mtd->oobsize >> 2; + + switch (cmd) { + case ONENAND_CMD_READ: + /* Main */ + for (i = 0; i < mcount; i++) + *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + return 0; + + case ONENAND_CMD_READOOB: + writel(TSRF, &onenand->reg->TRANS_SPARE); + /* Main */ + for (i = 0; i < mcount; i++) + *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + + /* Spare */ + for (i = 0; i < scount; i++) + *s++ = s3c_read_cmd(CMD_MAP_01(mem_addr)); + + writel(0, &onenand->reg->TRANS_SPARE); + return 0; + + case ONENAND_CMD_PROG: + /* Main */ + for (i = 0; i < mcount; i++) + s3c_write_cmd(*m++, CMD_MAP_01(mem_addr)); + return 0; + + case ONENAND_CMD_PROGOOB: + writel(TSRF, &onenand->reg->TRANS_SPARE); + + /* Main - dummy write */ + for (i = 0; i < mcount; i++) + s3c_write_cmd(0xffffffff, CMD_MAP_01(mem_addr)); + + /* Spare */ + for (i = 0; i < scount; i++) + s3c_write_cmd(*s++, CMD_MAP_01(mem_addr)); + + writel(0, &onenand->reg->TRANS_SPARE); + return 0; + + case ONENAND_CMD_UNLOCK_ALL: + s3c_write_cmd(ONENAND_UNLOCK_ALL, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_ERASE: + s3c_write_cmd(ONENAND_ERASE_START, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_MULTIBLOCK_ERASE: + s3c_write_cmd(ONENAND_MULTI_ERASE_SET, CMD_MAP_10(mem_addr)); + return 0; + + case ONENAND_CMD_ERASE_VERIFY: + s3c_write_cmd(ONENAND_ERASE_VERIFY, CMD_MAP_10(mem_addr)); + return 0; + + default: + break; + } + + return 0; +} + +static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + int index = ONENAND_CURRENT_BUFFERRAM(this); + unsigned char *p; + + if (area == ONENAND_DATARAM) { + p = (unsigned char *) onenand->page_buf; + if (index == 1) + p += this->writesize; + } else { + p = (unsigned char *) onenand->oob_buf; + if (index == 1) + p += mtd->oobsize; + } + + return p; +} + +static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, + size_t count) +{ + unsigned char *p; + + p = s3c_get_bufferram(mtd, area); + memcpy(buffer, p + offset, count); + return 0; +} + +static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + unsigned char *p; + + p = s3c_get_bufferram(mtd, area); + memcpy(p + offset, buffer, count); + return 0; +} + +static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state) +{ + struct samsung_onenand *reg = (struct samsung_onenand *)onenand->base; + unsigned int flags = INT_ACT | LOAD_CMP; + unsigned int stat; + unsigned long timeout = 0x10000; + + while (timeout--) { + stat = readl(&reg->INT_ERR_STAT); + if (stat & flags) + break; + } + /* To get correct interrupt status in timeout case */ + stat = readl(&onenand->reg->INT_ERR_STAT); + writel(stat, &onenand->reg->INT_ERR_ACK); + + if (stat & LD_FAIL_ECC_ERR) { + s3c_onenand_reset(); + return ONENAND_BBT_READ_ERROR; + } + + if (stat & LOAD_CMP) { + int ecc = readl(&onenand->reg->ECC_ERR_STAT); + if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { + s3c_onenand_reset(); + return ONENAND_BBT_READ_ERROR; + } + } + + return 0; +} + +static void s3c_onenand_check_lock_status(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + unsigned int block, end; + int tmp; + + end = this->chipsize >> this->erase_shift; + + for (block = 0; block < end; block++) { + tmp = s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0))); + + if (readl(&onenand->reg->INT_ERR_STAT) & LOCKED_BLK) { + printf("block %d is write-protected!\n", block); + writel(LOCKED_BLK, &onenand->reg->INT_ERR_ACK); + } + } +} + +static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, + size_t len, int cmd) +{ + struct onenand_chip *this = mtd->priv; + int start, end, start_mem_addr, end_mem_addr; + + start = ofs >> this->erase_shift; + start_mem_addr = onenand->mem_addr(start, 0, 0); + end = start + (len >> this->erase_shift) - 1; + end_mem_addr = onenand->mem_addr(end, 0, 0); + + if (cmd == ONENAND_CMD_LOCK) { + s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(start_mem_addr)); + s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(end_mem_addr)); + } else { + s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(start_mem_addr)); + s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(end_mem_addr)); + } + + this->wait(mtd, FL_LOCKING); +} + +static void s3c_onenand_unlock_all(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + loff_t ofs = 0; + size_t len = this->chipsize; + + /* FIXME workaround */ + this->subpagesize = mtd->writesize; + mtd->subpage_sft = 0; + + if (this->options & ONENAND_HAS_UNLOCK_ALL) { + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); + + /* No need to check return value */ + this->wait(mtd, FL_LOCKING); + + /* Workaround for all block unlock in DDP */ + if (!ONENAND_IS_DDP(this)) { + s3c_onenand_check_lock_status(mtd); + return; + } + + /* All blocks on another chip */ + ofs = this->chipsize >> 1; + len = this->chipsize >> 1; + } + + s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); + + s3c_onenand_check_lock_status(mtd); +} + +#ifdef CONFIG_S3C64XX +static void s3c_set_width_regs(struct onenand_chip *this) +{ + int dev_id, density; + int fba, fpa, fsa; + int dbs_dfs; + + dev_id = DEVICE_ID0_REG; + + density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf; + dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP); + + fba = density + 7; + if (dbs_dfs) + fba--; /* Decrease the fba */ + fpa = 6; + if (density >= ONENAND_DEVICE_DENSITY_512Mb) + fsa = 2; + else + fsa = 1; + + DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu", + FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG, + DDP_DEVICE_REG); + + DPRINTK("mem_cfg0 0x%lx, sync mode %lu, " + "dev_page_size %lu, BURST LEN %lu", + MEM_CFG0_REG, SYNC_MODE_REG, + DEV_PAGE_SIZE_REG, BURST_LEN0_REG); + + DEV_PAGE_SIZE_REG = 0x1; + + FBA_WIDTH0_REG = fba; + FPA_WIDTH0_REG = fpa; + FSA_WIDTH0_REG = fsa; + DBS_DFS_WIDTH0_REG = dbs_dfs; +} +#endif + +void s3c_onenand_init(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + + onenand = malloc(sizeof(struct s3c_onenand)); + if (!onenand) + return; + + onenand->page_buf = malloc(SZ_4K * sizeof(char)); + if (!onenand->page_buf) + return; + memset(onenand->page_buf, 0xFF, SZ_4K); + + onenand->oob_buf = malloc(128 * sizeof(char)); + if (!onenand->oob_buf) + return; + memset(onenand->oob_buf, 0xFF, 128); + + onenand->mtd = mtd; + +#ifdef CONFIG_S5PC1XX + /* S5PC100 specific values */ + onenand->base = (void *) 0xE7100000; + onenand->ahb_addr = (void *) 0xB0000000; + onenand->mem_addr = s5pc100_mem_addr; +#else + onenand->base = (void *) 0x70100000; + onenand->ahb_addr = (void *) 0x20000000; + onenand->mem_addr = s3c64xx_mem_addr; +#endif + onenand->reg = (struct samsung_onenand *)onenand->base; + + this->read_word = s3c_onenand_readw; + this->write_word = s3c_onenand_writew; + + this->wait = s3c_onenand_wait; + this->bbt_wait = s3c_onenand_bbt_wait; + this->unlock_all = s3c_onenand_unlock_all; + this->command = s3c_onenand_command; + + this->read_bufferram = onenand_read_bufferram; + this->write_bufferram = onenand_write_bufferram; + + this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; +} diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 06f7baf..9a6f317 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -135,6 +135,7 @@ struct onenand_chip { #define ONENAND_HAS_CONT_LOCK (0x0001) #define ONENAND_HAS_UNLOCK_ALL (0x0002) #define ONENAND_HAS_2PLANE (0x0004) +#define ONENAND_RUNTIME_BADBLOCK_CHECK (0x0200) #define ONENAND_PAGEBUF_ALLOC (0x1000) #define ONENAND_OOBBUF_ALLOC (0x2000) diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index fc63380..07fed1c 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -121,6 +121,8 @@ #define ONENAND_CMD_LOCK_TIGHT (0x2C) #define ONENAND_CMD_UNLOCK_ALL (0x27) #define ONENAND_CMD_ERASE (0x94) +#define ONENAND_CMD_MULTIBLOCK_ERASE (0x95) +#define ONENAND_CMD_ERASE_VERIFY (0x71) #define ONENAND_CMD_RESET (0xF0) #define ONENAND_CMD_READID (0x90) @@ -184,7 +186,9 @@ * ECC Status Reigser FF00h (R) */ #define ONENAND_ECC_1BIT (1 << 0) +#define ONENAND_ECC_1BIT_ALL (0x5555) #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) +#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010) #endif /* __ONENAND_REG_H */ diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h new file mode 100644 index 0000000..d389606 --- /dev/null +++ b/include/linux/mtd/samsung_onenand.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2005-2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SAMSUNG_ONENAND_H__ +#define __SAMSUNG_ONENAND_H__ + +#include <asm/hardware.h> + +/* + * OneNAND Controller + */ + +#ifndef __ASSEMBLY__ +struct samsung_onenand { + unsigned long MEM_CFG; /* 0x0000 */ + unsigned char res1[0xc]; + unsigned long BURST_LEN; /* 0x0010 */ + unsigned char res2[0xc]; + unsigned long MEM_RESET; /* 0x0020 */ + unsigned char res3[0xc]; + unsigned long INT_ERR_STAT; /* 0x0030 */ + unsigned char res4[0xc]; + unsigned long INT_ERR_MASK; /* 0x0040 */ + unsigned char res5[0xc]; + unsigned long INT_ERR_ACK; /* 0x0050 */ + unsigned char res6[0xc]; + unsigned long ECC_ERR_STAT; /* 0x0060 */ + unsigned char res7[0xc]; + unsigned long MANUFACT_ID; /* 0x0070 */ + unsigned char res8[0xc]; + unsigned long DEVICE_ID; /* 0x0080 */ + unsigned char res9[0xc]; + unsigned long DATA_BUF_SIZE; /* 0x0090 */ + unsigned char res10[0xc]; + unsigned long BOOT_BUF_SIZE; /* 0x00A0 */ + unsigned char res11[0xc]; + unsigned long BUF_AMOUNT; /* 0x00B0 */ + unsigned char res12[0xc]; + unsigned long TECH; /* 0x00C0 */ + unsigned char res13[0xc]; + unsigned long FBA; /* 0x00D0 */ + unsigned char res14[0xc]; + unsigned long FPA; /* 0x00E0 */ + unsigned char res15[0xc]; + unsigned long FSA; /* 0x00F0 */ + unsigned char res16[0x3c]; + unsigned long SYNC_MODE; /* 0x0130 */ + unsigned char res17[0xc]; + unsigned long TRANS_SPARE; /* 0x0140 */ + unsigned char res18[0x3c]; + unsigned long ERR_PAGE_ADDR; /* 0x0180 */ + unsigned char res19[0x1c]; + unsigned long INT_PIN_EN; /* 0x01A0 */ + unsigned char res20[0x1c]; + unsigned long ACC_CLOCK; /* 0x01C0 */ + unsigned char res21[0x1c]; + unsigned long ERR_BLK_ADDR; /* 0x01E0 */ + unsigned char res22[0xc]; + unsigned long FLASH_VER_ID; /* 0x01F0 */ + unsigned char res23[0x6c]; + unsigned long WATCHDOG_CNT_LOW; /* 0x0260 */ + unsigned char res24[0xc]; + unsigned long WATCHDOG_CNT_HI; /* 0x0270 */ + unsigned char res25[0xc]; + unsigned long SYNC_WRITE; /* 0x0280 */ + unsigned char res26[0x1c]; + unsigned long COLD_RESET; /* 0x02A0 */ + unsigned char res27[0xc]; + unsigned long DDP_DEVICE; /* 0x02B0 */ + unsigned char res28[0xc]; + unsigned long MULTI_PLANE; /* 0x02C0 */ + unsigned char res29[0x1c]; + unsigned long TRANS_MODE; /* 0x02E0 */ + unsigned char res30[0x1c]; + unsigned long ECC_ERR_STAT2; /* 0x0300 */ + unsigned char res31[0xc]; + unsigned long ECC_ERR_STAT3; /* 0x0310 */ + unsigned char res32[0xc]; + unsigned long ECC_ERR_STAT4; /* 0x0320 */ + unsigned char res33[0x1c]; + unsigned long DEV_PAGE_SIZE; /* 0x0340 */ + unsigned char res34[0x4c]; + unsigned long INT_MON_STATUS; /* 0x0390 */ +}; +#endif + +#define ONENAND_MEM_RESET_HOT 0x3 +#define ONENAND_MEM_RESET_COLD 0x2 +#define ONENAND_MEM_RESET_WARM 0x1 + +#define CACHE_OP_ERR (1 << 13) +#define RST_CMP (1 << 12) +#define RDY_ACT (1 << 11) +#define INT_ACT (1 << 10) +#define UNSUP_CMD (1 << 9) +#define LOCKED_BLK (1 << 8) +#define BLK_RW_CMP (1 << 7) +#define ERS_CMP (1 << 6) +#define PGM_CMP (1 << 5) +#define LOAD_CMP (1 << 4) +#define ERS_FAIL (1 << 3) +#define PGM_FAIL (1 << 2) +#define INT_TO (1 << 1) +#define LD_FAIL_ECC_ERR (1 << 0) + +#define TSRF (1 << 0) + +/* common initialize function */ +extern void s3c_onenand_init(struct mtd_info *); + +#endif -- 1.5.4.3

6 12

[U-Boot] [PATCH 1/4 v2] s5pc1xx: support Samsung s5pc1xx SoC
by Minkyu Kang 09 Oct '09

09 Oct '09

This patch adds support for the Samsung s5pc100 and s5pc110 SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor. Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> --- cpu/arm_cortexa8/s5pc1xx/Makefile | 53 ++++++ cpu/arm_cortexa8/s5pc1xx/cache.c | 43 +++++ cpu/arm_cortexa8/s5pc1xx/clock.c | 302 ++++++++++++++++++++++++++++++ cpu/arm_cortexa8/s5pc1xx/cpu_info.c | 75 ++++++++ cpu/arm_cortexa8/s5pc1xx/reset.S | 47 +++++ cpu/arm_cortexa8/s5pc1xx/timer.c | 195 +++++++++++++++++++ include/asm-arm/arch-s5pc1xx/clk.h | 46 +++++ include/asm-arm/arch-s5pc1xx/clock.h | 100 ++++++++++ include/asm-arm/arch-s5pc1xx/cpu.h | 73 +++++++ include/asm-arm/arch-s5pc1xx/gpio.h | 127 +++++++++++++ include/asm-arm/arch-s5pc1xx/hardware.h | 63 ++++++ include/asm-arm/arch-s5pc1xx/i2c.h | 43 +++++ include/asm-arm/arch-s5pc1xx/interrupt.h | 40 ++++ include/asm-arm/arch-s5pc1xx/mem.h | 58 ++++++ include/asm-arm/arch-s5pc1xx/power.h | 42 ++++ include/asm-arm/arch-s5pc1xx/pwm.h | 65 +++++++ include/asm-arm/arch-s5pc1xx/uart.h | 53 ++++++ 17 files changed, 1425 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/Makefile create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/clock.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/cpu_info.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/reset.S create mode 100644 cpu/arm_cortexa8/s5pc1xx/timer.c create mode 100644 include/asm-arm/arch-s5pc1xx/clk.h create mode 100644 include/asm-arm/arch-s5pc1xx/clock.h create mode 100644 include/asm-arm/arch-s5pc1xx/cpu.h create mode 100644 include/asm-arm/arch-s5pc1xx/gpio.h create mode 100644 include/asm-arm/arch-s5pc1xx/hardware.h create mode 100644 include/asm-arm/arch-s5pc1xx/i2c.h create mode 100644 include/asm-arm/arch-s5pc1xx/interrupt.h create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h create mode 100644 include/asm-arm/arch-s5pc1xx/power.h create mode 100644 include/asm-arm/arch-s5pc1xx/pwm.h create mode 100644 include/asm-arm/arch-s5pc1xx/uart.h diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile new file mode 100644 index 0000000..e08d9d8 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS = reset.o + +COBJS += cache.o +COBJS += clock.o +COBJS += cpu_info.o +COBJS += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.c b/cpu/arm_cortexa8/s5pc1xx/cache.c new file mode 100644 index 0000000..8652a45 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cache.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/cache.h> + +void l2_cache_enable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} + +void l2_cache_disable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c new file mode 100644 index 0000000..da56fda --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/clock.h> + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + +#ifndef CONFIG_SYS_CLK_FREQ_C100 +#define CONFIG_SYS_CLK_FREQ_C100 12000000 +#endif +#ifndef CONFIG_SYS_CLK_FREQ_C110 +#define CONFIG_SYS_CLK_FREQ_C110 24000000 +#endif + +/* + * CONFIG_SYS_CLK_FREQ_C1xx should be defined as the input frequency + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ + */ +unsigned long get_pll_clk(int pllreg) +{ + struct s5pc100_clock *clk_c100 = + (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk_c110 = + (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + unsigned long r, m, p, s, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + if (cpu_is_s5pc110()) + r = readl(&clk_c110->APLL_CON); + else + r = readl(&clk_c100->APLL_CON); + break; + case MPLL: + if (cpu_is_s5pc110()) + r = readl(&clk_c110->MPLL_CON); + else + r = readl(&clk_c100->MPLL_CON); + break; + case EPLL: + if (cpu_is_s5pc110()) + r = readl(&clk_c110->EPLL_CON); + else + r = readl(&clk_c100->EPLL_CON); + break; + case HPLL: + if (cpu_is_s5pc110()) { + puts("s5pc110 don't use HPLL\n"); + return 0; + } + r = readl(&clk_c100->HPLL_CON); + break; + case VPLL: + if (cpu_is_s5pc100()) { + puts("s5pc100 don't use VPLL\n"); + return 0; + } + r = readl(&clk_c110->VPLL_CON); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + if (cpu_is_s5pc110()) { + /* + * APLL_CON: MIDV [25:16] + * MPLL_CON: MIDV [25:16] + * EPLL_CON: MIDV [24:16] + * VPLL_CON: MIDV [24:16] + */ + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + } else { + /* + * APLL_CON: MIDV [25:16] + * MPLL_CON: MIDV [23:16] + * EPLL_CON: MIDV [23:16] + * HPLL_CON: MIDV [23:16] + */ + if (pllreg == APLL) + mask = 0x3ff; + else + mask = 0x0ff; + } + m = (r >> 16) & mask; + + /* PDIV [13:8] */ + p = (r >> 8) & 0x3f; + /* SDIV [2:0] */ + s = r & 0x7; + + if (cpu_is_s5pc110()) { + freq = CONFIG_SYS_CLK_FREQ_C110; + if (pllreg == APLL) { + if (s < 1) + s = 1; + /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ + fout = m * (freq / (p * (1 << (s - 1)))); + } else + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + fout = m * (freq / (p * (1 << s))); + } else { + /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */ + freq = CONFIG_SYS_CLK_FREQ_C100; + fout = m * (freq / (p * (1 << s))); + } + + return fout; +} + +/* return ARMCORE frequency */ +unsigned long get_arm_clk(void) +{ + struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + unsigned long div; + unsigned long dout_apll, armclk; + unsigned int apll_ratio, arm_ratio; + + div = readl(&clk->DIV0); + if (cpu_is_s5pc110()) { + /* ARM_RATIO: don't use */ + arm_ratio = 0; + /* APLL_RATIO: [2:0] */ + apll_ratio = div & 0x7; + } else { + /* ARM_RATIO: [6:4] */ + arm_ratio = (div >> 4) & 0x7; + /* APLL_RATIO: [0] */ + apll_ratio = div & 0x1; + } + + dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + armclk = dout_apll / (arm_ratio + 1); + + return armclk; +} + +/* return FCLK frequency */ +unsigned long get_fclk(void) +{ + return get_pll_clk(APLL); +} + +/* return MCLK frequency */ +unsigned long get_mclk(void) +{ + return get_pll_clk(MPLL); +} + +/* s5pc100: return HCLKD0 frequency */ +unsigned long get_hclk(void) +{ + struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + unsigned long hclkd0; + uint div, d0_bus_ratio; + + div = readl(&clk->DIV0); + /* D0_BUS_RATIO: [10:8] */ + d0_bus_ratio = (div >> 8) & 0x7; + + hclkd0 = get_arm_clk() / (d0_bus_ratio + 1); + + return hclkd0; +} + +/* s5pc100: return PCLKD0 frequency */ +unsigned long get_pclkd0(void) +{ + struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + unsigned long pclkd0; + uint div, pclkd0_ratio; + + div = readl(&clk->DIV0); + /* PCLKD0_RATIO: [14:12] */ + pclkd0_ratio = (div >> 12) & 0x7; + + pclkd0 = get_hclk() / (pclkd0_ratio + 1); + + return pclkd0; +} + +/* s5pc100: return PCLKD1 frequency */ +unsigned long get_pclkd1(void) +{ + struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + unsigned long d1_bus, pclkd1; + uint div, d1_bus_ratio, pclkd1_ratio; + + div = readl(&clk->DIV0); + /* D1_BUS_RATIO: [14:12] */ + d1_bus_ratio = (div >> 12) & 0x7; + /* PCLKD1_RATIO: [18:16] */ + pclkd1_ratio = (div >> 16) & 0x7; + + /* ASYNC Mode */ + d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); + pclkd1 = d1_bus / (pclkd1_ratio + 1); + + return pclkd1; +} + +/* s5pc110: return HCLKs frequency */ +unsigned long get_hclk_sys(int dom) +{ + struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + unsigned long hclk; + unsigned int div; + unsigned int offset; + unsigned int hclk_sys_ratio; + + if (dom == CLK_M) + return get_hclk(); + + div = readl(&clk->DIV0); + + /* + * HCLK_MSYS_RATIO: [10:8] + * HCLK_DSYS_RATIO: [19:16] + * HCLK_PSYS_RATIO: [27:24] + */ + offset = 8 + (dom << 0x3); + + hclk_sys_ratio = (div >> offset) & 0xf; + + hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); + + return hclk; +} + +/* s5pc110: return PCLKs frequency */ +unsigned long get_pclk_sys(int dom) +{ + struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + unsigned long pclk; + unsigned int div; + unsigned int offset; + unsigned int pclk_sys_ratio; + + div = readl(&clk->DIV0); + + /* + * PCLK_MSYS_RATIO: [14:12] + * PCLK_DSYS_RATIO: [22:20] + * PCLK_PSYS_RATIO: [30:28] + */ + offset = 12 + (dom << 0x3); + + pclk_sys_ratio = (div >> offset) & 0x7; + + pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1); + + return pclk; +} + +/* return peripheral clock */ +unsigned long get_pclk(void) +{ + if (cpu_is_s5pc110()) + return get_pclk_sys(CLK_P); + else + return get_pclkd1(); +} + +/* return UCLK frequency */ +unsigned long get_uclk(void) +{ + return get_pll_clk(EPLL); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c new file mode 100644 index 0000000..eacacc8 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> + +/* Default is s5pc100 */ +unsigned int s5pc1xx_cpu_id = 0xC100; + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); + s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); + + return 0; +} +#endif + +u32 get_device_type(void) +{ + return s5pc1xx_cpu_id; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU:\tS5P%X@%sMHz\n", + s5pc1xx_cpu_id, strmhz(buf, get_arm_clk())); + if (cpu_is_s5pc110()) { + printf("\tAPLL = %s MHz, ", strmhz(buf, get_fclk())); + printf("MPLL = %s MHz, ", strmhz(buf, get_mclk())); + printf("EPLL = %s MHz\n", strmhz(buf, get_uclk())); + + printf("\tHclk: Msys %s MHz, ", + strmhz(buf, get_hclk_sys(CLK_M))); + printf("Dsys %7s MHz, ", strmhz(buf, get_hclk_sys(CLK_D))); + printf("Psys %7s MHz\n", strmhz(buf, get_hclk_sys(CLK_P))); + + printf("\tPclk: Msys %s MHz, ", + strmhz(buf, get_pclk_sys(CLK_M))); + printf("Dsys %7s MHz, ", strmhz(buf, get_pclk_sys(CLK_D))); + printf("Psys %7s MHz\n", strmhz(buf, get_pclk_sys(CLK_P))); + } else { + printf("\tFclk = %s MHz\n", strmhz(buf, get_fclk())); + printf("\tHclkD0 = %s MHz\n", strmhz(buf, get_hclk())); + printf("\tPclkD0 = %s MHz\n", strmhz(buf, get_pclkd0())); + printf("\tPclkD1 = %s MHz\n", strmhz(buf, get_pclkd1())); + } + + return 0; +} +#endif diff --git a/cpu/arm_cortexa8/s5pc1xx/reset.S b/cpu/arm_cortexa8/s5pc1xx/reset.S new file mode 100644 index 0000000..7f6ff9c --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/reset.S @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2009 Samsung Electronics. + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/cpu.h> + +#define S5PC100_SWRESET 0xE0200000 +#define S5PC110_SWRESET 0xE0102000 + +.globl reset_cpu +reset_cpu: + ldr r1, =S5PC1XX_PRO_ID + ldr r2, [r1] + ldr r4, =0x00010000 + and r4, r2, r4 + cmp r4, #0 + bne 110f + /* S5PC100 */ + ldr r1, =S5PC100_SWRESET + ldr r2, =0xC100 + b 200f +110: /* S5PC110 */ + ldr r1, =S5PC110_SWRESET + mov r2, #1 +200: + str r2, [r1] +_loop_forever: + b _loop_forever diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/cpu/arm_cortexa8/s5pc1xx/timer.c new file mode 100644 index 0000000..f3d94b8 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/timer.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Heungjun Kim <riverful.kim(a)samsung.com> + * Inki Dae <inki.dae(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/pwm.h> +#include <asm/arch/clk.h> + +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ +#define MUX4_DIV_SHIFT 16 + +#define TCON_TIMER4_SHIFT 20 + +static unsigned long count_value; + +/* Internal tick units */ +static unsigned long long timestamp; /* Monotonic incrementing timer */ +static unsigned long lastdec; /* Last decremneter snapshot */ + +/* macro to read the 16 bit timer */ +static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void) +{ + if (cpu_is_s5pc110()) + return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE; + else + return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE; +} + +int timer_init(void) +{ + struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + u32 val; + + /* + * @ PWM Timer 4 + * Timer Freq(HZ) = + * PCLK / { (prescaler_value + 1) * (divider_value) } + */ + + /* set prescaler : 16 */ + /* set divider : 2 */ + writel((PRESCALER_1 & 0xff) << 8, &timer->TCFG0); + writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->TCFG1); + + if (count_value == 0) { + /* reset initial value */ + /* count_value = 2085937.5(HZ) (per 1 sec)*/ + count_value = get_pclk() / ((PRESCALER_1 + 1) * + (MUX_DIV_2 + 1)); + + /* count_value / 100 = 20859.375(HZ) (per 10 msec) */ + count_value = count_value / 100; + } + + /* set count value */ + writel(count_value, &timer->TCNTB4); + lastdec = count_value; + + val = (readl(&timer->TCON) & ~(0x07 << TCON_TIMER4_SHIFT)) | + S5PC1XX_TCON4_AUTO_RELOAD; + + /* auto reload & manual update */ + writel(val | S5PC1XX_TCON4_UPDATE, &timer->TCON); + + /* start PWM timer 4 */ + writel(val | S5PC1XX_TCON4_START, &timer->TCON); + + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +/* delay x useconds */ +void udelay(unsigned long usec) +{ + unsigned long tmo, tmp; + + if (usec >= 1000) { + /* + * if "big" number, spread normalization + * to seconds + * 1. start to normalize for usec to ticks per sec + * 2. find number of "ticks" to wait to achieve target + * 3. finish normalize. + */ + tmo = usec / 1000; + tmo *= (CONFIG_SYS_HZ * count_value / 10); + tmo /= 1000; + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ * count_value / 10; + tmo /= (1000 * 1000); + } + + /* get current timestamp */ + tmp = get_timer(0); + + /* if setting this fordward will roll time stamp */ + /* reset "advancing" timestamp to 0, set lastdec value */ + /* else, set advancing stamp wake up time */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + /* loop till event */ + while (get_timer_masked() < tmo) + ; /* nop */ +} + +void reset_timer_masked(void) +{ + struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + + /* reset time */ + lastdec = readl(&timer->TCNTO4); + timestamp = 0; +} + +unsigned long get_timer_masked(void) +{ + struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + unsigned long now = readl(&timer->TCNTO4); + + if (lastdec >= now) + timestamp += lastdec - now; + else + timestamp += lastdec + count_value - now; + + lastdec = now; + + return timestamp; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h new file mode 100644 index 0000000..9c13a71 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_fclk(void); +unsigned long get_mclk(void); +unsigned long get_hclk(void); +unsigned long get_pclk(void); +unsigned long get_uclk(void); + +/*s5pc110 */ +#define CLK_M 0 +#define CLK_D 1 +#define CLK_P 2 + +unsigned long get_hclk_sys(int dom); +unsigned long get_pclk_sys(int dom); + +/* s5pc100 */ +unsigned long get_pclkd0(void); +unsigned long get_pclkd1(void); + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h new file mode 100644 index 0000000..f11c9ce --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +/* + * Clock control + */ + +/* Clock Register */ + +#ifndef __ASSEMBLY__ +struct s5pc100_clock { + unsigned long APLL_LOCK; + unsigned long MPLL_LOCK; + unsigned long EPLL_LOCK; + unsigned long HPLL_LOCK; + unsigned char res1[0xf0]; + unsigned long APLL_CON; + unsigned long MPLL_CON; + unsigned long EPLL_CON; + unsigned long HPLL_CON; + unsigned char res2[0xf0]; + unsigned long SRC0; + unsigned long SRC1; + unsigned long SRC2; + unsigned long SRC3; + unsigned char res3[0xf0]; + unsigned long DIV0; + unsigned long DIV1; + unsigned long DIV2; + unsigned long DIV3; + unsigned long DIV4; + unsigned char res4[0x1ec]; + unsigned long GATE_D00; + unsigned long GATE_D01; + unsigned long GATE_D02; + unsigned char res5[0x54]; + unsigned long GATE_SCLK0; + unsigned long GATE_SCLK1; +}; + +struct s5pc110_clock { + unsigned long APLL_LOCK; + unsigned char res1[0x4]; + unsigned long MPLL_LOCK; + unsigned char res2[0x4]; + unsigned long EPLL_LOCK; + unsigned char res3[0xc]; + unsigned long VPLL_LOCK; + unsigned char res4[0xdc]; + unsigned long APLL_CON; + unsigned char res5[0x4]; + unsigned long MPLL_CON; + unsigned char res6[0x4]; + unsigned long EPLL_CON; + unsigned char res7[0xc]; + unsigned long VPLL_CON; + unsigned char res8[0xdc]; + unsigned long SRC0; + unsigned long SRC1; + unsigned long SRC2; + unsigned long SRC3; + unsigned char res9[0xf0]; + unsigned long DIV0; + unsigned long DIV1; + unsigned long DIV2; + unsigned long DIV3; + unsigned long DIV4; + unsigned char res10[0x1ec]; + unsigned long GATE_D00; + unsigned long GATE_D01; + unsigned long GATE_D02; + unsigned char res11[0x54]; + unsigned long GATE_SCLK0; + unsigned long GATE_SCLK1; +}; +#endif + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h new file mode 100644 index 0000000..c7d7183 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/cpu.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _S5PC1XX_CPU_H +#define _S5PC1XX_CPU_H + +#include <asm/hardware.h> + +#define S5PC1XX_ADDR_BASE 0xe0000000 +#define S5P_ADDR(x) (S5PC1XX_ADDR_BASE + (x)) + +#define S5PC1XX_CLOCK_BASE 0xE0100000 +#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ + +/* Note that write the macro by address order */ +#define S5PC100_VIC0_BASE 0xE4000000 +#define S5PC100_VIC1_BASE 0xE4100000 +#define S5PC100_VIC2_BASE 0xE4200000 +#define S5PC100_SROMC_BASE 0xE7000000 +#define S5PC100_ONENAND_BASE 0xE7100000 +#define S5PC100_WATCHDOG_BASE 0xEA200000 + +#define S5PC110_WATCHDOG_BASE 0xE2700000 +#define S5PC110_SROMC_BASE 0xE8000000 +#define S5PC110_VIC0_BASE 0xF2000000 +#define S5PC110_VIC1_BASE 0xF2100000 +#define S5PC110_VIC2_BASE 0xF2200000 +#define S5PC110_VIC3_BASE 0xF2300000 + +/* + * Chip ID + */ +#define S5PC1XX_CHIP_ID(x) (0xE0000000 + (x)) +#define S5PC1XX_PRO_ID S5PC1XX_CHIP_ID(0) +#define S5PC1XX_OMR S5PC1XX_CHIP_ID(4) + +#ifndef __ASSEMBLY__ +/* CPU detection macros */ +extern unsigned int s5pc1xx_cpu_id; + +#define IS_SAMSUNG_TYPE(type, id) \ +static inline int is_##type(void) \ +{ \ + return (s5pc1xx_cpu_id == (id)) ? 1 : 0; \ +} + +IS_SAMSUNG_TYPE(s5pc100, 0xc100) +IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define cpu_is_s5pc100() is_s5pc100() +#define cpu_is_s5pc110() is_s5pc110() +#endif + +#endif /* _S5PC1XX_CPU_H */ diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h new file mode 100644 index 0000000..26d0950 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __S5PC1XX_GPIO_H +#define __S5PC1XX_GPIO_H + +/* GPIO Bank Base */ +#define S5PC100_GPIO_BASE(x) (0xE0300000 + (x)) +#define S5PC110_GPIO_BASE(x) (0xE0200000 + (x)) + +/* S5PC100 bank offset */ +#define S5PC100_GPIO_A0_OFFSET 0x000 +#define S5PC100_GPIO_A1_OFFSET 0x020 +#define S5PC100_GPIO_B_OFFSET 0x040 +#define S5PC100_GPIO_C_OFFSET 0x060 +#define S5PC100_GPIO_D_OFFSET 0x080 +#define S5PC100_GPIO_E0_OFFSET 0x0A0 +#define S5PC100_GPIO_E1_OFFSET 0x0C0 +#define S5PC100_GPIO_F0_OFFSET 0x0E0 +#define S5PC100_GPIO_F1_OFFSET 0x100 +#define S5PC100_GPIO_F2_OFFSET 0x120 +#define S5PC100_GPIO_F3_OFFSET 0x140 +#define S5PC100_GPIO_G0_OFFSET 0x160 +#define S5PC100_GPIO_G1_OFFSET 0x180 +#define S5PC100_GPIO_G2_OFFSET 0x1A0 +#define S5PC100_GPIO_G3_OFFSET 0x1C0 +#define S5PC100_GPIO_I_OFFSET 0x1E0 +#define S5PC100_GPIO_J0_OFFSET 0x200 +#define S5PC100_GPIO_J1_OFFSET 0x220 +#define S5PC100_GPIO_J2_OFFSET 0x240 +#define S5PC100_GPIO_J3_OFFSET 0x260 +#define S5PC100_GPIO_J4_OFFSET 0x280 +#define S5PC100_GPIO_K0_OFFSET 0x2A0 +#define S5PC100_GPIO_K1_OFFSET 0x2C0 +#define S5PC100_GPIO_K2_OFFSET 0x2E0 +#define S5PC100_GPIO_K3_OFFSET 0x300 +#define S5PC100_GPIO_L0_OFFSET 0x320 +#define S5PC100_GPIO_L1_OFFSET 0x340 +#define S5PC100_GPIO_L2_OFFSET 0x360 +#define S5PC100_GPIO_L3_OFFSET 0x380 +#define S5PC100_GPIO_L4_OFFSET 0x3A0 +#define S5PC100_GPIO_H0_OFFSET 0xC00 +#define S5PC100_GPIO_H1_OFFSET 0xC20 +#define S5PC100_GPIO_H2_OFFSET 0xC40 +#define S5PC100_GPIO_H3_OFFSET 0xC60 + +/* S5PC110 bank offset */ +#define S5PC110_GPIO_A0_OFFSET 0x000 +#define S5PC110_GPIO_A1_OFFSET 0x020 +#define S5PC110_GPIO_B_OFFSET 0x040 +#define S5PC110_GPIO_C0_OFFSET 0x060 +#define S5PC110_GPIO_C1_OFFSET 0x080 +#define S5PC110_GPIO_D0_OFFSET 0x0A0 +#define S5PC110_GPIO_D1_OFFSET 0x0C0 +#define S5PC110_GPIO_E0_OFFSET 0x0E0 +#define S5PC110_GPIO_E1_OFFSET 0x110 +#define S5PC110_GPIO_F0_OFFSET 0x120 +#define S5PC110_GPIO_F1_OFFSET 0x140 +#define S5PC110_GPIO_F2_OFFSET 0x160 +#define S5PC110_GPIO_F3_OFFSET 0x180 +#define S5PC110_GPIO_G0_OFFSET 0x1A0 +#define S5PC110_GPIO_G1_OFFSET 0x1C0 +#define S5PC110_GPIO_G2_OFFSET 0x1E0 +#define S5PC110_GPIO_G3_OFFSET 0x200 +#define S5PC110_GPIO_I_OFFSET 0x220 +#define S5PC110_GPIO_J0_OFFSET 0x240 +#define S5PC110_GPIO_J1_OFFSET 0x260 +#define S5PC110_GPIO_J2_OFFSET 0x280 +#define S5PC110_GPIO_J3_OFFSET 0x2A0 +#define S5PC110_GPIO_J4_OFFSET 0x2C0 +#define S5PC110_GPIO_MP0_1_OFFSET 0x2E0 +#define S5PC110_GPIO_MP0_2_OFFSET 0x300 +#define S5PC110_GPIO_MP0_3_OFFSET 0x320 +#define S5PC110_GPIO_MP0_4_OFFSET 0x340 +#define S5PC110_GPIO_MP0_5_OFFSET 0x360 +#define S5PC110_GPIO_MP0_6_OFFSET 0x380 +#define S5PC110_GPIO_MP0_7_OFFSET 0x3A0 +#define S5PC110_GPIO_MP1_0_OFFSET 0x3C0 +#define S5PC110_GPIO_MP1_1_OFFSET 0x3E0 +#define S5PC110_GPIO_MP1_2_OFFSET 0x410 +#define S5PC110_GPIO_MP1_3_OFFSET 0x420 +#define S5PC110_GPIO_MP1_4_OFFSET 0x440 +#define S5PC110_GPIO_MP1_5_OFFSET 0x460 +#define S5PC110_GPIO_MP1_6_OFFSET 0x480 +#define S5PC110_GPIO_MP1_7_OFFSET 0x4A0 +#define S5PC110_GPIO_MP1_8_OFFSET 0x4C0 +#define S5PC110_GPIO_MP2_0_OFFSET 0x4E0 +#define S5PC110_GPIO_MP2_1_OFFSET 0x510 +#define S5PC110_GPIO_MP2_2_OFFSET 0x520 +#define S5PC110_GPIO_MP2_3_OFFSET 0x540 +#define S5PC110_GPIO_MP2_4_OFFSET 0x560 +#define S5PC110_GPIO_MP2_5_OFFSET 0x580 +#define S5PC110_GPIO_MP2_6_OFFSET 0x5A0 +#define S5PC110_GPIO_MP2_7_OFFSET 0x5C0 +#define S5PC110_GPIO_MP2_8_OFFSET 0x5E0 +#define S5PC110_GPIO_H0_OFFSET 0xC00 +#define S5PC110_GPIO_H1_OFFSET 0xC20 +#define S5PC110_GPIO_H2_OFFSET 0xC40 +#define S5PC110_GPIO_H3_OFFSET 0xC60 + +/* GPIO bank Offset */ +#define S5PC1XX_GPIO_CON_OFFSET 0x0 +#define S5PC1XX_GPIO_DAT_OFFSET 0x4 +#define S5PC1XX_GPIO_PULL_OFFSET 0x8 +#define S5PC1XX_GPIO_DRV_OFFSET 0xc +#define S5PC1XX_GPIO_PDNCON_OFFSET 0x10 +#define S5PC1XX_GPIO_PDNPULL_OFFSET 0x14 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/hardware.h b/include/asm-arm/arch-s5pc1xx/hardware.h new file mode 100644 index 0000000..ca95c3d --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/hardware.h @@ -0,0 +1,63 @@ +/* + * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_HARDWARE_H_ +#define _ARCH_HARDWARE_H_ + +#include <asm/sizes.h> + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long)(Data)) + +#define __REG(x) (*(vu_long *)(x)) +#define __REGl(x) (*(vu_long *)(x)) +#define __REGw(x) (*(vu_short *)(x)) +#define __REGb(x) (*(vu_char *)(x)) +#define __REG2(x, y) (*(vu_long *)((x) + (y))) +#else +#define UData(Data) (Data) + +#define __REG(x) (x) +#define __REGl(x) (x) +#define __REGw(x) (x) +#define __REGb(x) (x) +#define __REG2(x, y) ((x) + (y)) +#endif + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData(1) << FSize(Field)) - 1) << FShft(Field)) +#define FAlnMsk(Field) ((UData(1) << FSize(Field)) - 1) +#define F1stBit(Field) (UData(1) << FShft(Field)) + +#define FClrBit(Data, Bit) (Data = (Data & ~(Bit))) +#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field))) + +#define FInsrt(Value, Field) \ + (UData(Value) << FShft(Field)) + +#define FExtr(Data, Field) \ + ((UData(Data) >> FShft(Field)) & FAlnMsk(Field)) + +#endif /* _ARCH_HARDWARE_H_ */ diff --git a/include/asm-arm/arch-s5pc1xx/i2c.h b/include/asm-arm/arch-s5pc1xx/i2c.h new file mode 100644 index 0000000..6c7d3b6 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Kyungnin Park <kyungmin.park(a)samsung.com> + * + * based on s3c24x0_i2c.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_I2C_H_ +#define __ASM_ARCH_I2C_H_ + +/* I2C */ +#define S5PC100_I2C0_BASE 0xEC100000 +#define S5PC100_I2C1_BASE 0xEC200000 +#define S5PC110_I2C0_BASE 0xE1800000 +#define S5PC110_I2C2_BASE 0xE1A00000 + +#ifndef __ASSEMBLY__ +struct s5pc1xx_i2c { + unsigned long IICCON; + unsigned long IICSTAT; + unsigned long IICADD; + unsigned long IICDS; + unsigned long IICLC; +}; +#endif + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/interrupt.h b/include/asm-arm/arch-s5pc1xx/interrupt.h new file mode 100644 index 0000000..a3c8680 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/interrupt.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_INTERRUPT_H_ +#define __ASM_ARM_ARCH_INTERRUPT_H_ + +/* Vector Interrupt Offset */ +#define VIC_IRQSTATUS_OFFSET 0x0 +#define VIC_FIQSTATUS_OFFSET 0x4 +#define VIC_RAWINTR_OFFSET 0x8 +#define VIC_INTSELECT_OFFSET 0xc +#define VIC_INTENABLE_OFFSET 0x10 +#define VIC_INTENCLEAR_OFFSET 0x14 +#define VIC_SOFTINT_OFFSET 0x18 +#define VIC_SOFTINTCLEAR_OFFSET 0x1c +#define VIC_PROTECTION_OFFSET 0x20 +#define VIC_SWPRIORITYMASK_OFFSET 0x24 +#define VIC_PRIORITYDAISY_OFFSET 0x28 +#define VIC_INTADDRESS_OFFSET 0xf00 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h new file mode 100644 index 0000000..4b06aaf --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/mem.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_MEM_H_ +#define __ASM_ARM_ARCH_MEM_H_ + +/* + * SROMC Controller + */ +/* DRAM Memory Controller */ +#define S5PC100_DMC_BASE 0xE6000000 +#define S5PC110_DMC0_BASE 0xF0000000 +#define S5PC110_DMC1_BASE 0xF1400000 + +/* DMC offset */ +#define CONCONTROL_OFFSET 0x00 +#define MEMCONTROL_OFFSET 0x04 +#define MEMCONFIG0_OFFSET 0x08 +#define MEMCONFIG1_OFFSET 0x0c +#define DIRECTCMD_OFFSET 0x10 +#define PRECHCONFIG_OFFSET 0x14 +#define PHYCONTROL0_OFFSET 0x18 +#define PHYCONTROL1_OFFSET 0x1c +#define PHYCONTROL2_OFFSET 0x20 +#define PWRDNCONFIG_OFFSET 0x28 +#define TIMINGAREF_OFFSET 0x30 +#define TIMINGROW_OFFSET 0x34 +#define TIMINGDATA_OFFSET 0x38 +#define TIMINGPOWER_OFFSET 0x3c +#define PHYSTATUS0_OFFSET 0x40 +#define PHYSTATUS1_OFFSET 0x44 +#define CHIP0STATUS_OFFSET 0x48 +#define CHIP1STATUS_OFFSET 0x4c +#define AREFSTATUS_OFFSET 0x50 +#define MRSTATUS_OFFSET 0x54 +#define PHYTEST0_OFFSET 0x58 +#define PHYTEST1_OFFSET 0x5c + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h new file mode 100644 index 0000000..57e2a2b --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/power.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_POWER_H_ +#define __ASM_ARM_ARCH_POWER_H_ + +/* + * Power control + */ +#define S5PC100_OTHERS 0xE0108200 +#define S5PC100_RST_STAT 0xE0108300 +#define S5PC100_SLEEP_WAKEUP (1 << 3) +#define S5PC100_WAKEUP_STAT 0xE0108304 +#define S5PC100_INFORM0 0xE0108400 + +#define S5PC110_RST_STAT 0xE010A000 +#define S5PC110_SLEEP_WAKEUP (1 << 3) +#define S5PC110_WAKEUP_STAT 0xE010C200 +#define S5PC110_OTHERS 0xE010E000 +#define S5PC110_USB_PHY_CON 0xE010E80C +#define S5PC110_INFORM0 0xE010F000 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h new file mode 100644 index 0000000..85c63d7 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +/* + * PWM Timer + */ +#define S5PC100_PWMTIMER_BASE 0xEA000000 +#define S5PC110_PWMTIMER_BASE 0xE2500000 + +/* PWM timer addressing */ +#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE +#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE + +/* Interval mode(Auto Reload) of PWM Timer 4 */ +#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +/* Update TCNTB4 */ +#define S5PC1XX_TCON4_UPDATE (1 << 21) +/* start bit of PWM Timer 4 */ +#define S5PC1XX_TCON4_START (1 << 20) + +#ifndef __ASSEMBLY__ +struct s5pc1xx_timer { + unsigned long TCFG0; + unsigned long TCFG1; + unsigned long TCON; + unsigned long TCNTB0; + unsigned long TCMPB0; + unsigned long TCNTO0; + unsigned long TCNTB1; + unsigned long TCMPB1; + unsigned long TCNTO1; + unsigned long TCNTB2; + unsigned long TCMPB2; + unsigned long TCNTO2; + unsigned long TCNTB3; + unsigned long res1; + unsigned long TCNTO3; + unsigned long TCNTB4; + unsigned long TCNTO4; + unsigned long TINTCSTAT; +}; +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h new file mode 100644 index 0000000..1a2ca41 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/uart.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Heungjun Kim <riverful.kim(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +/* + * UART + */ +/* uart base address */ +#define S5PC100_PA_UART 0xEC000000 +#define S5PC110_PA_UART 0xE2900000 + +#ifndef __ASSEMBLY__ +struct s5pc1xx_uart { + unsigned long ULCON; + unsigned long UCON; + unsigned long UFCON; + unsigned long UMCON; + unsigned long UTRSTAT; + unsigned long UERSTAT; + unsigned long UFSTAT; + unsigned long UMSTAT; + unsigned char UTXH; + unsigned char res1[3]; + unsigned char URXH; + unsigned char res2[3]; + unsigned long UBRDIV; + unsigned short UDIVSLOT; + unsigned char res3[2]; +}; +#endif /* __ASSEMBLY__ */ + +#endif -- 1.5.4.3

4 8

[U-Boot] [PATCH] This modification will make the binay of smdk6400 nand spl in correct size
by sun peng 08 Oct '09

08 Oct '09

When I'm playing with u-boot I found that the size of smdk6400 nand spl binary image can't pad to 4K. So I make some minor change to the config.mk file to achieve the correct padding size. Signed-off-by: Sunpeng <sunnycamel(a)gmail.com> --- nand_spl/board/samsung/smdk6400/config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/nand_spl/board/samsung/smdk6400/config.mk b/nand_spl/board/samsung/smdk6400/config.mk index 4b16230..013dec9 100644 --- a/nand_spl/board/samsung/smdk6400/config.mk +++ b/nand_spl/board/samsung/smdk6400/config.mk @@ -33,7 +33,7 @@ include $(TOPDIR)/board/$(BOARDDIR)/config.mk # PAD_TO used to generate a 4kByte binary needed for the combined image # -> PAD_TO = TEXT_BASE + 4096 -PAD_TO := $(shell expr $$[$(TEXT_BASE) + 4096]) +PAD_TO := $(shell expr $(TEXT_BASE) + 4096) ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -- 1.6.0.4

2 1

[U-Boot] [PATCH] sbc8641d: fix LAW so board doesn't hang on DDR init
by Paul Gortmaker 08 Oct '09

08 Oct '09

All versions between now and since this commit: commit bd76729bcbfd64b5d016a9b936f058931fc06eaf MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default will fail to allow the SBC8641D to get past DDR init, because the LAW config was overlapping. Eventually this board will do SPD EEPROM config, but for now this gets the board working again. Signed-off-by: Paul Gortmaker <paul.gortmaker(a)windriver.com> --- board/sbc8641d/law.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index 760c693..d20fa51 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -44,14 +44,17 @@ struct law_entry law_table[] = { +#if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), +#endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; -- 1.6.5.rc1

2 1

[U-Boot] Xilinx LL temac update
by monstr＠monstr.eu 07 Oct '09

07 Oct '09

Hi Ben, I updated LL-temac driver - all fixes are there. Ad to your point Microblaze uses only one ethernet core. It is possible to use a lot of IPs but I don't have board like this to test it that's why I don't want change it. If you find any other problem please let me know. If is OK - I'll create net branch with these changes (LL_TEMAC/Emaclite + removing old Emac driver) Thanks, Michal

3 8

[U-Boot] [PATCH v2] TI: OMAP3: Remove SZ_xx references
by s-paulraj＠ti.com 07 Oct '09

07 Oct '09

From: Sandeep Paulraj <s-paulraj(a)ti.com> This patch removes dependency on the sizes.h header file and removes all references to SZ_xx. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- Changes since the initial version include fixing an error noticed by Wolfgang and using shift operators in ARM CORTEX A8 code. cpu/arm_cortexa8/omap3/mem.c | 6 +++--- cpu/arm_cortexa8/omap3/sys_info.c | 2 +- include/configs/devkit8000.h | 15 +++++++-------- include/configs/omap3_beagle.h | 15 +++++++-------- include/configs/omap3_evm.h | 15 +++++++-------- include/configs/omap3_overo.h | 15 +++++++-------- include/configs/omap3_pandora.h | 15 +++++++-------- include/configs/omap3_zoom1.h | 15 +++++++-------- include/configs/omap3_zoom2.h | 15 +++++++-------- 9 files changed, 53 insertions(+), 60 deletions(-) diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 079c848..b4dec39 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -92,7 +92,7 @@ void make_cs1_contiguous(void) u32 size, a_add_low, a_add_high; size = get_sdr_cs_size(CS0); - size /= SZ_32M; /* find size to offset CS1 */ + size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ a_add_high = (size & 3) << 8; /* set up low field */ a_add_low = (size & 0x3C) >> 2; /* set up high field */ writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); @@ -249,7 +249,7 @@ void gpmc_init(void) enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; - f_sec = SZ_128K; + f_sec = (128 << 10); /* 128 KiB */ /* env setup */ boot_flash_base = base; boot_flash_off = f_off; @@ -265,7 +265,7 @@ void gpmc_init(void) enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; - f_sec = SZ_128K; + f_sec = (128 << 10); /* 128 KiB */ /* env setup */ boot_flash_base = base; boot_flash_off = f_off; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 765aaf2..31b2003 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -124,7 +124,7 @@ u32 get_sdr_cs_size(u32 cs) /* get ram size field */ size = readl(&sdrc_base->cs[cs].mcfg) >> 8; size &= 0x3FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ return size; } diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cd40da6..d2cfd8f 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -30,7 +30,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* High Level Configuration Options */ #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ @@ -59,9 +58,9 @@ #define CONFIG_REVISION_TAG 1 /* Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -270,16 +269,16 @@ #define CONFIG_SYS_HZ 1000 /* The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_128M /* at least 128 meg */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -288,7 +287,7 @@ /* NAND and environment organization */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 61629f8..e94fbd7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -27,7 +27,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -62,9 +61,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -238,10 +237,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -249,7 +248,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -268,7 +267,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9f0f34b..ee424f7 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -32,7 +32,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -67,9 +66,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ /* @@ -230,10 +229,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -241,7 +240,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -260,7 +259,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 07a031b..20450f0 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -54,9 +53,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -223,10 +222,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -234,7 +233,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -253,7 +252,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 1cfd7e9..c71baa2 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -22,7 +22,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -57,9 +56,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -227,10 +226,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -238,7 +237,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -257,7 +256,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 61a41e7..97fe989 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -28,7 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -63,9 +62,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -235,10 +234,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -246,7 +245,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -265,7 +264,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 03f92f5..e8086ef 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -29,7 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * High Level Configuration Options @@ -64,9 +63,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ /* @@ -200,10 +199,10 @@ * * The stack sizes are set up in start.S using these settings */ -#define CONFIG_STACKSIZE SZ_128K +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K -#define CONFIG_STACKSIZE_FIQ SZ_4K +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -211,7 +210,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -230,7 +229,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base -- 1.6.0.4

2 1

[U-Boot] [PATCH] relocation: Do not relocate NULL pointers.
by Joakim Tjernlund 06 Oct '09

06 Oct '09

NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund(a)transmode.se> --- I have only tested this on 83xx and on a somewhat older u-boot. The change is exactly the same on all PowerPC platforms though. cpu/mpc512x/start.S | 6 ++++-- cpu/mpc5xx/start.S | 6 ++++-- cpu/mpc5xxx/start.S | 6 ++++-- cpu/mpc8220/start.S | 6 ++++-- cpu/mpc824x/start.S | 6 ++++-- cpu/mpc8260/start.S | 6 ++++-- cpu/mpc83xx/start.S | 6 ++++-- cpu/mpc85xx/start.S | 6 ++++-- cpu/mpc86xx/start.S | 6 ++++-- cpu/mpc8xx/start.S | 6 ++++-- 10 files changed, 40 insertions(+), 20 deletions(-) diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682d..a00e045 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -609,15 +609,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 106935c..85ea7a8 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -458,15 +458,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 6b1162a..eb42939 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -684,15 +684,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 3abc619..af9472d 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -649,15 +649,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 39325cd..750457b 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 379f2fb..edb95e6 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -909,15 +909,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 26e3106..ee4b862 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -957,16 +957,18 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b #ifndef CONFIG_NAND_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 4f7236f..d56003b 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -932,15 +932,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 63cc8db..e65f1c0 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -733,15 +733,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 8864c37..e84326e 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 -- 1.6.4.4

7 38

[U-Boot] [PATCH 0/3 v3] New MIIPHYBB implementation with multi-bus support
by Luigi 'Comio' Mantellini 05 Oct '09

05 Oct '09

From: Luigi 'Comio' Mantellini <luigi.mantellini(a)idf-hit.com> This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to support an arbitrary number of buses. This feature is useful when your board uses different mii buses for different phys and all (or a part) of these buses are implemented via bit-banging mode. The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver CONFIG_BITBANGMII_MULTI - Enable the multi bus support If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs to define the following macros: MII_INIT - Generic cod to enable the MII bus (like gpios setup) MDIO_DECLARE - Declaration needed to access to the MDIO pin MDIO_ACTIVE - Activate the MDIO pin as out pin MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin MDIO_READ - Read the MDIO pin MDIO(v) - Write v on the MDIO pin MDC_DECLARE - Declaration needed to access to the MDC pin MDC(v) - Write v on the MDC pin The previous macros make the driver compatible with the previous version (that didn't support the multi-bus). When the CONFIG_BITBANGMII_MULTI is defined, the board code needs to fill the bbmiibusses[] array with a record for each required bus. The record (struct bbmiibus) has the following fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name int (*init)() - Initialization function called at startup time (just before the Ethernet initialization) int (*mdio_active)() - Activate the MDIO pin as output int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin int (*set_mdio)() - Write the MDIO pin int (*get_mdio)() - Read the MDIO pin int (*set_mdc)() - Write the MDC pin int (*delay)() - Delay function void *priv - Private data used by board specific code The board code will look like: struct bbmiibus bbmiibusses[] = { { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... }, { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... }, ... }; Patch Changelog: v1 -- First (broken) release v2 -- Fix some typos and disable callbacks pointers relacation (if CONFIG_RELOC_FIXUP_WORKS is not defined) v3 -- Do not relocate NULL pointers Luigi 'Comio' Mantellini (3): Bit-banged MII driver with multi-bus support. Add bb_miiphy_init call before any ethernet bring-up code. Update all board to support new bbmiiphy driver (with multibus support) drivers/net/phy/miiphybb.c | 324 +++++++++++++++++++++++++++++------------- include/configs/ISPAN.h | 3 + include/configs/MPC8260ADS.h | 2 + include/configs/MPC8266ADS.h | 3 + include/configs/MPC8560ADS.h | 3 + include/configs/Rattler.h | 3 + include/configs/SBC8540.h | 3 + include/configs/TQM8272.h | 2 + include/configs/VoVPN-GW.h | 3 + include/configs/ZPC1900.h | 3 + include/configs/ep8248.h | 3 + include/configs/ep82xxm.h | 3 + include/configs/gw8260.h | 3 + include/configs/hymod.h | 9 ++ include/configs/muas3001.h | 3 + include/configs/ppmc8260.h | 3 + include/configs/sacsng.h | 3 + include/configs/sbc8260.h | 3 + include/configs/sbc8560.h | 3 + include/miiphy.h | 22 +++ lib_arm/board.c | 3 + lib_avr32/board.c | 3 + lib_blackfin/board.c | 3 + lib_i386/board.c | 3 + lib_m68k/board.c | 3 + lib_mips/board.c | 3 + lib_ppc/board.c | 4 +- lib_sh/board.c | 3 + lib_sparc/board.c | 3 + 29 files changed, 335 insertions(+), 97 deletions(-)

5 13

[U-Boot] build failure on denx top
by Aggrwal Poonam-B10812 05 Oct '09

05 Oct '09

Hello All, On denx tree master branch , u-boot build is failing for 83xx and 85xx platforms. Build log make[1]: Entering directory `/project/p1020_swe_nobackup/usr/poonam/p20x0/denx/latest/mirrors.u-boot /u-boot/examples/standalone' /opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linu x-gnuspe/bin/powerpc-none-linux-gnuspe-gcc -g -Os -fPIC -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xFE000000 -I/project/p1020_swe_nobackup/usr/poonam/p20x0/denx/latest/mirrors.u-boo t/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linu x-gnuspe/lib/gcc/powerpc-none-linux-gnuspe/4.3.2/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC83xx -DCONFIG_E300 -ffixed-r2 -msoft-float -Wall -Wstrict-prototypes -fno-stack-protector -g -Os -fPIC -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xFE000000 -I/project/p1020_swe_nobackup/usr/poonam/p20x0/denx/latest/mirrors.u-boo t/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/freescale/usr/local/gcc-4.3.74-eglibc-2.8.74-dp-2/powerpc-none-linu x-gnuspe/lib/gcc/powerpc-none-linux-gnuspe/4.3.2/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC83xx -DCONFIG_E300 -ffixed-r2 -msoft-float -I.. -Bstatic -T u-boot.lds -n -Ttext 0xFE000000 -o .c powerpc-none-linux-gnuspe-gcc: 0xFE000000: No such file or directory powerpc-none-linux-gnuspe-gcc: no input files make[1]: *** [.c] Error 1 make[1]: Leaving directory `/project/p1020_swe_nobackup/usr/poonam/p20x0/denx/latest/mirrors.u-boot /u-boot/examples/standalone' make: *** [examples/standalone] Error 2 When I remove the following commit, things work fine. From 557555fe0b82940ba7cc69f81d31d6ef4d4933b4 Mon Sep 17 00:00:00 2001 From: Mike Frysinger <vapier(a)gentoo.org <mailto:vapier@gentoo.org> > Date: Fri, 4 Sep 2009 19:54:45 -0400 Subject: [PATCH] standalone: convert to kbuild style Clean up the arch/cpu/board/config checks as well as redundant setting of srec/bin variables by using the kbuild VAR-$(...) style. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> I am facing it for FSL 83xx and 85xx platforms. Is anybody else also seeing this build failure. Regards Poonam

2 2

[U-Boot] [PATCH v0 1/2] u-boot-2009.08 NET: Move MDIO regs out of TSEC Space
by Sandeep Gopalpet 05 Oct '09

05 Oct '09

Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different Signed-off-by: Sandeep Gopalpet <sandeep.kumar(a)freescale.com> --- drivers/net/tsec.c | 20 ++++++++-------- include/asm-ppc/immap_85xx.h | 10 ++++++++ include/tsec.h | 48 +++++++++++++++++++++++++++++++---------- 3 files changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5c3d261..2ad033e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -83,7 +83,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -136,6 +136,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -222,7 +223,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -245,7 +246,7 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) { uint value; @@ -290,11 +291,11 @@ static void tsec_configure_serdes(struct tsec_private *priv) { /* Access TBI PHY registers at given TSEC register offset as opposed to the * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -306,12 +307,11 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -739,7 +739,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -1772,7 +1772,7 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 100dfe1..dc82f49 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1935,4 +1935,14 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +/* TSEC and MDIO OFFSETS */ +#define CONFIG_SYS_TSEC1_OFFSET (0x24000) +#define TSEC_SIZE (0x01000) + +#define CONFIG_SYS_MDIO1_OFFSET (0x24520) +#define MDIO_OFFSET (0x01000) + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_85xx__*/ diff --git a/include/tsec.h b/include/tsec.h index 0ac3034..342c07e 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao(a)motorola.com) * author Andy Fleming @@ -24,18 +24,34 @@ #define CONFIG_SYS_TSEC1_OFFSET (0x24000) #endif -#define TSEC_SIZE 0x01000 +#ifndef TSEC_SIZE + #define TSEC_SIZE 0x01000 +#endif + +#ifndef CONFIG_SYS_MDIO1_OFFSET + #define CONFIG_SYS_MDIO1_OFFSET (0x24520) +#endif + +#ifndef MDIO_OFFSET + #define MDIO_OFFSET 0x01000 +#endif /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ || defined(CONFIG_MPC83xx) +#ifndef TSEC_BASE_ADDR #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #endif +#ifndef MDIO_BASE_ADDR + #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#endif +#endif #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET ), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS \ @@ -44,7 +60,8 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -461,6 +478,16 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; +typedef struct tsec_mdio +{ + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ +} tsec_mdio_t; + typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -526,12 +553,7 @@ typedef struct tsec uint res51c; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ + uint resmdio[6]; uint res538; @@ -571,7 +593,8 @@ typedef struct tsec struct tsec_private { volatile tsec_t *regs; - volatile tsec_t *phyregs; + volatile tsec_mdio_t *phyregs; + volatile tsec_mdio_t *phyregs_sgmii; struct phy_info *phyinfo; uint phyaddr; u32 flags; @@ -630,7 +653,8 @@ struct phy_info { struct tsec_info_struct { tsec_t *regs; - tsec_t *miiregs; + tsec_mdio_t *miiregs; + tsec_mdio_t *miiregs_sgmii; char *devname; unsigned int phyaddr; u32 flags; -- 1.5.2.2

4 5