September 2009 - U-Boot

[U-Boot] autoscr command
by Berns 04 Oct '09

04 Oct '09

Hi, i use the autoscr command to store further information in a NAND at the first start. After this it modify the bootcmd and save the enviroment and the last command should restart the device. The script works fine but "saveenv" seams to abort the script file. I have used different memory location, i have checked the memory contents and i have placed saveenv at the beginning, middle and at the end of the script. It allways abort after "saveenv". I use Uboot 2008.10. Thanks for any advise. Kind Regards Rainer Berns BEKA Elektronik Rainer Berns & Rudolf Kauls GbR Siemensstrasse 29 50374 Erftstadt Tel.: +49 2235/4606-0 Fax.: +49 2235/4606-29 Email: Berns(a)BEKA-Elektronik.de

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[U-Boot] [PATCH] mpc512x. Micron nand flash needs a reset before a read command is issued.
by Paul Gibson 04 Oct '09

04 Oct '09

Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command. --- drivers/mtd/nand/mpc5121_nfc.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index 856cb36..7fd8a35 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -334,6 +334,7 @@ static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_ERASE2: case NAND_CMD_READID: case NAND_CMD_STATUS: + case NAND_CMD_RESET: break; default: -- 1.6.0.4

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[U-Boot] [PATCH] Add mpc5125ads board and processor to the mpc512x family
by Martha M Stan 04 Oct '09

04 Oct '09

Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- Makefile | 3 + board/freescale/mpc5125ads/Makefile | 53 +++ board/freescale/mpc5125ads/config.mk | 23 ++ board/freescale/mpc5125ads/mpc5125ads.c | 420 +++++++++++++++++++++ board/freescale/mpc5125ads/u-boot.lds | 122 ++++++ cpu/mpc512x/asm-offsets.h | 6 + cpu/mpc512x/cpu.c | 3 + cpu/mpc512x/fixed_sdram.c | 8 +- cpu/mpc512x/iopin.c | 17 +- cpu/mpc512x/serial.c | 23 +- cpu/mpc512x/start.S | 15 + drivers/net/mpc512x_fec.c | 47 ++- include/asm-ppc/immap_512x.h | 618 +++++++++++++++++++++---------- include/configs/mpc5121ads.h | 1 + include/configs/mpc5125ads.h | 501 +++++++++++++++++++++++++ 15 files changed, 1638 insertions(+), 222 deletions(-) create mode 100644 board/freescale/mpc5125ads/Makefile create mode 100644 board/freescale/mpc5125ads/config.mk create mode 100644 board/freescale/mpc5125ads/mpc5125ads.c create mode 100644 board/freescale/mpc5125ads/u-boot.lds create mode 100644 include/configs/mpc5125ads.h diff --git a/Makefile b/Makefile index 0b61d05..a8ec984 100644 --- a/Makefile +++ b/Makefile @@ -844,6 +844,9 @@ mpc5121ads_rev2_config \ fi @$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale +mpc5125ads_config: unconfig + @$(MKCONFIG) -a mpc5125ads ppc mpc512x mpc5125ads freescale + ######################################################################### ## MPC8xx Systems ######################################################################### diff --git a/board/freescale/mpc5125ads/Makefile b/board/freescale/mpc5125ads/Makefile new file mode 100644 index 0000000..20fbf6e --- /dev/null +++ b/board/freescale/mpc5125ads/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +$(shell mkdir -p $(OBJTREE)/board/freescale/common) + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mpc5125ads/config.mk b/board/freescale/mpc5125ads/config.mk new file mode 100644 index 0000000..14998f4 --- /dev/null +++ b/board/freescale/mpc5125ads/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/freescale/mpc5125ads/mpc5125ads.c b/board/freescale/mpc5125ads/mpc5125ads.c new file mode 100644 index 0000000..445c765 --- /dev/null +++ b/board/freescale/mpc5125ads/mpc5125ads.c @@ -0,0 +1,420 @@ +/* + * Copyright 2009 Silicon Turnkey Express, Inc. + * Martha Marx Stan <mmarx(a)silicontkx.com> + * + * This file is based on mpc5121ads.c + * (C) Copyright 2007-2009 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/bitops.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mpc512x.h> +#include <fdt_support.h> + +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#include <flash.h> +extern flash_info_t flash_info[]; +extern ulong flash_get_size(ulong addr, flash_info_t *info); +#endif + +/* Clocks in use all configurations */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE2)| \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN | \ + CLOCK_SCCR2_SDHC_EN) + +/* Configuration Option Set 0 Clocks */ +#define SCCR2_CFG0_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_DIU_EN) + +/* Configuration Option Set 1 Clocks */ +#define SCCR1_CFG1_CLOCKS_EN (CLOCK_SCCR1_FEC2_EN) + +#define SCCR2_CFG1_CLOCKS_EN (CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_USB2_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +static iopin_t ioregs_common_init[] = { + /* + * Note: io pin init for LPC_CS2 is done in start.S + * also, DDR io pin init is done in fixed_sdram() + * + * FUNC1=PSC9_3 Sets Next 2 to PSC9 pads x4f & x50 + */ + { + offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO14 Sets 1 pad */ + { + offsetof(struct ioctrl512x, io_control_psc_mclk_in), 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=IRQ0 Sets 1 pad */ + { + offsetof(struct ioctrl512x, io_control_psc1_1), 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=CKSTP_OUT Sets 1 pad */ + { + offsetof(struct ioctrl512x, io_control_psc1_4), 1, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=I2C1_SCL Sets Next 2 to I2C1 pads */ + { + offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* ORs all pads to highest slew rate*/ + { + offsetof(struct ioctrl512x, io_control_lpc_clk), + offsetof(struct ioctrl512x,io_control_psc1_4) - + offsetof(struct ioctrl512x,io_control_lpc_clk) +1, 1, + IO_PIN_FMUX(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; +static iopin_t ioregs_cfg0_init[] = { + /* FUNC2=DIU_LD00 Sets Next 2 to DIU pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld00), 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=DIU_LD08 Sets Next 2 to DIU pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld08), 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=DIU_LD16 Sets Next 2 to DIU pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld16), 2, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; +static iopin_t ioregs_cfg1_init[] = { + /* FUNC2=USB1_DATA0 Sets Next 4 to USB1 pads */ + { + offsetof(struct ioctrl512x, io_control_diu_clk), 4, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO32 Sets 1 (2 ??) pad */ + { + offsetof(struct ioctrl512x, io_control_diu_ld00), 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_DATA4 Sets Next 6 to USB1 pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld02), 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=GPIO37 Sets 2 to GPIO pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld08), 2, 0, + IO_PIN_FMUX(3) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB1_NEXT Sets Next 6 to USB1 and USB2 pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld10), 6, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=I2C3_SCL Sets Next 2 to I2C3 pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld16), 8, 0, + IO_PIN_FMUX(1) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=USB2_DATA4 Sets Next 8 to USB2 pads */ + { + offsetof(struct ioctrl512x, io_control_diu_ld18), 8, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */ + { + offsetof(struct ioctrl512x, io_control_usb1_data0), 12, 0, + IO_PIN_FMUX(2) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; + +int board_early_init_f (void) +{ + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ + out_be32(&im->sysconf.lpcs2aw, CSAW_START(CONFIG_SYS_CPLD_BASE) | + CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)); + out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); + + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + sync_law(&im->sysconf.lpcs2aw); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash id routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ + + if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xc1); + } else { + /* running from Backup flash */ + out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); + } + + /* + * Configure Flash Speed + */ + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); + out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); + + /* + * Enable clocks + */ + if (IS_CFG1_SWITCH) { + out_be32(&im->clk.sccr[0], + SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], + SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN); + } else { + out_be32(&im->clk.sccr[0], + SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], + SCCR2_CLOCKS_EN | SCCR2_CFG0_CLOCKS_EN); + } +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + out_be32(&im->clk.sccr[1], + in_be32(&im->clk.sccr[1])| CLOCK_SCCR2_IIM_EN); +#endif + /* + * initialize function mux & slew rate for all IO pins + * there are two peripheral options controlled by switch 8 + */ + if (IS_CFG1_SWITCH) { + iopin_initialize(ioregs_cfg1_init, + sizeof(ioregs_cfg1_init)/sizeof(ioregs_cfg1_init[0])); + } else { + iopin_initialize(ioregs_cfg0_init, + sizeof(ioregs_cfg0_init)/sizeof(ioregs_cfg0_init[0])); + } + + iopin_initialize(ioregs_common_init, + sizeof(ioregs_common_init)/sizeof(ioregs_common_init[0])); + + /* enable default pins */ + out_8(&im->io_ctrl.io_control_gbobe, IOCTRL_GBOBE_ON); + return 0; +} + +phys_size_t initdram (int board_type) +{ + /* Elpida init sequence is an alternative to the default for Micron */ + + u32 elpida_init_sequence[] = { + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_EM2, + CONFIG_SYS_DDRCMD_EM3, + CONFIG_SYS_DDRCMD_EN_DLL, + CONFIG_SYS_ELPIDA_RES_DLL, + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_ELPIDA_INIT_DEV_OP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_ELPIDA_OCD_DEFAULT, + CONFIG_SYS_ELPIDA_OCD_EXIT, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP + }; + + u32 msize; + + msize = fixed_sdram(0, elpida_init_sequence, + sizeof(elpida_init_sequence)/sizeof(u32)); + + return msize; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 tmp_val; + + extern int ads5121_diu_init(void); + + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 bkup_size = flash_info[0].size; + u32 bkup_start = 0xffffffff - bkup_size +1; + + if (bkup_size == CONFIG_SYS_BKUP_FLASH_SIZE) { + + /* + * Running from the smaller sized Backup flash + * must remap flash so that the env maps same as main flash + */ + debug("Remap backup flash to start at 0x%08lx \n",bkup_start); + out_be32(&im->sysconf.lpcs0aw, CSAW_START(bkup_start) | + CSAW_STOP(bkup_start, bkup_size)); + /* + * According to MPC5121e RM, configuring local access windows + * should be followed by a dummy read of the config register + * that was modified last and an isync + */ + sync_law(&im->sysconf.lpcs0aw); + flash_get_size(bkup_start, 0); + } + + if (IS_CFG1_SWITCH) /* no diu in CFG1 */ + return 0; +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + + if (IS_CFG1_SWITCH){ + /* turn on ??? */ + i2c_set_bus_num(2); + } else { + /* + * DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + i2c_set_bus_num(1); + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + } +#endif +#ifdef CONFIG_FSL_DIU_FB +#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) + mpc5121_diu_init(); +#endif +#endif + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ +int checkboard (void) +{ + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); + uchar cpld_min_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x03); + + printf ("Board: MPC5125ADS rev. 0x%04x (CPLD rev. 0x%02x", + brd_rev, cpld_rev); + + if (cpld_min_rev != '\0') + printf (".%02x-BETA)\n", cpld_min_rev); + else + printf (")\n"); + + if (IS_CFG1_SWITCH) /* CAN1+2, SDHC1, USB1+2, FEC1+2, I2C1+2*/ + printf("Peripheral Option Set 1\n"); + else /* CAN1+2, SDHC1, DIU, USB1, FEC1, I2C1+3*/ + printf("Peripheral Option Set 0\n"); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/freescale/mpc5125ads/u-boot.lds b/board/freescale/mpc5125ads/u-boot.lds new file mode 100644 index 0000000..f2f6e14 --- /dev/null +++ b/board/freescale/mpc5125ads/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h index 4b14778..b79c656 100644 --- a/cpu/mpc512x/asm-offsets.h +++ b/cpu/mpc512x/asm-offsets.h @@ -11,5 +11,11 @@ #define CS_CTRL 0x00020 #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ +/* needed for pin muxing in MPC5125 */ +#define IOCTRL_OFFSET 0xA000 +#define IOCTRL_LPC_AX03 0x09 +#define IOCTRL_I2C1_SCL 0x4f +#define IOCTRL_I2C1_SDA 0x50 + #define EXC_OFF_SYS_RESET 0x0100 #define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 42ccd81..12d21f6 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -53,6 +53,9 @@ int checkcpu (void) case SPR_5121E: puts ("MPC5121e "); break; + case SPR_5125: + puts ("MPC5125 "); + break; default: printf ("Unknown part ID %08x ", spridr & 0xffff0000); } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 63a3035..12ac44d 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -36,6 +36,7 @@ u32 default_mddrc_config[4] = { }; u32 default_init_seq[] = { +#ifndef CONFIG_SYS_DDR_OVRIDE_DEF CONFIG_SYS_DDRCMD_NOP, CONFIG_SYS_DDRCMD_NOP, CONFIG_SYS_DDRCMD_NOP, @@ -67,6 +68,7 @@ u32 default_init_seq[] = { CONFIG_SYS_DDRCMD_OCD_DEFAULT, CONFIG_SYS_DDRCMD_PCHG_ALL, CONFIG_SYS_DDRCMD_NOP +#endif }; /* @@ -90,7 +92,11 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) } /* Initialize IO Control */ - out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); +#ifdef CONFIG_MPC5125 + out_8(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); +#else + out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); +#endif /* Initialize DDR Local Window */ out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index be20947..ab5dd1c 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -28,15 +28,27 @@ void iopin_initialize(iopin_t *ioregs_init, int len) { short i, j, p; - u32 *reg; immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - reg = (u32 *)&(im->io_ctrl); +#ifdef CONFIG_MPC5125 + u8 *reg =(u8 *)&(im->io_ctrl); +#else + u32 *reg =(u32 *)&(im->io_ctrl); +#endif if (sizeof(ioregs_init) == 0) return; for (i = 0; i < len; i++) { +#ifdef CONFIG_MPC5125 + for (p = 0, j = ioregs_init[i].p_offset; + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or) + setbits_8(&(reg[j]), ioregs_init[i].val); + else + out_8(&reg[j], ioregs_init[i].val); + } +#else for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); p < ioregs_init[i].nr_pins; p++, j++) { if (ioregs_init[i].bit_or) @@ -44,6 +56,7 @@ void iopin_initialize(iopin_t *ioregs_init, int len) else out_be32 (reg + j, ioregs_init[i].val); } +#endif } return; } diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 4fc4693..c2bd29c 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -64,12 +64,17 @@ void serial_setbrg(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; - unsigned long baseclk, div; + unsigned long div; /* calculate dividor for setting PSC CTUR and CTLR registers */ - baseclk = (gd->ips_clk + 8) / 16; - div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; +#ifndef CONFIG_MPC5125 + unsigned long baseclk = (gd->ips_clk + 8) / 16; + + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; +#else + div = gd->ips_clk/(16 * gd->baudrate); +#endif out_8(&psc->ctur, (div >> 8) & 0xff); out_8(&psc->ctlr, div & 0xff); /* set baudrate */ } @@ -81,9 +86,10 @@ int serial_init(void) fifo_init (psc); +#ifndef CONFIG_MPC5125 /* set MR register to point to MR1 */ out_8(&psc->command, PSC_SEL_MODE_REG_1); - +#endif /* disable Tx/Rx */ out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE); @@ -93,12 +99,17 @@ int serial_init(void) /* switch to UART mode */ out_be32(&psc->sicr, 0); + + /* configure parity, bit length and so on in mode registers */ +#ifdef CONFIG_MPC5125 + out_8(&psc->mr1, PSC_MODE_8_BITS | PSC_MODE_PARNONE); + out_8(&psc->mr2, PSC_MODE_1_STOPBIT); +#else /* mode register points to mr1 */ - /* configure parity, bit length and so on in mode register 1*/ out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); /* now, mode register points to mr2 */ out_8(&psc->mode, PSC_MODE_1_STOPBIT); - +#endif /* set baudrate */ serial_setbrg(); diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 2e3f645..61e3b50 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -243,6 +243,21 @@ boot_cold: lis r4, CONFIG_SYS_CS0_CFG@h ori r4, r4, CONFIG_SYS_CS0_CFG@l stw r4, CS0_CONFIG(r3) +#ifdef CONFIG_MPC5125 + /* CS2 FUNC MUX must be done before CS is enabled */ + lis r5, (CONFIG_SYS_IMMR + IOCTRL_OFFSET)@h + ori r5, r5, (CONFIG_SYS_IMMR + IOCTRL_OFFSET)@l + + li r4, CONFIG_SYS_IOCTRL_MUX_CS2 + stb r4, IOCTRL_LPC_AX03(r5) + + /* change the pin muxing on PSC9 if it is being used as console */ +#if (CONFIG_PSC_CONSOLE == 9) + li r4, CONFIG_SYS_IOCTRL_MUX_PSC9 + stb r4, IOCTRL_I2C1_SCL(r5) + stb r4, IOCTRL_I2C1_SDA(r5) +#endif +#endif /* Master enable all CS's */ lis r4, CS_CTRL_ME@h diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index fb2c19a..3ff1c31 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -41,7 +41,11 @@ static int rx_buff_idx = 0; static void mpc512x_fec_phydump (char *devname) { u16 phyStatus, i; - u8 phyAddr = CONFIG_PHY_ADDR; +#ifdef CONFIG_MPC5125 + uint8 phyAddr = ((devname[3]=='2') ? CONFIG_PHY2_ADDR : CONFIG_PHY_ADDR); +#else + uint8 phyAddr = CONFIG_PHY_ADDR; +#endif u8 reg_mask[] = { /* regs to print: 0...8, 21,27,31 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, @@ -242,9 +246,17 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) /* Set Opcode/Pause Duration Register */ out_be32(&fec->eth->op_pause, 0x00010020); +#ifdef CONFIG_MPC5125 + /* RMII Mode */ + if (dev->name[3] == '2') + out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x124); + else + /* Frame length=1522; MII mode */ + out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); +#else /* Frame length=1522; MII mode */ out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24); - +#endif /* Half-duplex, heartbeat disabled */ out_be32(&fec->eth->x_cntrl, 0x00000000); @@ -286,7 +298,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) u16 phyStatus; #if (DEBUG & 0x1) - printf ("mpc512x_fec_init_phy... Begin\n"); + printf ("mpc512x_fec_init_phy... with dev %s Begin\n", dev->name); #endif /* @@ -618,12 +630,14 @@ int mpc512x_fec_initialize (bd_t * bis) int i; char *tmp, *end, env_enetaddr[6]; void * bd; + fec512x_t *cur_fec = &(im->fec); +fec_init_start: fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); dev = (struct eth_device *) malloc (sizeof(*dev)); memset (dev, 0, sizeof *dev); - fec->eth = &im->fec; + fec->eth = cur_fec; # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; @@ -637,7 +651,11 @@ int mpc512x_fec_initialize (bd_t * bis) dev->send = mpc512x_fec_send; dev->recv = mpc512x_fec_recv; - sprintf (dev->name, "FEC ETHERNET"); + if (cur_fec == &(im->fec)) + sprintf (dev->name, "FEC ETHERNET"); + else + sprintf (dev->name, "FEC2 ETHERNET"); + eth_register (dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) @@ -646,8 +664,8 @@ int mpc512x_fec_initialize (bd_t * bis) #endif /* Clean up space FEC's MIB and FIFO RAM ...*/ - memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib)); - memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo)); + memset ((void *)cur_fec->mib, 0x00, sizeof(im->fec.mib)); + memset ((void *)cur_fec->fifo, 0x00, sizeof(im->fec.fifo)); /* * Malloc space for BDs (must be quad word-aligned) @@ -672,7 +690,11 @@ int mpc512x_fec_initialize (bd_t * bis) * a garbage after reset. When not using fec for booting * the Linux fec driver will try to work with this garbage. */ - tmp = getenv ("ethaddr"); + if (cur_fec == &(im->fec)) + tmp = getenv ("ethaddr"); + else + tmp = getenv ("eth1addr"); + if (tmp) { for (i=0; i<6; i++) { env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; @@ -685,7 +707,14 @@ int mpc512x_fec_initialize (bd_t * bis) } mpc512x_fec_init_phy (dev, bis); - +#ifdef CONFIG_MPC5125 + /* 2nd fec may not be in use */ + if (cur_fec == &(im->fec) && + (in_be32(&im->clk.sccr[0]) & CLOCK_SCCR1_FEC2_EN)) { + cur_fec = &(im->fec2); + goto fec_init_start; + } +#endif return 1; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 79cdd80..50ef20c 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -36,6 +36,8 @@ #define _START_OFFSET EXC_OFF_SYS_RESET #define SPR_5121E 0x80180000 +#define SPR_5125 0x80190000 + /* * IMMRBAR - Internal Memory Register Base Address @@ -210,21 +212,25 @@ typedef struct clk512x { #define CLOCK_SCCR1_TPR_EN 0x00001000 #define CLOCK_SCCR1_PCI_EN 0x00000800 #define CLOCK_SCCR1_DDR_EN 0x00000400 +#define CLOCK_SCCR1_FEC2_EN 0x00000200 /* System Clock Control Register 2 commands */ #define CLOCK_SCCR2_DIU_EN 0x80000000 #define CLOCK_SCCR2_AXE_EN 0x40000000 #define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB2_EN 0x10000000 -#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_USB1_EN 0x10000000 +#define CLOCK_SCCR2_USB2_EN 0x08000000 #define CLOCK_SCCR2_I2C_EN 0x04000000 #define CLOCK_SCCR2_BDLC_EN 0x02000000 +#define CLOCK_SCCR2_AUTO_EN 0x02000000 #define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_AUTO_EN 0x02000000 #define CLOCK_SCCR2_SPDIF_EN 0x00800000 #define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 #define CLOCK_SCCR2_MBX_EN 0x00200000 #define CLOCK_SCCR2_MBX_3D_EN 0x00100000 #define CLOCK_SCCR2_IIM_EN 0x00080000 +#define CLOCK_SCCR2_SDHC2_EN 0x00020000 /* SCFR1 System Clock Frequency Register 1 */ #define SCFR1_IPS_DIV 0x3 @@ -642,208 +648,346 @@ typedef struct pcidma512x { * IO Control */ typedef struct ioctrl512x { - u32 io_control_mem; /* MEM pad ctrl reg */ - u32 io_control_gp; /* GP pad ctrl reg */ - u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ - u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ - u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ - u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ - u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ - u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ - u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ - u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ - u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ - u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ - u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ - u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ - u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ - u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ - u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ - u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ - u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ - u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ - u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ - u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ - u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ - u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ - u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ - u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ - u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ - u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ - u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ - u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ - u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ - u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ - u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ - u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ - u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ - u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ - u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ - u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ - u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ - u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ - u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ - u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ - u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ - u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ - u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ - u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ - u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ - u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ - u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ - u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ - u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ - u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ - u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ - u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ - u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ - u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ - u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ - u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ - u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ - u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ - u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ - u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ - u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ - u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ - u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ - u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ - u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ - u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ - u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ - u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ - u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ - u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ - u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ - u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ - u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ - u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ - u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ - u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ - u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ - u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ - u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ - u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ - u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ - u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ - u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ - u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ - u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ - u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ - u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ - u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ - u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ - u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ - u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ - u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ - u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ - u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ - u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ - u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ - u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ - u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ - u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ - u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ - u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ - u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ - u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ - u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ - u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ - u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ - u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ - u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ - u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ - u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ - u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ - u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ - u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ - u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ - u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ - u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ - u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ - u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ - u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ - u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ - u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ - u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ - u32 io_control_irq0; /* IRQ0 pad ctrl reg */ - u32 io_control_irq1; /* IRQ1 pad ctrl reg */ - u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ - u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ - u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ - u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ - u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ - u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ - u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ - u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ - u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ - u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ - u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ - u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ - u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ - u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ - u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ - u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ - u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ - u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ - u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ - u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ - u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ - u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ - u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ - u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ - u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ - u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ - u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ - u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ - u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ - u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ - u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ - u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ - u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ - u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ - u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ - u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ - u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ - u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ - u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ - u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ - u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ - u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ - u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ - u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ - u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ - u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ - u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ - u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ - u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ - u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ - u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ - u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ - u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ - u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ - u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ - u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ - u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ - u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ - u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ - u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ - u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ - u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ - u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ - u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ - u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ - u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ - u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ - u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ +#ifdef CONFIG_MPC5125 + u8 io_control_mem; /* offset 0x00 mem pad ctrl reg */ + u8 io_control_gbobe; /* offset 0x01 gbobe pad ctrl reg */ + u8 res1[2]; + u8 io_control_lpc_clk; /* offset 0x04 lpc_clk pad ctrl reg */ + u8 io_control_lpc_oe_b; /* offset 0x05 lpc_oe_b pad ctrl reg */ + u8 io_control_lpc_rwb; /* offset 0x06 lpc_rwb pad ctrl reg */ + u8 io_control_lpc_cs0_b; /* offset 0x07 lpc_cs0_b */ + u8 io_control_lpc_ack_b; /* offset 0x08 lpc_ack_b pad ctrl reg */ + u8 io_control_lpc_ax03; /* offset 0x09 lpc_ax03 pad ctrl reg */ + u8 io_control_emb_ax02; /* offset 0x0a emb_ax02 pad ctrl reg */ + u8 io_control_emb_ax01; /* offset 0x0b emb_ax01 pad ctrl reg */ + u8 io_control_emb_ax00; /* offset 0x0c emb_ax00 pad ctrl reg */ + u8 io_control_emb_ad31; /* offset 0x0d emb_ad31 pad ctrl reg */ + u8 io_control_emb_ad30; /* offset 0x0e emb_ad30 pad ctrl reg */ + u8 io_control_emb_ad29; /* offset 0x0f emb_ad29 pad ctrl reg */ + u8 io_control_emb_ad28; /* offset 0x10 emb_ad28 pad ctrl reg */ + u8 io_control_emb_ad27; /* offset 0x11 emb_ad27 pad ctrl reg */ + u8 io_control_emb_ad26; /* offset 0x12 emb_ad26 pad ctrl reg */ + u8 io_control_emb_ad25; /* offset 0x13 emb_ad25 pad ctrl reg */ + u8 io_control_emb_ad24; /* offset 0x14 emb_ad24 pad ctrl reg */ + u8 io_control_emb_ad23; /* offset 0x15 emb_ad23 pad ctrl reg */ + u8 io_control_emb_ad22; /* offset 0x16 emb_ad22 pad ctrl reg */ + u8 io_control_emb_ad21; /* offset 0x17 emb_ad21 pad ctrl reg */ + u8 io_control_emb_ad20; /* offset 0x18 emb_ad20 pad ctrl reg */ + u8 io_control_emb_ad19; /* offset 0x19 emb_ad19 pad ctrl reg */ + u8 io_control_emb_ad18; /* offset 0x1a emb_ad18 pad ctrl reg */ + u8 io_control_emb_ad17; /* offset 0x1b emb_ad17 pad ctrl reg */ + u8 io_control_emb_ad16; /* offset 0x1c emb_ad16 pad ctrl reg */ + u8 io_control_emb_ad15; /* offset 0x1d emb_ad15 pad ctrl reg */ + u8 io_control_emb_ad14; /* offset 0x1e emb_ad14 pad ctrl reg */ + u8 io_control_emb_ad13; /* offset 0x1f emb_ad13 pad ctrl reg */ + u8 io_control_emb_ad12; /* offset 0x20 emb_ad12 pad ctrl reg */ + u8 io_control_emb_ad11; /* offset 0x21 emb_ad11 pad ctrl reg */ + u8 io_control_emb_ad10; /* offset 0x22 emb_ad10 pad ctrl reg */ + u8 io_control_emb_ad09; /* offset 0x23 emb_ad09 pad ctrl reg */ + u8 io_control_emb_ad08; /* offset 0x24 emb_ad08 pad ctrl reg */ + u8 io_control_emb_ad07; /* offset 0x25 emb_ad07 pad ctrl reg */ + u8 io_control_emb_ad06; /* offset 0x26 emb_ad06 pad ctrl reg */ + u8 io_control_emb_ad05; /* offset 0x27 emb_ad05 pad ctrl reg */ + u8 io_control_emb_ad04; /* offset 0x28 emb_ad04 pad ctrl reg */ + u8 io_control_emb_ad03; /* offset 0x29 emb_ad03 pad ctrl reg */ + u8 io_control_emb_ad02; /* offset 0x2a emb_ad02 pad ctrl reg */ + u8 io_control_emb_ad01; /* offset 0x2b emb_ad01 pad ctrl reg */ + u8 io_control_emb_ad00; /* offset 0x2c emb_ad00 pad ctrl reg */ + u8 io_control_nfc_ce0_b; /* offset 0x2d nfc_ce0_b pad ctrl reg */ + u8 io_control_nfc_rb; /* offset 0x2e nfc_rb pad ctrl reg */ + u8 io_control_diu_clk; /* offset 0x2f diu_clk pad ctrl reg */ + u8 io_control_diu_de; /* offset 0x30 diu_de pad ctrl reg */ + u8 io_control_diu_hsync; /* offset 0x31 diu_hsync pad ctrl reg */ + u8 io_control_diu_vsync; /* offset 0x32 diu_vsync pad ctrl reg */ + u8 io_control_diu_ld00; /* offset 0x33 diu_ld00 pad ctrl reg */ + u8 io_control_diu_ld01; /* offset 0x34 diu_ld01 pad ctrl reg */ + u8 io_control_diu_ld02; /* offset 0x35 diu_ld02 pad ctrl reg */ + u8 io_control_diu_ld03; /* offset 0x36 diu_ld03 pad ctrl reg */ + u8 io_control_diu_ld04; /* offset 0x37 diu_ld04 pad ctrl reg */ + u8 io_control_diu_ld05; /* offset 0x38 diu_ld05 pad ctrl reg */ + u8 io_control_diu_ld06; /* offset 0x39 diu_ld06 pad ctrl reg */ + u8 io_control_diu_ld07; /* offset 0x3a diu_ld07 pad ctrl reg */ + u8 io_control_diu_ld08; /* offset 0x3b diu_ld08 pad ctrl reg */ + u8 io_control_diu_ld09; /* offset 0x3c diu_ld09 pad ctrl reg */ + u8 io_control_diu_ld10; /* offset 0x3d diu_ld10 pad ctrl reg */ + u8 io_control_diu_ld11; /* offset 0x3e diu_ld11 pad ctrl reg */ + u8 io_control_diu_ld12; /* offset 0x3f diu_ld12 pad ctrl reg */ + u8 io_control_diu_ld13; /* offset 0x40 diu_ld13 pad ctrl reg */ + u8 io_control_diu_ld14; /* offset 0x41 diu_ld14 pad ctrl reg */ + u8 io_control_diu_ld15; /* offset 0x42 diu_ld15 pad ctrl reg */ + u8 io_control_diu_ld16; /* offset 0x43 diu_ld16 pad ctrl reg */ + u8 io_control_diu_ld17; /* offset 0x44 diu_ld17 pad ctrl reg */ + u8 io_control_diu_ld18; /* offset 0x45 diu_ld18 pad ctrl reg */ + u8 io_control_diu_ld19; /* offset 0x46 diu_ld19 pad ctrl reg */ + u8 io_control_diu_ld20; /* offset 0x47 diu_ld20 pad ctrl reg */ + u8 io_control_diu_ld21; /* offset 0x48 diu_ld21 pad ctrl reg */ + u8 io_control_diu_ld22; /* offset 0x49 diu_ld22 pad ctrl reg */ + u8 io_control_diu_ld23; /* offset 0x4a diu_ld23 pad ctrl reg */ + u8 io_control_can4_rx; /* offset 0x4b can4_rx pad ctrl reg */ + u8 io_control_can4_tx; /* offset 0x4c can4_tx pad ctrl reg */ + u8 io_control_can1_tx; /* offset 0x4d can1_tx pad ctrl reg */ + u8 io_control_can2_tx; /* offset 0x4e can2_tx pad ctrl reg */ + u8 io_control_i2c1_scl; /* offset 0x4f i2c1_scl pad ctrl reg */ + u8 io_control_i2c1_sda; /* offset 0x50 i2c1_sda pad ctrl reg */ + u8 io_control_fec1_txd_2; /* offset 0x51 fec1_txd_2 pad ctrl reg */ + u8 io_control_fec1_txd_3; /* offset 0x52 fec1_txd_3 pad ctrl reg */ + u8 io_control_fec1_rxd_2; /* offset 0x53 fec1_rxd_2 pad ctrl reg */ + u8 io_control_fec1_rxd_3; /* offset 0x54 fec1_rxd_3 pad ctrl reg */ + u8 io_control_fec1_crs; /* offset 0x55 fec1_crs pad ctrl reg */ + u8 io_control_fec1_tx_er; /* offset 0x56 fec1_tx_er pad ctrl reg */ + u8 io_control_fec1_rxd_1; /* offset 0x57 fec1_rxd_1 pad ctrl reg */ + u8 io_control_fec1_txd_1; /* offset 0x58 fec1_txd_1 pad ctrl reg */ + u8 io_control_fec1_mdc; /* offset 0x59 fec1_mdc pad ctrl reg */ + u8 io_control_fec1_rx_er; /* offset 0x5a fec1_rx_er pad ctrl reg */ + u8 io_control_fec1_mdio; /* offset 0x5b fec1_mdio pad ctrl reg */ + u8 io_control_fec1_rxd_0; /* offset 0x5c fec1_rxd_0 pad ctrl reg */ + u8 io_control_fec1_txd_0; /* offset 0x5d fec1_txd_0 pad ctrl reg */ + u8 io_control_fec1_tx_clk; /* offset 0x5e fec1_tx_clk pad ctrl reg */ + u8 io_control_fec1_rx_clk; /* offset 0x5f fec1_rx_clk pad ctrl reg */ + u8 io_control_fec1_rx_dv; /* offset 0x60 fec1_rx_dv pad ctrl reg */ + u8 io_control_fec1_tx_en; /* offset 0x61 fec1_tx_en pad ctrl reg */ + u8 io_control_fec1_col; /* offset 0x62 fec1_col pad ctrl reg */ + u8 io_control_usb1_data0; /* offset 0x63 usb1_data0 pad ctrl reg */ + u8 io_control_usb1_data1; /* offset 0x64 usb1_data1 pad ctrl reg */ + u8 io_control_usb1_data2; /* offset 0x65 usb1_data2 pad ctrl reg */ + u8 io_control_usb1_data3; /* offset 0x66 usb1_data3 pad ctrl reg */ + u8 io_control_usb1_data4; /* offset 0x67 usb1_data4 pad ctrl reg */ + u8 io_control_usb1_data5; /* offset 0x68 usb1_data5 pad ctrl reg */ + u8 io_control_usb1_data6; /* offset 0x69 usb1_data6 pad ctrl reg */ + u8 io_control_usb1_data7; /* offset 0x6a usb1_data7 pad ctrl reg */ + u8 io_control_usb1_stop; /* offset 0x6b usb1_stop pad ctrl reg */ + u8 io_control_usb1_clk; /* offset 0x6c usb1_clk pad ctrl reg */ + u8 io_control_usb1_next; /* offset 0x6d usb1_next pad ctrl reg */ + u8 io_control_usb1_dir; /* offset 0x6e usb1_dir pad ctrl reg */ + u8 io_control_sdhc1_clk; /* offset 0x6f sdhc1_clk pad ctrl reg */ + u8 io_control_sdhc1_cmd; /* offset 0x70 sdhc1_cmd pad ctrl reg */ + u8 io_control_sdhc1_d0; /* offset 0x71 sdhc1_d0 pad ctrl reg */ + u8 io_control_sdhc1_d1; /* offset 0x72 sdhc1_d1 pad ctrl reg */ + u8 io_control_sdhc1_d2; /* offset 0x73 sdhc1_d2 pad ctrl reg */ + u8 io_control_sdhc1_d3; /* offset 0x74 sdhc1_d3 pad ctrl reg */ + u8 io_control_psc_mclk_in; /* offset 0x75 psc_mclk_in pad ctrl reg */ + u8 io_control_psc0_0; /* offset 0x76 psc0_0 pad ctrl reg */ + u8 io_control_psc0_1; /* offset 0x77 psc0_1 pad ctrl reg */ + u8 io_control_psc0_2; /* offset 0x78 psc0_2 pad ctrl reg */ + u8 io_control_psc0_3; /* offset 0x79 psc0_3 pad ctrl reg */ + u8 io_control_psc0_4; /* offset 0x7a psc0_4 pad ctrl reg */ + u8 io_control_psc1_0; /* offset 0x7b psc1_0 pad ctrl reg */ + u8 io_control_psc1_1; /* offset 0x7c psc1_1 pad ctrl reg */ + u8 io_control_psc1_2; /* offset 0x7d psc1_2 pad ctrl reg */ + u8 io_control_psc1_3; /* offset 0x7e psc1_3 pad ctrl reg */ + u8 io_control_psc1_4; /* offset 0x7f psc1_4 pad ctrl reg */ + u8 io_control_j1850_tx; /* offset 0x80 j1850_tx pad ctrl reg */ + u8 io_control_j1850_rx; /* offset 0x81 j1850_rx pad ctrl reg */ + u8 reserved[0x1000 - 0x82]; /* fill to 4096 bytes size */ +#else + u32 io_control_mem; /* MEM pad ctrl reg */ + u32 io_control_gp; /* GP pad ctrl reg */ + u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ + u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ + u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ + u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ + u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ + u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ + u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ + u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ + u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ + u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ + u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ + u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ + u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ + u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ + u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ + u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ + u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ + u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ + u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ + u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ + u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ + u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ + u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ + u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ + u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ + u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ + u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ + u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ + u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ + u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ + u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ + u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ + u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ + u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ + u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ + u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ + u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ + u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ + u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ + u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ + u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ + u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ + u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ + u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ + u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ + u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ + u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ + u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ + u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ + u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ + u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ + u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ + u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ + u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ + u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ + u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ + u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ + u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ + u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ + u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ + u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ + u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ + u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ + u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ + u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ + u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ + u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ + u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ + u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ + u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ + u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ + u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ + u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ + u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ + u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ + u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ + u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ + u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ + u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ + u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ + u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ + u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ + u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ + u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ + u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ + u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ + u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ + u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ + u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ + u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ + u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ + u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ + u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ + u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ + u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ + u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ + u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ + u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ + u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ + u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ + u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ + u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ + u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ + u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ + u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ + u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ + u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ + u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ + u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ + u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ + u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ + u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ + u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ + u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ + u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ + u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ + u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ + u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ + u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ + u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ + u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ + u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ + u32 io_control_irq0; /* IRQ0 pad ctrl reg */ + u32 io_control_irq1; /* IRQ1 pad ctrl reg */ + u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ + u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ + u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ + u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ + u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ + u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ + u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ + u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ + u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ + u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ + u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ + u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ + u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ + u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ + u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ + u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ + u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ + u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ + u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ + u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ + u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ + u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ + u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ + u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ + u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ + u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ + u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ + u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ + u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ + u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ + u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ + u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ + u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ + u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ + u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ + u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ + u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ + u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ + u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ + u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ + u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ + u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ + u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ + u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ + u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ + u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ + u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ + u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ + u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ + u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ + u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ + u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ + u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ + u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ + u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ + u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ + u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ + u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ + u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ + u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ + u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ + u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ + u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ + u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ + u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ + u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ + u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ + u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ +#endif } ioctrl512x_t; /* Indexes in regs array */ /* Set for DDR */ #define IOCTRL_MUX_DDR 0x00000036 +#define IOCTRL_GBOBE_ON 0x01 /* IO pin fields */ +#ifdef CONFIG_MPC5125 +#define IO_PIN_FMUX(v) ((v) << 5) /* pin function */ +#else #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#endif #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ @@ -854,7 +998,12 @@ typedef struct iopin_t { int p_offset; /* offset from IOCTL_MEM_OFFSET */ int nr_pins; /* number of pins to set this way */ int bit_or; /* or in the value instead of overwrite */ +#ifdef CONFIG_MPC5125 + u_char val; + u_char res0[3]; +#else u_long val; /* value to write or or */ +#endif }iopin_t; void iopin_initialize(iopin_t *,int); @@ -952,6 +1101,52 @@ typedef struct pata512x { * PSC */ typedef struct psc512x { +#ifdef CONFIG_MPC5125 + volatile u8 mr1; /* PSC + 0x00 */ + volatile u8 res0[3]; + volatile u8 mr2; /* PSC + 0x04 */ + volatile u8 res0a[3]; + volatile u16 psc_status; /* PSC + 0x08 */ + volatile u16 res1; + volatile u16 psc_clock_select;/* PSC + 0x0C mpc5125 manual has this as u8 */ + /* it has u8 res after it and for compatibility */ + /* will keep u16 so high bits are set as before */ + volatile u16 res1a; + volatile u8 command; /* PSC + 0x10 */ + volatile u8 res2[3]; + union { /* PSC + 0x14 */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + volatile u8 psc_ipcr; /* PSC + 0x18 */ + volatile u8 res3[3]; + volatile u8 psc_acr; /* PSC + 0x1C */ + volatile u8 res3a[3]; + volatile u16 psc_isr; /* PSC + 0x20 */ + volatile u16 res4; + volatile u16 psc_imr; /* PSC + 0x24 */ + volatile u16 res4a; + volatile u8 ctur; /* PSC + 0x28 */ + volatile u8 res5[3]; + volatile u8 ctlr; /* PSC + 0x2c */ + volatile u8 res6[3]; + volatile u32 ccr; /* PSC + 0x30 */ + volatile u8 res7[12]; + volatile u8 ivr; /* PSC + 0x40 */ + volatile u8 res8[3]; + volatile u8 ip; /* PSC + 0x44 */ + volatile u8 res9[3]; + volatile u8 op1; /* PSC + 0x48 */ + volatile u8 res10[3]; + volatile u8 op0; /* PSC + 0x4c */ + volatile u8 res11[3]; + volatile u32 sicr; /* PSC + 0x50 */ + volatile u8 res12[44]; +#else volatile u8 mode; /* PSC + 0x00 */ volatile u8 res0[3]; union { /* PSC + 0x04 */ @@ -1001,6 +1196,7 @@ typedef struct psc512x { volatile u8 res11[3]; volatile u32 sicr; /* PSC + 0x40 */ volatile u8 res12[60]; +#endif /* FIFOC is the same for all mpc512x */ volatile u32 tfcmd; /* PSC + 0x80 */ volatile u32 tfalarm; /* PSC + 0x84 */ volatile u32 tfstat; /* PSC + 0x88 */ @@ -1112,10 +1308,10 @@ typedef struct fifoc512x { #define FIFOC_PSC0_RX_SIZE 0x0 #define FIFOC_PSC0_RX_ADDR 0x0 -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 +#define FIFOC_PSC1_TX_SIZE 0x4 +#define FIFOC_PSC1_TX_ADDR 0x20 +#define FIFOC_PSC1_RX_SIZE 0x4 +#define FIFOC_PSC1_RX_ADDR 0x30 #define FIFOC_PSC2_TX_SIZE 0x0 #define FIFOC_PSC2_TX_ADDR 0x0 @@ -1152,10 +1348,10 @@ typedef struct fifoc512x { #define FIFOC_PSC8_RX_SIZE 0x0 #define FIFOC_PSC8_RX_ADDR 0x0 -#define FIFOC_PSC9_TX_SIZE 0x0 -#define FIFOC_PSC9_TX_ADDR 0x0 -#define FIFOC_PSC9_RX_SIZE 0x0 -#define FIFOC_PSC9_RX_ADDR 0x0 +#define FIFOC_PSC9_TX_SIZE 0x4 +#define FIFOC_PSC9_TX_ADDR 0x40 +#define FIFOC_PSC9_RX_SIZE 0x4 +#define FIFOC_PSC9_RX_ADDR 0x50 #define FIFOC_PSC10_TX_SIZE 0x0 #define FIFOC_PSC10_TX_ADDR 0x0 @@ -1200,6 +1396,14 @@ typedef struct immap { fec512x_t fec; /* Fast Ethernet Controller */ ulpi512x_t ulpi; /* USB ULPI */ u8 res4[0xa00]; +#ifdef CONFIG_MPC5125 + ulpi512x_t ulpi2; /* USB ULPI */ + u8 res5[0x200]; + fec512x_t fec2; /* 2nd Fast Ethernet Controller */ + gpt512x_t gpt2; /* 2nd General Purpose Timer */ + sdhc512x_t sdhc2; /* 2nd SDHC */ + u8 res6[0x3e00]; +#else utmi512x_t utmi; /* USB UTMI */ u8 res5[0x1000]; pcidma512x_t pci_dma; /* PCI DMA */ @@ -1208,6 +1412,7 @@ typedef struct immap { ios512x_t ios; /* PCI Sequencer */ pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ u8 res7[0xa00]; +#endif ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ ioctrl512x_t io_ctrl; /* IO Control */ iim512x_t iim; /* IC Identification module */ @@ -1215,8 +1420,13 @@ typedef struct immap { lpc512x_t lpc; /* LocalPlus Controller */ pata512x_t pata; /* Parallel ATA */ u8 res9[0xd00]; +#ifdef CONFIG_ADS5125 + psc512x_t psc[10]; /* PSCs */ + u8 res10[0x500]; +#else psc512x_t psc[12]; /* PSCs */ u8 res10[0x300]; +#endif fifoc512x_t fifoc; /* FIFO Controller */ u8 res11[0x2000]; dma512x_t dma; /* DMA */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index ebc518c..35e69c4 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -28,6 +28,7 @@ #define __CONFIG_H #define CONFIG_MPC5121ADS 1 + /* * Memory map for the MPC5121ADS board: * diff --git a/include/configs/mpc5125ads.h b/include/configs/mpc5125ads.h new file mode 100644 index 0000000..2ba7ba3 --- /dev/null +++ b/include/configs/mpc5125ads.h @@ -0,0 +1,501 @@ +/* + * Copyright 2009 Silicon Turnkey Express, Inc. + * Martha Marx Stan <mmarx(a)silicontkx.com> + * + * This file is based on mpc5121ads.h + * (C) Copyright 2007-2009 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * MPC5125ADS board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC5125ADS /* MPC5125 Reference Board */ +#define CONFIG_MPC5125 /* MPC5125 processor */ +/* + * Memory map for the MPC5125ADS board: + * + * 0x0000_0000 - 0x00FF_FFFF DDR RAM (16 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x4000_0000 - 0x400F_FFFF NAND FLASH CONTROLLER + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif +/* + * Enable Fast boot + */ +#define CONFIG_FASTBOOT + +#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* DDR Controller Configuration + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +/* Runtime MDDRC Commands */ +#define CONFIG_SYS_MDDRC_SYS_CFG 0xea802bc0 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34a90864 + +/* Not using the mpc512x Default DDR init sequence */ +#define CONFIG_SYS_DDR_OVRIDE_DEF + +/* DRAM Commands */ +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 + +#define DDRCMD_EMR_OCD(pr, ohm) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (1 << 16) | /* MODE Reg BA[2:0] */ \ + (0 << 12) | /* Outputs 0=Enabled */ \ + (0 << 11) | /* RDQS */ \ + (1 << 10) | /* DQS# */ \ + (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ + /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ + ((ohm & 0x2) << 5)| /* Rtt1 */ \ + (0 << 3) | /* additive posted CAS# */ \ + ((ohm & 0x1) << 2)| /* Rtt0 */ \ + (0 << 0) | /* Output Drive Strength */ \ + (0 << 0)) /* DLL Enable 0=Normal */ + +/* ODT must be set to 50 Ohm */ +#define CONFIG_SYS_ELPIDA_OCD_DEFAULT DDRCMD_EMR_OCD(7, 2) +#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 2) + +#define DDR_CMD_MODE_REG(cas, wr) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (0 << 16) | /* MODE Reg BA[2:0] */ \ + ((wr-1) << 9)| /* Write Recovery */ \ + (cas << 4) | /* CAS */ \ + (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ + (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ + +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDR_CMD_MODE_REG(4, 4) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDR_CMD_MODE_REG(4, 4) | (1 << 8)) + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x2000000 /* max flash size in bytes */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * CPLD registers area is really only 32 bytes in size, but the smallest possible LP + * window is 64KB + */ +#define CONFIG_SYS_CPLD_BASE 0x82000000 +#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ +#define IS_CFG1_SWITCH (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x13)) & 0x80) + +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00008000 /* 32 KB */ + +#define CONFIG_SYS_CS0_CFG 0x05059110 /* ALE active low, data size 2bytes */ +#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ +#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ + +/* Special IO Pin Muxing done in Start.S */ +#define CONFIG_SYS_IOCTRL_MUX_CS2 0x43 /* start.S pin muxing for CS2 */ +#define CONFIG_IOCTRL_MUX_PSC9 0x23 /* start.S pin muxing for PSC9 if it's the console */ + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_SPLASH_SIZE (2 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_PSC_CONSOLE2 9 /* other console is on PSC9 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#if (CONFIG_PSC_CONSOLE == 1) +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC1_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC1_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC1_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC1_RX_ADDR +#elif (CONFIG_PSC_CONSOLE2 == 9) +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC9_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC9_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC9_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC9_RX_ADDR +#else +#error CONFIG_PSC_CONSOLE must be 1 or 9 +#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + +/* I2C */ +#define CONFIG_HARD_I2C /* defd in ads5121 I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#if 0 +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#endif + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 10ms of delay */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_PHY2_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + + +/* + * Environment + */ +#define CONFIG_SYS_BKUP_FLASH_SIZE 0x400000 /* smaller sized bkup flash is 4M */ +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_ENV_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_SYS_ENV_SECT_SIZE 0x20000 /* one sector (128K) for env */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_ENV_ADDR + CONFIG_SYS_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FUSE + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#endif +/* + * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5125e Reference Manual. + */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB + #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + + +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME mpc5125ads +#define CONFIG_BOOTFILE mpc5125ads/uImage +#define CONFIG_ROOTPATH /opt/eldk/pcc_6xx + +#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=300000\0" \ + "fdt_addr_r=400000\0" \ + "ramdisk_addr_r=500000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FC040000\0" \ + "fdt_addr=FC2C0000\0" \ + "ramdisk_addr=FC300000\0" \ + "ramdiskfile=mpc5125ads/uRamdisk\0" \ + "fdtfile=mpc5125ads/mpc5125ads.dtb\0" \ + "u-boot=mpc5125ads/u-boot.bin\0" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "" + +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5125@0" +#define OF_SOC_COMPAT "fsl,mpc5125-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ -- 1.5.2.4

3 2

[U-Boot] [PATCH] Don't inline weak symbols
by Ron 03 Oct '09

03 Oct '09

GCC 4.4 complains about this now. Signed-off-by: Ron Lee <ron(a)debian.org> --- lib_arm/board.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index a44d308..02a55eb 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -124,23 +124,23 @@ void *sbrk (ptrdiff_t increment) * May be supplied by boards if desired */ void inline __coloured_LED_init (void) {} -void inline coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); +void coloured_LED_init (void) __attribute__((weak, alias("__coloured_LED_init"))); void inline __red_LED_on (void) {} -void inline red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); +void red_LED_on (void) __attribute__((weak, alias("__red_LED_on"))); void inline __red_LED_off(void) {} -void inline red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); +void red_LED_off(void) __attribute__((weak, alias("__red_LED_off"))); void inline __green_LED_on(void) {} -void inline green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); +void green_LED_on(void) __attribute__((weak, alias("__green_LED_on"))); void inline __green_LED_off(void) {} -void inline green_LED_off(void)__attribute__((weak, alias("__green_LED_off"))); +void green_LED_off(void) __attribute__((weak, alias("__green_LED_off"))); void inline __yellow_LED_on(void) {} -void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on"))); +void yellow_LED_on(void) __attribute__((weak, alias("__yellow_LED_on"))); void inline __yellow_LED_off(void) {} -void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))); +void yellow_LED_off(void) __attribute__((weak, alias("__yellow_LED_off"))); void inline __blue_LED_on(void) {} -void inline blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on"))); +void blue_LED_on(void) __attribute__((weak, alias("__blue_LED_on"))); void inline __blue_LED_off(void) {} -void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off"))); +void blue_LED_off(void) __attribute__((weak, alias("__blue_LED_off"))); /************************************************************************ * Init Utilities * -- 1.6.3.3

3 7

[U-Boot] [PATCH/RFC] arm/microblaze/nios/nios2/sh: Remove relocation fixups
by Peter Tyser 03 Oct '09

03 Oct '09

These architectures don't need relocation fixups, so reduce their codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS. Also remove the reloc_off field from their global data structures as it is no longer needed. Note that the location of the standalone application jump table pointer in the global data structure is affected by this change, breaking execution of standalone applications compiled for previous versions of U-Boot. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- I apparently forgot to send this yesterday with the rest of the relocation patches. If the ppc relocation series just sent gets accepted, this change should cut out some unneeded code from other arches which don't use relocation fixups. I haven't compiled any of these arches though, so take the patch with a grain of salt. common/stdio.c | 4 ++-- include/asm-arm/config.h | 3 +++ include/asm-arm/global_data.h | 1 - include/asm-microblaze/config.h | 3 +++ include/asm-microblaze/global_data.h | 1 - include/asm-nios/config.h | 3 +++ include/asm-nios/global_data.h | 1 - include/asm-nios2/config.h | 3 +++ include/asm-nios2/global_data.h | 1 - include/asm-sh/config.h | 3 +++ include/asm-sh/global_data.h | 1 - 11 files changed, 17 insertions(+), 7 deletions(-) diff --git a/common/stdio.c b/common/stdio.c index 5e58dbe..870ddfd 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -201,7 +201,7 @@ int stdio_deregister(char *devname) int stdio_init (void) { -#if !defined(CONFIG_ARM) && !defined(CONFIG_RELOC_FIXUP_WORKS) +#if !defined(CONFIG_RELOC_FIXUP_WORKS) /* already relocated for current ARM implementation */ ulong relocation_offset = gd->reloc_off; int i; @@ -211,7 +211,7 @@ int stdio_init (void) stdio_names[i] = (char *) (((ulong) stdio_names[i]) + relocation_offset); } -#endif /* !ARM && !CONFIG_RELOC_FIXUP_WORKS */ +#endif /* !CONFIG_RELOC_FIXUP_WORKS */ /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); diff --git a/include/asm-arm/config.h b/include/asm-arm/config.h index 049c44e..b76fd8e 100644 --- a/include/asm-arm/config.h +++ b/include/asm-arm/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all ARM boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 5c56ce3..8115a24 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -38,7 +38,6 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h index 049c44e..8a9064b 100644 --- a/include/asm-microblaze/config.h +++ b/include/asm-microblaze/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all Microblaze boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h index 3f49c34..ec7837f 100644 --- a/include/asm-microblaze/global_data.h +++ b/include/asm-microblaze/global_data.h @@ -39,7 +39,6 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h index 049c44e..2efe898 100644 --- a/include/asm-nios/config.h +++ b/include/asm-nios/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all NIOS boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index 4929a5b..fa54ee4 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -31,7 +31,6 @@ typedef struct global_data { unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h index 049c44e..011d603 100644 --- a/include/asm-nios2/config.h +++ b/include/asm-nios2/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all NIOS2 boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index db71324..34aa962 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -30,7 +30,6 @@ typedef struct global_data { unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h index 049c44e..978cc92 100644 --- a/include/asm-sh/config.h +++ b/include/asm-sh/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all sh boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h index f8ade5c..c12b855 100644 --- a/include/asm-sh/global_data.h +++ b/include/asm-sh/global_data.h @@ -35,7 +35,6 @@ typedef struct global_data unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ void **jt; /* Standalone app jump table */ -- 1.6.2.1

2 1

[U-Boot] [PATCH V2] ppc4xx: Add SDRAM detection for PMC440 boards
by Matthias Fuchs 02 Oct '09

02 Oct '09

This patch adds support to detect the amount of DDR2 SDRAM on PMC440 modules. Detection is done by probing through a list of available and supported hardware configurations from 1GByte down to 256MB. The static TLB entry is replaced by dynamically created entries. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- V2: - remove duplicate comment - fix commit message - coding style cleanup board/esd/pmc440/init.S | 11 ++---- board/esd/pmc440/sdram.c | 82 ++++++++++++++++++++++++++++++++------------- include/configs/PMC440.h | 1 - 3 files changed, 61 insertions(+), 33 deletions(-) diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 26a8282..6585fed 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -23,7 +23,7 @@ #include <asm-ppc/mmu.h> #include <config.h> -/************************************************************************** +/* * TLB TABLE * * This table is used by the cpu boot code to setup the initial tlb @@ -32,7 +32,7 @@ * * Pointer to the table is returned in r1 * - *************************************************************************/ + */ .section .bootpg,"ax" .globl tlbtab @@ -49,12 +49,7 @@ tlbtab: tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#endif + /* TLB entries for DDR2 SDRAM are generated dynamically */ #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index bb46ecc..c3528bc 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh, matthias.fuchs(a)esd.eu + * * (C) Copyright 2006 * Sylvie Gohl, AMCC/IBM, gohl.sylvie(a)fr.ibm.com * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol(a)fr.ibm.com @@ -31,33 +34,30 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/mmu.h> #include <ppc440.h> extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); +struct sdram_conf_s { + ulong size; + int rows; + int banks; +}; -#if defined(CONFIG_NAND_SPL) -/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133000000 -#endif +struct sdram_conf_s sdram_conf[] = { + {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */ + {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */ + {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */ +}; -/************************************************************************* - * +/* * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) + */ +int initdram_by_rb(int rows, int banks) { -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#if !defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); -#else - ulong speed = 133333333; /* 133MHz is on the safe side */ -#endif mtsdram(DDR0_02, 0x00000000); @@ -89,21 +89,25 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); + + mtsdram(DDR0_42, + DDR0_42_ADDR_PINS_DECODE(14 - rows) | + 0x00000006); + mtsdram(DDR0_43, + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | + 0x030A0200); + mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ + /* * Perform data eye search if requested. - * ----------------------------------------------------------*/ + */ denali_core_search_data_eye(); #endif - /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when @@ -111,5 +115,35 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CONFIG_SYS_MBYTES_SDRAM << 20); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t size; + int n; + + /* go through supported memory configurations */ + for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) { + size = sdram_conf[n].size; + + /* program TLB entries */ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, size, + TLB_WORD2_I_ENABLE); + + /* + * setup denali core + */ + initdram_by_rb(sdram_conf[n].rows, + sdram_conf[n].banks); + + /* check for suitable configuration */ + if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) + return size; + + /* delete TLB entries */ + remove_tlb(CONFIG_SYS_SDRAM_BASE, size); + } + + return 0; } diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 012ae79..d6e2f6b 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -215,7 +215,6 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif -- 1.6.1

2 1

[U-Boot] [PATCH v2] ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
by Stefan Roese 02 Oct '09

02 Oct '09

This patch merges the ECC handling (ECC parity byte writing) into one file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. This exception is because only those PPC's use the completely different Denali SDRAM controller core. Previously we had two routines to generate/write the ECC parity bytes. With this patch we now only have one core function left. Tested on Kilauea (no ECC) and Katmai (with and without ECC). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Felix Radensky <felix(a)embedded-sol.com> Cc: Grant Erickson <gerickson(a)nuovations.com> Cc: Pieter Voorthuijsen <pv(a)prodrive.nl> --- v2: - Removed not referenced defines from ppc405.h cpu/ppc4xx/44x_spd_ddr2.c | 194 ++++------------------------------- cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 6 +- cpu/ppc4xx/ecc.c | 167 +++++++++++++++++++++--------- cpu/ppc4xx/ecc.h | 52 +++++---- include/asm-ppc/ppc4xx-sdram.h | 7 +- include/ppc405.h | 4 - 6 files changed, 173 insertions(+), 257 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 736e3cb..3975306 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -9,7 +9,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson <gerickson(a)nuovations.com> - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * COPYRIGHT AMCC CORPORATION 2004 @@ -48,6 +48,8 @@ #include <asm/mmu.h> #include <asm/cache.h> +#include "ecc.h" + #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ @@ -93,24 +95,11 @@ void dcbz_area(u32 start_address, u32 num_bytes); #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) -static unsigned long is_ecc_enabled(void); - -/*-----------------------------------------------------------------------------+ - * wait_ddr_idle - *-----------------------------------------------------------------------------*/ -static void wait_ddr_idle(void) -{ - u32 val; - - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); -} - +#if !defined(CONFIG_NAND_SPL) /*-----------------------------------------------------------------------------+ * sdram_memsize *-----------------------------------------------------------------------------*/ -static phys_size_t sdram_memsize(void) +phys_size_t sdram_memsize(void) { phys_size_t mem_size; unsigned long mcopt2; @@ -184,6 +173,18 @@ static phys_size_t sdram_memsize(void) } /*-----------------------------------------------------------------------------+ + * is_ecc_enabled + *-----------------------------------------------------------------------------*/ +static unsigned long is_ecc_enabled(void) +{ + unsigned long val; + + mfsdram(SDRAM_MCOPT1, val); + + return SDRAM_MCOPT1_MCHK_CHK_DECODE(val); +} + +/*-----------------------------------------------------------------------------+ * board_add_ram_info *-----------------------------------------------------------------------------*/ void board_add_ram_info(int use_default) @@ -198,12 +199,11 @@ void board_add_ram_info(int use_default) get_sys_info(&board_cfg); -#if defined(CONFIG_440) +#if defined(CONFIG_405EX) + val = board_cfg.freqPLB; +#else mfsdr(SDR0_DDR0, val); val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); -#else - mfsdr(SDR0_SDSTP0, val); - val = MULDIV64((board_cfg.freqPLB), SDR0_SDSTP0_PLB2xDV0_DECODE(val), 1); #endif printf(" enabled, %d MHz", (val * 2) / 1000000); @@ -211,112 +211,7 @@ void board_add_ram_info(int use_default) val = (val & SDRAM_MMODE_DCL_MASK) >> 4; printf(", CL%d)", val); } - -#ifdef CONFIG_DDR_ECC -/*-----------------------------------------------------------------------------+ - * program_ecc_addr. - *-----------------------------------------------------------------------------*/ -static void program_ecc_addr(unsigned long start_address, - unsigned long num_bytes, - unsigned long tlb_word2_i_value) -{ - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long mcopt1; - char str[] = "ECC generation -"; - char slash[] = "\\|/-\\|/-"; - int loop = 0; - int loopi = 0; - - current_address = start_address; - mfsdram(SDRAM_MCOPT1, mcopt1); - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); - sync(); - eieio(); - wait_ddr_idle(); - - puts(str); - -#ifdef CONFIG_440 - if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { -#endif - /* ECC bit set method for non-cached memory */ - if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) - address_increment = 4; - else - address_increment = 8; - end_address = current_address + num_bytes; - - while (current_address < end_address) { - *((unsigned long *)current_address) = 0x00000000; - current_address += address_increment; - - if ((loop++ % (2 << 20)) == 0) { - putc('\b'); - putc(slash[loopi++ % 8]); - } - } -#ifdef CONFIG_440 - } else { - /* ECC bit set method for cached memory */ - dcbz_area(start_address, num_bytes); - /* Write modified dcache lines back to memory */ - clean_dcache_range(start_address, start_address + num_bytes); - } -#endif /* CONFIG_440 */ - - blank_string(strlen(str)); - - sync(); - eieio(); - wait_ddr_idle(); - - /* clear ECC error repoting registers */ - mtsdram(SDRAM_ECCCR, 0xffffffff); - mtdcr(0x4c, 0xffffffff); - - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); - sync(); - eieio(); - wait_ddr_idle(); - } -} - -/*-----------------------------------------------------------------------------+ - * do_program_ecc. - *-----------------------------------------------------------------------------*/ -static void do_program_ecc(unsigned long tlb_word2_i_value) -{ - unsigned long mcopt1; - unsigned long mcopt2; - unsigned long mcstat; - phys_size_t memsize = sdram_memsize(); - - if (memsize > CONFIG_MAX_MEM_MAPPED) { - printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); - return; - } - - mfsdram(SDRAM_MCOPT1, mcopt1); - mfsdram(SDRAM_MCOPT2, mcopt2); - - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - /* DDR controller must be enabled and not in self-refresh. */ - mfsdram(SDRAM_MCSTAT, mcstat); - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - - program_ecc_addr(0, memsize, tlb_word2_i_value); - } - } -} -#endif /* CONFIG_DDR_ECC */ +#endif /* !CONFIG_NAND_SPL */ #if defined(CONFIG_SPD_EEPROM) @@ -439,7 +334,6 @@ typedef enum ddr_cas_id { /*-----------------------------------------------------------------------------+ * Prototypes *-----------------------------------------------------------------------------*/ -static phys_size_t sdram_memsize(void); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -2405,25 +2299,6 @@ static void program_memory_queue(unsigned long *dimm_populated, #endif } -/*-----------------------------------------------------------------------------+ - * is_ecc_enabled. - *-----------------------------------------------------------------------------*/ -static unsigned long is_ecc_enabled(void) -{ - unsigned long dimm_num; - unsigned long ecc; - unsigned long val; - - ecc = 0; - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { - mfsdram(SDRAM_MCOPT1, val); - ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val)); - } - - return ecc; -} - #ifdef CONFIG_DDR_ECC /*-----------------------------------------------------------------------------+ * program_ecc. @@ -2989,21 +2864,6 @@ static void test(void) #else /* CONFIG_SPD_EEPROM */ -/*-----------------------------------------------------------------------------+ - * is_ecc_enabled - *-----------------------------------------------------------------------------*/ -static unsigned long is_ecc_enabled(void) -{ - unsigned long ecc; - unsigned long val; - - ecc = 0; - mfsdram(SDRAM_MCOPT1, val); - ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val)); - - return ecc; -} - /*----------------------------------------------------------------------------- * Function: initdram * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. @@ -3225,18 +3085,6 @@ void mtdcr_any(u32 dcr, u32 val) } } #endif /* defined(CONFIG_440) */ - -void blank_string(int size) -{ - int i; - - for (i = 0; i < size; i++) - putc('\b'); - for (i = 0; i < size; i++) - putc(' '); - for (i = 0; i < size; i++) - putc('\b'); -} #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ inline void ppc4xx_ibm_ddr2_register_dump(void) diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 91bf582..0283c91 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -42,6 +42,8 @@ #include <asm/io.h> #include <asm/processor.h> +#include "ecc.h" + #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) /* @@ -177,7 +179,7 @@ static u32 *get_membase(int bxcr_num) static inline void ecc_clear_status_reg(void) { - mtsdram(SDRAM_ECCCR, 0xffffffff); + mtsdram(SDRAM_ECCES, 0xffffffff); #if defined(SDRAM_R0BAS) mtdcr(SDRAM_ERRSTATLL, 0xffffffff); #endif @@ -210,7 +212,7 @@ static int ecc_check_status_reg(void) * ecc error, then don't count * this as a passing value */ - mfsdram(SDRAM_ECCCR, ecc_status); + mfsdram(SDRAM_ECCES, ecc_status); if (ecc_status != 0x00000000) { /* clear on error */ ecc_clear_status_reg(); diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c index 3f989e7..f105605 100644 --- a/cpu/ppc4xx/ecc.c +++ b/cpu/ppc4xx/ecc.c @@ -2,7 +2,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson <gerickson(a)nuovations.com> * - * (C) Copyright 2005-2007 + * (C) Copyright 2005-2009 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * (C) Copyright 2002 @@ -42,81 +42,144 @@ #include <ppc_defs.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/mmu.h> +#include <asm/cache.h> #include "ecc.h" #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) + +#if defined(CONFIG_405EX) /* - * void ecc_init() - * - * Description: - * This routine initializes a range of DRAM ECC memory with known - * data and enables ECC checking. - * - * TO DO: - * - Improve performance by utilizing cache. - * - Further generalize to make usable by other 4xx variants (e.g. - * 440EPx, et al). - * - * Input(s): - * start - A pointer to the start of memory covered by ECC requiring - * initialization. - * size - The size, in bytes, of the memory covered by ECC requiring - * initialization. - * - * Output(s): - * start - A pointer to the start of memory covered by ECC with - * CONFIG_SYS_ECC_PATTERN written to all locations and ECC data - * primed. - * - * Returns: - * N/A + * Currently only 405EX uses 16bit data bus width as an alternative + * option to 32bit data width (SDRAM0_MCOPT1_WDTH) */ -void ecc_init(unsigned long * const start, unsigned long size) +#define SDRAM_DATA_ALT_WIDTH 2 +#else +#define SDRAM_DATA_ALT_WIDTH 8 +#endif + +static void wait_ddr_idle(void) { - const unsigned long pattern = CONFIG_SYS_ECC_PATTERN; - unsigned long * const end = (unsigned long * const)((long)start + size); - unsigned long * current = start; + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); +} + +static void program_ecc_addr(unsigned long start_address, + unsigned long num_bytes, + unsigned long tlb_word2_i_value) +{ + unsigned long current_address; + unsigned long end_address; + unsigned long address_increment; unsigned long mcopt1; - long increment; + char str[] = "ECC generation -"; + char slash[] = "\\|/-\\|/-"; + int loop = 0; + int loopi = 0; - if (start >= end) - return; + current_address = start_address; + mfsdram(SDRAM_MCOPT1, mcopt1); + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); + sync(); + eieio(); + wait_ddr_idle(); + + puts(str); - mfsdram(SDRAM_ECC_CFG, mcopt1); +#ifdef CONFIG_440 + if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { +#endif + /* ECC bit set method for non-cached memory */ + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) + address_increment = 4; + else + address_increment = SDRAM_DATA_ALT_WIDTH; + end_address = current_address + num_bytes; - /* Enable ECC generation without checking or reporting */ + while (current_address < end_address) { + *((unsigned long *)current_address) = 0; + current_address += address_increment; - mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | - SDRAM_ECC_CFG_MCHK_GEN)); + if ((loop++ % (2 << 20)) == 0) { + putc('\b'); + putc(slash[loopi++ % 8]); + } + } +#ifdef CONFIG_440 + } else { + /* ECC bit set method for cached memory */ + dcbz_area(start_address, num_bytes); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); + } +#endif /* CONFIG_440 */ - increment = sizeof(u32); + blank_string(strlen(str)); -#if defined(CONFIG_440) + sync(); + eieio(); + wait_ddr_idle(); + + /* clear ECC error repoting registers */ + mtsdram(SDRAM_ECCES, 0xffffffff); + mtdcr(0x4c, 0xffffffff); + + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); + sync(); + eieio(); + wait_ddr_idle(); + } +} + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) +void ecc_init(unsigned long * const start, unsigned long size) +{ /* - * Look at the geometry of SDRAM (data width) to determine whether we - * can skip words when writing. + * Init ECC with cache disabled (on PPC's with IBM DDR + * controller (non DDR2), not tested with cache enabled yet */ + program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE); +} +#endif - if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) - increment = sizeof(u64); -#endif /* defined(CONFIG_440) */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +void do_program_ecc(unsigned long tlb_word2_i_value) +{ + unsigned long mcopt1; + unsigned long mcopt2; + unsigned long mcstat; + phys_size_t memsize = sdram_memsize(); - while (current < end) { - *current = pattern; - current = (unsigned long *)((long)current + increment); + if (memsize > CONFIG_MAX_MEM_MAPPED) { + printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); + return; } - /* Wait until the writes are finished. */ + mfsdram(SDRAM_MCOPT1, mcopt1); + mfsdram(SDRAM_MCOPT2, mcopt2); - sync(); + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + /* DDR controller must be enabled and not in self-refresh. */ + mfsdram(SDRAM_MCSTAT, mcstat); + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - /* Enable ECC generation with checking and no reporting */ - - mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | - SDRAM_ECC_CFG_MCHK_CHK)); + program_ecc_addr(0, memsize, tlb_word2_i_value); + } + } } +#endif + #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ #endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h index 67c3bff..b258891 100644 --- a/cpu/ppc4xx/ecc.h +++ b/cpu/ppc4xx/ecc.h @@ -2,7 +2,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson <gerickson(a)nuovations.com> * - * Copyright (c) 2007 DENX Software Engineering, GmbH + * Copyright (c) 2007-2009 DENX Software Engineering, GmbH * Stefan Roese <sr(a)denx.de> * * See file CREDITS for list of people who contributed to this @@ -25,18 +25,13 @@ * * Description: * This file implements ECC initialization for PowerPC processors - * using the SDRAM DDR2 controller, including the 405EX(r), - * 440SP(E), 460EX and 460GT. + * using the IBM SDRAM DDR1 & DDR2 controller. * */ #ifndef _ECC_H_ #define _ECC_H_ -#if !defined(CONFIG_SYS_ECC_PATTERN) -#define CONFIG_SYS_ECC_PATTERN 0x00000000 -#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */ - /* * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT @@ -46,24 +41,35 @@ /* For 440GP/GX/EP/GR */ #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) -#define SDRAM_ECC_CFG SDRAM_CFG0 -#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK -#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN -#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK -#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK -#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32 -#endif +#define SDRAM_MCOPT1 SDRAM_CFG0 +#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK +#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON +#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN +#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK +#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK +#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK +#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32 + +#define SDRAM_MCSTAT SDRAM0_MCSTS +#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS +#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT -/* For 405EX/440SP/SPe/460EX/GT */ -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) -#define SDRAM_ECC_CFG SDRAM_MCOPT1 -#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK -#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN -#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK -#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK -#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32 +#define SDRAM_ECCES SDRAM0_ECCESR #endif -extern void ecc_init(unsigned long * const start, unsigned long size); +void ecc_init(unsigned long * const start, unsigned long size); +void do_program_ecc(unsigned long tlb_word2_i_value); + +static void inline blank_string(int size) +{ + int i; + + for (i = 0; i < size; i++) + putc('\b'); + for (i = 0; i < size; i++) + putc(' '); + for (i = 0; i < size; i++) + putc('\b'); +} #endif /* _ECC_H_ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index b6182d4..92be514 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -117,6 +117,7 @@ #define SDRAM_MCSTS_MRSC 0x80000000 #define SDRAM_MCSTS_SRMS 0x40000000 #define SDRAM_MCSTS_CIS 0x20000000 +#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */ /* * SDRAM Refresh Timer Register @@ -416,8 +417,7 @@ #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_ECCES SDRAM_ECCCR +#define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ @@ -1397,7 +1397,6 @@ /* * Prototypes */ -void inline blank_string(int size); inline void ppc4xx_ibm_ddr2_register_dump(void); u32 mfdcr_any(u32); void mtdcr_any(u32, u32); @@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32); u32 ddr_clktr(u32); void spd_ddr_init_hang(void); u32 DQS_autocalibration(void); +phys_size_t sdram_memsize(void); +void dcbz_area(u32 start_address, u32 num_bytes); #endif /* __ASSEMBLY__ */ #endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/ppc405.h b/include/ppc405.h index 8a4ba3f..5e56897 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -768,10 +768,6 @@ #define SDR0_SDCS_SDD (0x80000000 >> 31) -/* SDR0_SDSTP0 Serial Device Strap Register0 */ -#define SDR0_SDSTP0 0x0020 -#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07)) - /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -- 1.6.4.4

1 1

[U-Boot] [PATCH] ppc4xx: Reorganize DDR2 ECC handling
by Felix Radensky 02 Oct '09

02 Oct '09

Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky <felix(a)embedded-sol.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 456 ++++++++++++++++++++++++-------------------- include/ppc405.h | 4 + 2 files changed, 253 insertions(+), 207 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 2ab2336..ac8f9cb 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -48,8 +48,6 @@ #include <asm/mmu.h> #include <asm/cache.h> -#include "ecc.h" - #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \ @@ -86,8 +84,240 @@ /* disable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE #endif /* CONFIG_4xx_DCACHE */ + +void dcbz_area(u32 start_address, u32 num_bytes); +#endif /* CONFIG_440 */ + +#define MAXRANKS 4 +#define MAXBXCF 4 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +static unsigned long is_ecc_enabled(void); + +/*-----------------------------------------------------------------------------+ + * wait_ddr_idle + *-----------------------------------------------------------------------------*/ +static void wait_ddr_idle(void) +{ + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); +} + +/*-----------------------------------------------------------------------------+ + * sdram_memsize + *-----------------------------------------------------------------------------*/ +static phys_size_t sdram_memsize(void) +{ + phys_size_t mem_size; + unsigned long mcopt2; + unsigned long mcstat; + unsigned long mb0cf; + unsigned long sdsz; + unsigned long i; + + mem_size = 0; + + mfsdram(SDRAM_MCOPT2, mcopt2); + mfsdram(SDRAM_MCSTAT, mcstat); + + /* DDR controller must be enabled and not in self-refresh. */ + /* Otherwise memsize is zero. */ + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { + for (i = 0; i < MAXBXCF; i++) { + mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); + /* Banks enabled */ + if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { +#if defined(CONFIG_440) + sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; +#else + sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK; +#endif + switch(sdsz) { + case SDRAM_RXBAS_SDSZ_8: + mem_size+=8; + break; + case SDRAM_RXBAS_SDSZ_16: + mem_size+=16; + break; + case SDRAM_RXBAS_SDSZ_32: + mem_size+=32; + break; + case SDRAM_RXBAS_SDSZ_64: + mem_size+=64; + break; + case SDRAM_RXBAS_SDSZ_128: + mem_size+=128; + break; + case SDRAM_RXBAS_SDSZ_256: + mem_size+=256; + break; + case SDRAM_RXBAS_SDSZ_512: + mem_size+=512; + break; + case SDRAM_RXBAS_SDSZ_1024: + mem_size+=1024; + break; + case SDRAM_RXBAS_SDSZ_2048: + mem_size+=2048; + break; + case SDRAM_RXBAS_SDSZ_4096: + mem_size+=4096; + break; + default: + printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" + , sdsz); + mem_size=0; + break; + } + } + } + } + + return mem_size << 20; +} + +/*-----------------------------------------------------------------------------+ + * board_add_ram_info + *-----------------------------------------------------------------------------*/ +void board_add_ram_info(int use_default) +{ + PPC4xx_SYS_INFO board_cfg; + u32 val; + + if (is_ecc_enabled()) + puts(" (ECC"); + else + puts(" (ECC not"); + + get_sys_info(&board_cfg); + +#if defined(CONFIG_440) + mfsdr(SDR0_DDR0, val); + val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); +#else + mfsdr(SDR0_SDSTP0, val); + val = MULDIV64((board_cfg.freqPLB), SDR0_SDSTP0_PLB2xDV0_DECODE(val), 1); +#endif + printf(" enabled, %d MHz", (val * 2) / 1000000); + + mfsdram(SDRAM_MMODE, val); + val = (val & SDRAM_MMODE_DCL_MASK) >> 4; + printf(", CL%d)", val); +} + +#ifdef CONFIG_DDR_ECC +/*-----------------------------------------------------------------------------+ + * program_ecc_addr. + *-----------------------------------------------------------------------------*/ +static void program_ecc_addr(unsigned long start_address, + unsigned long num_bytes, + unsigned long tlb_word2_i_value) +{ + unsigned long current_address; + unsigned long end_address; + unsigned long address_increment; + unsigned long mcopt1; + char str[] = "ECC generation -"; + char slash[] = "\\|/-\\|/-"; + int loop = 0; + int loopi = 0; + + current_address = start_address; + mfsdram(SDRAM_MCOPT1, mcopt1); + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); + sync(); + eieio(); + wait_ddr_idle(); + + puts(str); + +#ifdef CONFIG_440 + if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { +#endif + /* ECC bit set method for non-cached memory */ + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) + address_increment = 4; + else + address_increment = 8; + end_address = current_address + num_bytes; + + while (current_address < end_address) { + *((unsigned long *)current_address) = 0x00000000; + current_address += address_increment; + + if ((loop++ % (2 << 20)) == 0) { + putc('\b'); + putc(slash[loopi++ % 8]); + } + } +#ifdef CONFIG_440 + } else { + /* ECC bit set method for cached memory */ + dcbz_area(start_address, num_bytes); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); + } #endif /* CONFIG_440 */ + blank_string(strlen(str)); + + sync(); + eieio(); + wait_ddr_idle(); + + /* clear ECC error repoting registers */ + mtsdram(SDRAM_ECCCR, 0xffffffff); + mtdcr(0x4c, 0xffffffff); + + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); + sync(); + eieio(); + wait_ddr_idle(); + } +} + +/*-----------------------------------------------------------------------------+ + * do_program_ecc. + *-----------------------------------------------------------------------------*/ +static void do_program_ecc(unsigned long tlb_word2_i_value) +{ + unsigned long mcopt1; + unsigned long mcopt2; + unsigned long mcstat; + phys_size_t memsize = sdram_memsize(); + + if (memsize > CONFIG_MAX_MEM_MAPPED) { + printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); + return; + } + + mfsdram(SDRAM_MCOPT1, mcopt1); + mfsdram(SDRAM_MCOPT2, mcopt2); + + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + /* DDR controller must be enabled and not in self-refresh. */ + mfsdram(SDRAM_MCSTAT, mcstat); + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { + + program_ecc_addr(0, memsize, tlb_word2_i_value); + } + } +} +#endif /* CONFIG_DDR_ECC */ + #if defined(CONFIG_SPD_EEPROM) /*-----------------------------------------------------------------------------+ @@ -105,14 +335,10 @@ #define SDRAM_NONE 0 #define MAXDIMMS 2 -#define MAXRANKS 4 -#define MAXBXCF 4 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ #define ONE_BILLION 1000000000 -#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) - #define CMD_NOP (7 << 19) #define CMD_PRECHARGE (2 << 19) #define CMD_REFRESH (1 << 19) @@ -257,15 +483,11 @@ static void program_initplr(unsigned long *dimm_populated, unsigned long num_dimm_banks, ddr_cas_id_t selected_cas, int write_recovery); -static unsigned long is_ecc_enabled(void); #ifdef CONFIG_DDR_ECC static void program_ecc(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks, unsigned long tlb_word2_i_value); -static void program_ecc_addr(unsigned long start_address, - unsigned long num_bytes, - unsigned long tlb_word2_i_value); #endif #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) static void program_DQS_calibration(unsigned long *dimm_populated, @@ -278,7 +500,6 @@ static void DQS_calibration_process(void); #endif #endif int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -void dcbz_area(u32 start_address, u32 num_bytes); static unsigned char spd_read(uchar chip, uint addr) { @@ -292,79 +513,6 @@ static unsigned char spd_read(uchar chip, uint addr) } /*-----------------------------------------------------------------------------+ - * sdram_memsize - *-----------------------------------------------------------------------------*/ -static phys_size_t sdram_memsize(void) -{ - phys_size_t mem_size; - unsigned long mcopt2; - unsigned long mcstat; - unsigned long mb0cf; - unsigned long sdsz; - unsigned long i; - - mem_size = 0; - - mfsdram(SDRAM_MCOPT2, mcopt2); - mfsdram(SDRAM_MCSTAT, mcstat); - - /* DDR controller must be enabled and not in self-refresh. */ - /* Otherwise memsize is zero. */ - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - for (i = 0; i < MAXBXCF; i++) { - mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); - /* Banks enabled */ - if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { - sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; - - switch(sdsz) { - case SDRAM_RXBAS_SDSZ_8: - mem_size+=8; - break; - case SDRAM_RXBAS_SDSZ_16: - mem_size+=16; - break; - case SDRAM_RXBAS_SDSZ_32: - mem_size+=32; - break; - case SDRAM_RXBAS_SDSZ_64: - mem_size+=64; - break; - case SDRAM_RXBAS_SDSZ_128: - mem_size+=128; - break; - case SDRAM_RXBAS_SDSZ_256: - mem_size+=256; - break; - case SDRAM_RXBAS_SDSZ_512: - mem_size+=512; - break; - case SDRAM_RXBAS_SDSZ_1024: - mem_size+=1024; - break; - case SDRAM_RXBAS_SDSZ_2048: - mem_size+=2048; - break; - case SDRAM_RXBAS_SDSZ_4096: - mem_size+=4096; - break; - default: - printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" - , sdsz); - mem_size=0; - break; - } - } - } - } - - return mem_size << 20; -} - -/*-----------------------------------------------------------------------------+ * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. * Note: This routine runs from flash with a stack set up in the chip's * sram space. It is important that the routine does not require .sbss, .bss or @@ -643,26 +791,6 @@ static void get_spd_info(unsigned long *dimm_populated, } } -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - if (is_ecc_enabled()) - puts(" (ECC"); - else - puts(" (ECC not"); - - get_sys_info(&board_cfg); - - mfsdr(SDR0_DDR0, val); - val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); - printf(" enabled, %d MHz", (val * 2) / 1000000); - - mfsdram(SDRAM_MMODE, val); - val = (val & SDRAM_MMODE_DCL_MASK) >> 4; - printf(", CL%d)", val); -} /*------------------------------------------------------------------ * For the memory DIMMs installed, this routine verifies that they @@ -2305,9 +2433,6 @@ static void program_ecc(unsigned long *dimm_populated, unsigned long num_dimm_banks, unsigned long tlb_word2_i_value) { - unsigned long mcopt1; - unsigned long mcopt2; - unsigned long mcstat; unsigned long dimm_num; unsigned long ecc; @@ -2321,105 +2446,7 @@ static void program_ecc(unsigned long *dimm_populated, if (ecc == 0) return; - if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) { - printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); - return; - } - - mfsdram(SDRAM_MCOPT1, mcopt1); - mfsdram(SDRAM_MCOPT2, mcopt2); - - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - /* DDR controller must be enabled and not in self-refresh. */ - mfsdram(SDRAM_MCSTAT, mcstat); - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - - program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value); - } - } - - return; -} - -static void wait_ddr_idle(void) -{ - u32 val; - - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); -} - -/*-----------------------------------------------------------------------------+ - * program_ecc_addr. - *-----------------------------------------------------------------------------*/ -static void program_ecc_addr(unsigned long start_address, - unsigned long num_bytes, - unsigned long tlb_word2_i_value) -{ - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long mcopt1; - char str[] = "ECC generation -"; - char slash[] = "\\|/-\\|/-"; - int loop = 0; - int loopi = 0; - - current_address = start_address; - mfsdram(SDRAM_MCOPT1, mcopt1); - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); - sync(); - eieio(); - wait_ddr_idle(); - - puts(str); - if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { - /* ECC bit set method for non-cached memory */ - if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) - address_increment = 4; - else - address_increment = 8; - end_address = current_address + num_bytes; - - while (current_address < end_address) { - *((unsigned long *)current_address) = 0x00000000; - current_address += address_increment; - - if ((loop++ % (2 << 20)) == 0) { - putc('\b'); - putc(slash[loopi++ % 8]); - } - } - - } else { - /* ECC bit set method for cached memory */ - dcbz_area(start_address, num_bytes); - /* Write modified dcache lines back to memory */ - clean_dcache_range(start_address, start_address + num_bytes); - } - - blank_string(strlen(str)); - - sync(); - eieio(); - wait_ddr_idle(); - - /* clear ECC error repoting registers */ - mtsdram(SDRAM_ECCCR, 0xffffffff); - mtdcr(0x4c, 0xffffffff); - - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); - sync(); - eieio(); - wait_ddr_idle(); - } + do_program_ecc(tlb_word2_i_value); } #endif @@ -2962,6 +2989,21 @@ static void test(void) #else /* CONFIG_SPD_EEPROM */ +/*-----------------------------------------------------------------------------+ + * is_ecc_enabled + *-----------------------------------------------------------------------------*/ +static unsigned long is_ecc_enabled(void) +{ + unsigned long ecc; + unsigned long val; + + ecc = 0; + mfsdram(SDRAM_MCOPT1, val); + ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val)); + + return ecc; +} + /*----------------------------------------------------------------------------- * Function: initdram * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller. @@ -3106,7 +3148,7 @@ phys_size_t initdram(int board_type) #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ #if defined(CONFIG_DDR_ECC) - ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); + do_program_ecc(0); #endif /* defined(CONFIG_DDR_ECC) */ #if defined(CONFIG_440) diff --git a/include/ppc405.h b/include/ppc405.h index 5e56897..8a4ba3f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -768,6 +768,10 @@ #define SDR0_SDCS_SDD (0x80000000 >> 31) +/* SDR0_SDSTP0 Serial Device Strap Register0 */ +#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP0_PLB2xDV0_DECODE(n) ((((unsigned long)(n)) & 0x07)) + /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -- 1.5.4.3

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[U-Boot] [PATCH] arm: Correct build with CONFIG_SYS_HUSH_PARSER set
by Simon Kagstrom 01 Oct '09

01 Oct '09

arm: Correct build with CONFIG_SYS_HUSH_PARSER set FLAG_PARSE_SEMICOLON is not defined without hush.h, so include that. Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- cpu/arm926ejs/kirkwood/cpu.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c index d0cdaf6..fbe754c 100644 --- a/cpu/arm926ejs/kirkwood/cpu.c +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -27,6 +27,7 @@ #include <asm/cache.h> #include <u-boot/md5.h> #include <asm/arch/kirkwood.h> +#include <hush.h> #define BUFLEN 16 -- 1.6.0.4

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[U-Boot] About DM6467_config
by Kazuaki Ichinohe 01 Oct '09

01 Oct '09

Hello, Please describe configuration (make xxxx_config) of DM6467. Can I use the davinci_dvevm_config ? Regards, Kazuaki Ichinohe

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