September 2009 - U-Boot

[U-Boot] [PATCH] arm_cortexa8: support cache flush to other soc
by Minkyu Kang 10 Sep '09

10 Sep '09

Current code is supported only omap3 soc. this patch will support s5pc1xx(s5pc100 and s5pc110) soc also. Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- cpu/arm_cortexa8/cpu.c | 24 +++++++++++------------- 1 files changed, 11 insertions(+), 13 deletions(-) diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 5a5981e..3d430b1 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -35,9 +35,6 @@ #include <command.h> #include <asm/system.h> #include <asm/cache.h> -#ifndef CONFIG_L2_OFF -#include <asm/arch/sys_proto.h> -#endif static void cache_flush(void); @@ -61,17 +58,18 @@ int cleanup_before_linux(void) cache_flush(); #ifndef CONFIG_L2_OFF - /* turn off L2 cache */ - l2_cache_disable(); - /* invalidate L2 cache also */ - v7_flush_dcache_all(get_device_type()); -#endif - i = 0; - /* mem barrier to sync up things */ - asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + if (get_device_type() != 0xC100) { + /* turn off L2 cache */ + l2_cache_disable(); + /* invalidate L2 cache also */ + v7_flush_dcache_all(get_device_type()); -#ifndef CONFIG_L2_OFF - l2_cache_enable(); + i = 0; + /* mem barrier to sync up things */ + asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + + l2_cache_enable(); + } #endif return 0; -- 1.5.4.3

8 22

[U-Boot] [PATCH] Add new Elpida memory configuration for mpc5121ads board
by Martha M Stan 10 Sep '09

10 Sep '09

From: Martha Marx <mmarx(a)silicontkx.com> Rev 3 and earlier stay with Micron settings. Rev 4 boards manufactured before Nov-2008 Serial Number #1180 also stay with Micron settings. All new boards use a slightly slower Elpida setting. CONFIG_SYS_ELPIDA_MICRON_MIX sets up this detection and use. Signed-off-by: Martha Marx Stan <mmarx(a)silicontkx.com> --- board/freescale/mpc5121ads/mpc5121ads.c | 34 ++++++++++++ cpu/mpc512x/fixed_sdram.c | 88 +++++++++++++++++++++++------- include/configs/mpc5121ads.h | 36 ++++++++----- 3 files changed, 124 insertions(+), 34 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index a0d7a82..c6bbbad 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -34,6 +34,9 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX +#include <net.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -133,6 +136,37 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX +u32 is_micron(void){ + + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + uchar macaddr[6]; + u32 brddate, macchk, ismicron; + + /* + * MAC address has serial number with date of manufacture + * Boards made before Nov-08 #1180 use Micron memory; + * 001e59 is the STx vendor # + * Default is Elpida since it works for both but is slightly slower + */ + ismicron = 0; + if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t",brddate); + + if (macchk == 0x001e59 && brddate <= 8111180) + ismicron = 1; + } else if (brd_rev < 0x400) { + debug("Board is pre-Rev4:"); + ismicron = 1; + } + debug("Using %s Memory settings\n\t", + ismicron ? "Micron" : "Elpida"); + return(ismicron); +} +#endif + phys_size_t initdram(int board_type) { u32 msize = 0; diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 5be02f7..063f60a 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -25,6 +25,9 @@ #include <asm/io.h> #include <asm/mpc512x.h> +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX +extern u32 is_micron(void); +#endif /* * fixed sdram init: * The board doesn't use memory modules that have serial presence @@ -36,6 +39,11 @@ long int fixed_sdram(void) u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); u32 i; +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX + u32 use_micron = is_micron(); +#else + u32 use_micron = 1; +#endif /* Initialize IO Control */ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); @@ -74,10 +82,19 @@ long int fixed_sdram(void) out_be32(&im->mddrc.lut_table4_alternate_lower, MDDRCGRP_LUT4_AL); /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2); + if (use_micron) { + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2); +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX + } else { + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_ELPIDA); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1_ELPIDA); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2_ELPIDA); +#endif + } /* Initialize DDR */ for (i = 0; i < 10; i++) @@ -89,25 +106,54 @@ long int fixed_sdram(void) out_be32(&im->mddrc.ddr_command, DDR_NOP); out_be32(&im->mddrc.ddr_command, DDR_RFSH); out_be32(&im->mddrc.ddr_command, DDR_NOP); - out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, DDR_NOP); - out_be32(&im->mddrc.ddr_command, DDR_EM2); - out_be32(&im->mddrc.ddr_command, DDR_NOP); - out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, DDR_EM2); - out_be32(&im->mddrc.ddr_command, DDR_EM3); - out_be32(&im->mddrc.ddr_command, DDR_EN_DLL); - out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, DDR_RFSH); - out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, DDR_NOP); + if (use_micron) { + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_EM3); + out_be32(&im->mddrc.ddr_command, DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + + /* Start MDDRC */ + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN); + +#ifdef CONFIG_SYS_ELPIDA_MICRON_MIX + } else { + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_EM3); + out_be32(&im->mddrc.ddr_command, DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command, DDR_RES_DLL); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_ELPIDA_INIT_DEV_OP); + udelay(200); + out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, DDR_OCD_EXIT); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, DDR_OCD_EXIT); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + for (i = 0; i < 10; i++) + out_be32(&im->mddrc.ddr_command, DDR_NOP); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_ELPIDA_RUN); +#endif + } return msize; } diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 5df51e3..a618b16 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -85,6 +85,7 @@ #endif #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_ELPIDA_MICRON_MIX /* DDR Controller Configuration * @@ -130,29 +131,38 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ + #ifdef CONFIG_MPC5121ADS_REV2 -#define MDDRC_SYS_CFG 0xF8604A00 -#define MDDRC_SYS_CFG_RUN 0xE8604A00 -#define MDDRC_TIME_CFG1 0x54EC1168 -#define MDDRC_TIME_CFG2 0x35210864 +#define MDDRC_SYS_CFG 0xF8604A00 +#define MDDRC_TIME_CFG1 0x54EC1168 +#define MDDRC_TIME_CFG2 0x35210864 #else -#define MDDRC_SYS_CFG 0xFA804A00 -#define MDDRC_SYS_CFG_RUN 0xEA804A00 -#define MDDRC_TIME_CFG1 0x68EC1168 -#define MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG 0xFA804A00 +#define MDDRC_SYS_CFG_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1 0x68EC1168 +#define MDDRC_TIME_CFG2 0x34310864 #endif -#define MDDRC_SYS_CFG_EN 0xF0000000 -#define MDDRC_TIME_CFG0 0x00003D2E -#define MDDRC_TIME_CFG0_RUN 0x06183D2E - +#define MDDRC_SYS_CFG_ELPIDA 0xFA802B00 +#define MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802B00 +#define MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define MDDRC_TIME_CFG2_ELPIDA 0x35310864 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E +#define MDDRC_SYS_CFG_EN 0xF0000000 + +#define DDR_MRS_CAS(n) (n << 4) +#define DDR_MRS_WR(n) ((n-1) << 9) +#define DDR_MICRON_INIT_DEV_OP 0x01000002 | DDR_MRS_WR(2) | DDR_MRS_CAS(3) +#define DDR_ELPIDA_INIT_DEV_OP 0x01000002 | DDR_MRS_WR(4) | DDR_MRS_CAS(4) #define DDR_NOP 0x01380000 #define DDR_PCHG_ALL 0x01100400 #define DDR_EM2 0x01020000 #define DDR_EM3 0x01030000 #define DDR_EN_DLL 0x01010000 +#define DDR_RES_DLL 0x01000932 #define DDR_RFSH 0x01080000 -#define DDR_MICRON_INIT_DEV_OP 0x01000432 #define DDR_OCD_DEFAULT 0x01010780 +#define DDR_OCD_EXIT 0x01010400 /* DDR Priority Manager Configuration */ #define MDDRCGRP_PM_CFG1 0x00077777 -- 1.5.2.4

2 1

Re: [U-Boot] [PATCH v3] AT91: Problems with SD
by Albin Tonnerre 10 Sep '09

10 Sep '09

Hi Konrad, On Thu, 10 Sep 2009 08:58 +0200, Konrad Mattheis wrote : > I will try this later on the day. What is the Base for this patch? Again 2009.08 or do I have > to apply other patches? 2009.08 is fine. > You wrote in this message that this is a port to the new generic mmc api. > Do I also have to make different initialization? Like CONFIG_GENERIC_MMC instead of CONFIG_AT91_MMC You need CONFIG_GENERIC_MMC in addition to CONFIG_ATMEL_MCI, not instead of. Regards, -- Albin Tonnerre, Free Electrons Kernel, drivers and embedded Linux development, consulting, training and support. http://free-electrons.com

1 0

[U-Boot] Our competition sells these lists for $2500 and more
by Luciano U Palmer 10 Sep '09

10 Sep '09

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1 0

[U-Boot] [PATCH] MCI support for AT91 family processors.
by Sami Kantoluoto 10 Sep '09

10 Sep '09

Fixed to parse CSD correctly on little endian processors as gcc orders bitfields differently between big and little endian ones. Signed-off-by: Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> --- drivers/mmc/atmel_mci.c | 55 ++++++++++++++++++++++++++++++++++++-- include/asm-arm/arch-at91/clk.h | 5 +++ 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 3946ffe..c2837a8 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -282,6 +282,53 @@ static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) cid->mdt = (resp[3] >> 8) & 0x0fff; } +static void mmc_parse_csd(struct mmc_csd *csd, unsigned long *resp) +{ +#if __BYTE_ORDER == __BIG_ENDIAN + memcpy(csd, resp, sizeof(csd)); +#elif __BYTE_ORDER == __LITTLE_ENDIAN + csd->csd_structure = resp[0] >> 30; + csd->spec_vers = resp[0] >> 26; + csd->rsvd1 = resp[0] >> 24; + csd->taac = resp[0] >> 16; + csd->nsac = resp[0] >> 8; + csd->tran_speed = resp[0] & 0xff; + csd->ccc = resp[1] >> 20; + csd->read_bl_len = resp[1] >> 16; + csd->read_bl_partial = resp[1] >> 15; + csd->write_blk_misalign = resp[1] >> 14; + csd->read_blk_misalign = resp[1] >> 13; + csd->dsr_imp = resp[1] >> 12; + csd->rsvd2 = resp[1] >> 10; + csd->c_size = (resp[1] << 2) | (resp[2] >> 30); + csd->vdd_r_curr_min = resp[2] >> 27; + csd->vdd_r_curr_max = resp[2] >> 24; + csd->vdd_w_curr_min = resp[2] >> 21; + csd->vdd_w_curr_max = resp[2] >> 18; + csd->c_size_mult = resp[2] >> 15; + csd->sector_size = resp[2] >> 10; + csd->erase_grp_size = resp[2] >> 5; + csd->wp_grp_size = resp[2] & 0x1f; + csd->wp_grp_enable = resp[3] >> 31; + csd->default_ecc = resp[3] >> 29; + csd->r2w_factor = resp[3] >> 26; + csd->write_bl_len = resp[3] >> 22; + csd->write_bl_partial = resp[3] >> 21; + csd->rsvd3 = resp[3] >> 16; + + csd->file_format_grp = resp[3] >> 15; + csd->copy = resp[3] >> 14; + csd->perm_write_protect = resp[3] >> 13; + csd->tmp_write_protect = resp[3] >> 12; + csd->file_format = resp[3] >> 10; + csd->ecc = resp[3] >> 8; + csd->crc = resp[3] >> 1; + csd->one = resp[3] & 1; +#else +#error Unsupported __BYTE_ORDER +#endif +} + static void mmc_dump_cid(const struct mmc_cid *cid) { printf("Manufacturer ID: %02X\n", cid->mid); @@ -298,7 +345,7 @@ static void mmc_dump_csd(const struct mmc_csd *csd) { unsigned long *csd_raw = (unsigned long *)csd; printf("CSD data: %08lx %08lx %08lx %08lx\n", - csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); + ntohl(csd_raw[0]), ntohl(csd_raw[1]), ntohl(csd_raw[2]), ntohl(csd_raw[3])); printf("CSD structure version: 1.%u\n", csd->csd_structure); printf("MMC System Spec version: %u\n", csd->spec_vers); printf("Card command classes: %03x\n", csd->ccc); @@ -368,7 +415,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) /* Get RCA of the card that responded */ ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); - if (ret) + if (ret) return ret; mmc_rca = resp[0] >> 16; @@ -468,6 +515,7 @@ int mmc_legacy_init(int verbose) struct mmc_cid cid; struct mmc_csd csd; unsigned int max_blksz; + unsigned long resp[4]; int ret; /* Initialize controller */ @@ -488,9 +536,10 @@ int mmc_legacy_init(int verbose) return ret; /* Get CSD from the card */ - ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR); + ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, resp, R2 | NCR); if (ret) return ret; + mmc_parse_csd(&csd, resp); if (verbose) mmc_dump_csd(&csd); diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index f642dd9..26b537c 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -54,6 +54,11 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + static inline unsigned long get_twi_clk_rate(unsigned int dev_id) { return get_mck_clk_rate(); -- 1.6.0.4

3 5

[U-Boot] [PATCH v4 5/5][repost] tools: mkimage: Add: Kirkwood Boot Image support (kwbimage)
by Prafulla Wadaskar 10 Sep '09

10 Sep '09

This patch adds type kwbimage support for new mkimage core For more details refer docs/README.kwbimage This patch is tested with Sheevaplug board Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> Acked-by: Ron Lee <ron(a)debian.org> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- v2: updated as per review comments for v1 added len checks in checksum functions added printable strings for each valid table entry use of sccanf not changed since it offers return value for failure v3: resolved merge issues on mkimage branch v4: added warning fix on amd64 Use an intermediate type as large as the pointers we do simple arithmetic with. Use a format string type that suits the sizeof type from KWBIMAGE_MAX_CONFIG. The compiler warns about both of these on amd64. included kwbimage.o in the build dependency calculations _GNU_SOURCE defined to obtain getline prototype from stdio.h most of these changes suggested by Ron Lee (in cc list) v4 repost: typos corrected in commit message Makefile | 5 + common/image.c | 1 + doc/README.kwbimage | 93 ++++++++++++ include/image.h | 1 + tools/Makefile | 5 + tools/kwbimage.c | 405 +++++++++++++++++++++++++++++++++++++++++++++++++++ tools/kwbimage.h | 106 +++++++++++++ tools/mkimage.c | 2 + tools/mkimage.h | 1 + 9 files changed, 619 insertions(+), 0 deletions(-) create mode 100644 doc/README.kwbimage create mode 100644 tools/kwbimage.c create mode 100644 tools/kwbimage.h diff --git a/Makefile b/Makefile index 329e0f5..7d7637a 100644 --- a/Makefile +++ b/Makefile @@ -314,6 +314,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ +$(obj)u-boot.kwb: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \ + -a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -3671,6 +3675,7 @@ clobber: clean @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) + @rm -f $(obj)u-boot.kwb @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm diff --git a/common/image.c b/common/image.c index e8ecfa5..d0f169d 100644 --- a/common/image.c +++ b/common/image.c @@ -139,6 +139,7 @@ static table_entry_t uimage_type[] = { { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { -1, "", "", }, }; diff --git a/doc/README.kwbimage b/doc/README.kwbimage new file mode 100644 index 0000000..2a5b3b3 --- /dev/null +++ b/doc/README.kwbimage @@ -0,0 +1,93 @@ +--------------------------------------------- +Kirkwood Boot Image generation using mkimage +--------------------------------------------- + +This document describes the U-Boot feature as it +is implemented for the Kirkwood family of SoCs. + +The Kirkwood SoC's can boot directly from NAND FLASH, +SPI FLASH, SATA etc. using its internal bootRom support. + +for more details refer section 24.2 of Kirkwood functional specifications. +ref: www.marvell.com/products/embedded.../kirkwood/index.jsp + +Command syntax: +-------------- +./tools/mkimage -l <kwboot_file> + to list the kwb image file details + +./tools/mkimage -n <board specific configuration file> \ + -T kwbimage -a <start address> -e <execution address> \ + -d <input_raw_binary> <output_kwboot_file> + +for ex. +./tools/mkimage -n ./board/Marvell/openrd_base/kwbimage.cfg \ + -T kwbimage -a 0x00600000 -e 0x00600000 \ + -d u-boot.bin u-boot.kwb + +kwimage support available with mkimage utility will generate kirkwood boot +image that can be flashed on the board NAND/SPI flash + +Board specific configuration file specifications: +------------------------------------------------ +1. This file must present in the $(BOARDDIR) and the name should be + kwbimage.cfg (since this is used in Makefile) +2. This file can have empty lines and lines starting with "#" as first + character to put comments +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line is must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + BOOT_FROM nand/spi/sata + NAND_ECC_MODE default/rs/hamming/disabled + NAND_PAGE_SIZE any uint16_t hex value + SATA_PIO_MODE any uint32_t hex value + DDR_INIT_DELAY any uint32_t hex value + DATA regaddr and regdara hex value + you can have maximum 55 such register programming commands + +3. All commands are optional to program + +Typical example of kwimage.cfg file: +----------------------------------- + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b +# DRAM Configuration +DATA 0xFFD01400 0x43000c30 +DATA 0xFFD01404 0x37543000 +DATA 0xFFD01408 0x22125451 +DATA 0xFFD0140C 0x00000a33 +DATA 0xFFD01410 0x000000cc +DATA 0xFFD01414 0x00000000 +DATA 0xFFD01418 0x00000000 +DATA 0xFFD0141C 0x00000C52 +DATA 0xFFD01420 0x00000040 +DATA 0xFFD01424 0x0000F17F +DATA 0xFFD01428 0x00085520 +DATA 0xFFD0147C 0x00008552 +DATA 0xFFD01504 0x0FFFFFF1 +DATA 0xFFD01508 0x10000000 +DATA 0xFFD0150C 0x0FFFFFF5 +DATA 0xFFD01514 0x00000000 +DATA 0xFFD0151C 0x00000000 +DATA 0xFFD01494 0x00030000 +DATA 0xFFD01498 0x00000000 +DATA 0xFFD0149C 0x0000E803 +DATA 0xFFD01480 0x00000001 +# End of Header extension +DATA 0x0 0x0 + +------------------------------------------------ +Author: Prafulla Wadaskar <prafulla(a)marvell.com> diff --git a/include/image.h b/include/image.h index 58f13f9..0a5d39b 100644 --- a/include/image.h +++ b/include/image.h @@ -155,6 +155,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index d5c23fd..b04e3f3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -99,6 +99,7 @@ OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o +OBJ_FILES-y += kwbimage.o OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o OBJ_FILES-y += os_support.o @@ -189,6 +190,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)default_image.o \ $(obj)fit_image.o \ $(obj)image.o \ + $(obj)kwbimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ @@ -218,6 +220,9 @@ $(obj)fit_image.o: $(SRCTREE)/tools/fit_image.c $(obj)image.o: $(SRCTREE)/common/image.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< +$(obj)kwbimage.o: $(SRCTREE)/tools/kwbimage.c + $(CC) -g $(FIT_CFLAGS) -c -o $@ $< + $(obj)mkimage.o: $(SRCTREE)/tools/mkimage.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< diff --git a/tools/kwbimage.c b/tools/kwbimage.c new file mode 100644 index 0000000..28dc2d6 --- /dev/null +++ b/tools/kwbimage.c @@ -0,0 +1,405 @@ +/* + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Required to obtain the getline prototype from stdio.h */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "kwbimage.h" + +/* + * Supported commands for configuration file + */ +static table_entry_t kwbimage_cmds[] = { + {CMD_BOOT_FROM, "BOOT_FROM", "boot comand", }, + {CMD_NAND_ECC_MODE, "NAND_ECC_MODE", "NAND mode", }, + {CMD_NAND_PAGE_SIZE, "NAND_PAGE_SIZE", "NAND size", }, + {CMD_SATA_PIO_MODE, "SATA_PIO_MODE", "SATA mode", }, + {CMD_DDR_INIT_DELAY, "DDR_INIT_DELAY", "DDR init dly", }, + {CMD_DATA, "DATA", "Reg Write Data", }, + {CMD_INVALID, "", "", }, +}; + +/* + * Supported Boot options for configuration file + */ +static table_entry_t kwbimage_bootops[] = { + {IBR_HDR_SPI_ID, "spi", "SPI Flash", }, + {IBR_HDR_NAND_ID, "nand", "NAND Flash", }, + {IBR_HDR_SATA_ID, "sata", "Sata port", }, + {IBR_HDR_PEX_ID, "pex", "PCIe port", }, + {IBR_HDR_UART_ID, "uart", "Serial port", }, + {-1, "", "Invalid", }, +}; + +/* + * Supported NAND ecc options configuration file + */ +static table_entry_t kwbimage_eccmodes[] = { + {IBR_HDR_ECC_DEFAULT, "default", "Default mode", }, + {IBR_HDR_ECC_FORCED_HAMMING, "hamming", "Hamming mode", }, + {IBR_HDR_ECC_FORCED_RS, "rs", "RS mode", }, + {IBR_HDR_ECC_DISABLED, "disabled", "ECC Disabled", }, + {-1, "", "", }, +}; + +static struct kwb_header kwbimage_header; +static int datacmd_cnt = 0; +static char * fname = "Unknown"; +static int lineno = -1; + +/* + * Report Error if xflag is set in addition to default + */ +static int kwbimage_check_params (struct mkimage_params *params) +{ + if (!strlen (params->imagename)) { + printf ("Error:%s - Configuration file not specified, " + "it is needed for kwbimage generation\n", + params->cmdname); + return CFG_INVALID; + } + return ((params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen (params->imagename))); +} + +static uint32_t check_get_hexval (char *token) +{ + uint32_t hexval; + + if (!sscanf (token, "%x", &hexval)) { + printf ("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit (EXIT_FAILURE); + } + return hexval; +} + +/* + * Generates 8 bit checksum + */ +static uint8_t kwbimage_checksum8 (void *start, uint32_t len, uint8_t csum) +{ + register uint8_t sum = csum; + volatile uint8_t *p = (volatile uint8_t *)start; + + /* check len and return zero checksum if invalid */ + if (!len) + return 0; + + do { + sum += *p; + p++; + } while (--len); + return (sum); +} + +/* + * Generates 32 bit checksum + */ +static uint32_t kwbimage_checksum32 (uint32_t *start, uint32_t len, uint32_t csum) +{ + register uint32_t sum = csum; + volatile uint32_t *p = start; + + /* check len and return zero checksum if invalid */ + if (!len) + return 0; + + if (len % sizeof(uint32_t)) { + printf ("Error:%s[%d] - lenght is not in multiple of %d\n", + __FUNCTION__, len, sizeof(uint32_t)); + return 0; + } + + do { + sum += *p; + p++; + len -= sizeof(uint32_t); + } while (len > 0); + return (sum); +} + +static void kwbimage_check_cfgdata (char *token, enum kwbimage_cmd cmdsw, + struct kwb_header *kwbhdr) +{ + bhr_t *mhdr = &kwbhdr->kwb_hdr; + extbhr_t *exthdr = &kwbhdr->kwb_exthdr; + int i; + + switch (cmdsw) { + case CMD_BOOT_FROM: + i = get_table_entry_id (kwbimage_bootops, + "Kwbimage boot option", token); + + if (i < 0) + goto INVL_DATA; + + mhdr->blockid = i; + printf ("Preparing kirkwood boot image to boot " + "from %s\n", token); + break; + case CMD_NAND_ECC_MODE: + i = get_table_entry_id (kwbimage_eccmodes, + "NAND ecc mode", token); + + if (i < 0) + goto INVL_DATA; + + mhdr->nandeccmode = i; + printf ("Nand ECC mode = %s\n", token); + break; + case CMD_NAND_PAGE_SIZE: + mhdr->nandpagesize = + (uint16_t) check_get_hexval (token); + printf ("Nand page size = 0x%x\n", mhdr->nandpagesize); + break; + case CMD_SATA_PIO_MODE: + mhdr->satapiomode = + (uint8_t) check_get_hexval (token); + printf ("Sata PIO mode = 0x%x\n", + mhdr->satapiomode); + break; + case CMD_DDR_INIT_DELAY: + mhdr->ddrinitdelay = + (uint16_t) check_get_hexval (token); + printf ("DDR init delay = %d msec\n", mhdr->ddrinitdelay); + break; + case CMD_DATA: + exthdr->rcfg[datacmd_cnt].raddr = + check_get_hexval (token); + + break; + case CMD_INVALID: + goto INVL_DATA; + default: + goto INVL_DATA; + } + return; + +INVL_DATA: + printf ("Error:%s[%d] - Invalid data\n", fname, lineno); + exit (EXIT_FAILURE); +} + +/* + * this function sets the kwbimage header by- + * 1. Abstracting input command line arguments data + * 2. parses the kwbimage configuration file and update extebded header data + * 3. calculates header, extended header and image checksums + */ +static void kwdimage_set_ext_header (struct kwb_header *kwbhdr, char* name) { + bhr_t *mhdr = &kwbhdr->kwb_hdr; + extbhr_t *exthdr = &kwbhdr->kwb_exthdr; + FILE *fd = NULL; + int j; + char *line = NULL; + char * token, *saveptr1, *saveptr2; + size_t len = 0; + enum kwbimage_cmd cmd; + + fname = name; + /* set dram register offset */ + exthdr->dramregsoffs = (intptr_t)&exthdr->rcfg - (intptr_t)mhdr; + + if ((fd = fopen (name, "r")) == 0) { + printf ("Error:%s - Can't open\n", fname); + exit (EXIT_FAILURE); + } + + /* Simple kwimage.cfg file parser */ + lineno=0; + while ((getline (&line, &len, fd)) > 0) { + lineno++; + token = strtok_r (line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + + for (j = 0, cmd = CMD_INVALID, line = token; ; line = NULL) { + token = strtok_r (line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + + /* Process rest as valid config command line */ + switch (j) { + case CFG_COMMAND: + cmd = get_table_entry_id (kwbimage_cmds, + "Kwbimage command", token); + + if (cmd == CMD_INVALID) + goto INVL_CMD; + break; + + case CFG_DATA0: + kwbimage_check_cfgdata (token, cmd, kwbhdr); + break; + + case CFG_DATA1: + if (cmd != CMD_DATA) + goto INVL_CMD; + + exthdr->rcfg[datacmd_cnt].rdata = + check_get_hexval (token); + + if (datacmd_cnt > KWBIMAGE_MAX_CONFIG ) { + printf ("Error:%s[%d] - Found more " + "than max(%zd) allowed " + "data configurations\n", + fname, lineno, + KWBIMAGE_MAX_CONFIG); + exit (EXIT_FAILURE); + } else + datacmd_cnt++; + break; + + default: + goto INVL_CMD; + } + j++; + } + } + if (line) + free (line); + + fclose (fd); + return; + +/* + * Invalid Command error reporring + * + * command CMD_DATA needs three strings on a line + * whereas other commands need only two. + * + * if more than two/three (as per command type) are observed, + * then error will be reported + */ +INVL_CMD: + printf ("Error:%s[%d] - Invalid command\n", fname, lineno); + exit (EXIT_FAILURE); +} + +static void kwbimage_set_header (void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + struct kwb_header *hdr = (struct kwb_header *)ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + extbhr_t *exthdr = &hdr->kwb_exthdr; + uint32_t checksum; + int size; + + /* Build and add image checksum header */ + checksum = kwbimage_checksum32 ((uint32_t *)ptr, sbuf->st_size, 0); + + size = write (ifd, &checksum, sizeof(uint32_t)); + if (size != sizeof(uint32_t)) { + printf ("Error:%s - Checksum write %d bytes %s\n", + params->cmdname, size, params->imagefile); + exit (EXIT_FAILURE); + } + + sbuf->st_size += sizeof(uint32_t); + + mhdr->blocksize = sbuf->st_size - sizeof(struct kwb_header); + mhdr->srcaddr = sizeof(struct kwb_header); + mhdr->destaddr= params->addr; + mhdr->execaddr =params->ep; + mhdr->ext = 0x1; /* header extension appended */ + + kwdimage_set_ext_header (hdr, params->imagename); + /* calculate checksums */ + mhdr->checkSum = kwbimage_checksum8 ((void *)mhdr, sizeof(bhr_t), 0); + exthdr->checkSum = kwbimage_checksum8 ((void *)exthdr, + sizeof(extbhr_t), 0); +} + +static int kwbimage_verify_header (unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct kwb_header *hdr = (struct kwb_header *)ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + extbhr_t *exthdr = &hdr->kwb_exthdr; + uint8_t calc_hdrcsum; + uint8_t calc_exthdrcsum; + + calc_hdrcsum = kwbimage_checksum8 ((void *)mhdr, + sizeof(bhr_t) - sizeof(uint8_t), 0); + if (calc_hdrcsum != mhdr->checkSum) + return -FDT_ERR_BADSTRUCTURE; /* mhdr csum not matched */ + + calc_exthdrcsum = kwbimage_checksum8 ((void *)exthdr, + sizeof(extbhr_t) - sizeof(uint8_t), 0); + if (calc_hdrcsum != mhdr->checkSum) + return -FDT_ERR_BADSTRUCTURE; /* exthdr csum not matched */ + + return 0; +} + +static void kwbimage_print_header (const void *ptr) +{ + struct kwb_header *hdr = (struct kwb_header *) ptr; + bhr_t *mhdr = &hdr->kwb_hdr; + char *name = get_table_entry_name (kwbimage_bootops, + "Kwbimage boot option", + (int) mhdr->blockid); + + printf ("Image Type: Kirkwood Boot from %s Image\n", name); + printf ("Data Size: "); + genimg_print_size (mhdr->blocksize - sizeof(uint32_t)); + printf ("Load Address: %08x\n", mhdr->destaddr); + printf ("Entry Point: %08x\n", mhdr->execaddr); +} + +static int kwbimage_check_image_types (uint8_t type) +{ + if (type == IH_TYPE_KWBIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +/* + * kwbimage type parameters definition + */ +static struct image_type_params kwbimage_params = { + .name = "Kirkwood Boot Image support", + .header_size = sizeof(struct kwb_header), + .hdr = (void*)&kwbimage_header, + .check_image_type = kwbimage_check_image_types, + .verify_header = kwbimage_verify_header, + .print_header = kwbimage_print_header, + .set_header = kwbimage_set_header, + .check_params = kwbimage_check_params, +}; + +void init_kwb_image_type (void) +{ + mkimage_register (&kwbimage_params); +} diff --git a/tools/kwbimage.h b/tools/kwbimage.h new file mode 100644 index 0000000..3d3d5e9 --- /dev/null +++ b/tools/kwbimage.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KWBIMAGE_H_ +#define _KWBIMAGE_H_ + +#include <stdint.h> + +#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) +#define MAX_TEMPBUF_LEN 32 + +/* NAND ECC Mode */ +#define IBR_HDR_ECC_DEFAULT 0x00 +#define IBR_HDR_ECC_FORCED_HAMMING 0x01 +#define IBR_HDR_ECC_FORCED_RS 0x02 +#define IBR_HDR_ECC_DISABLED 0x03 + +/* Boot Type - block ID */ +#define IBR_HDR_I2C_ID 0x4D +#define IBR_HDR_SPI_ID 0x5A +#define IBR_HDR_NAND_ID 0x8B +#define IBR_HDR_SATA_ID 0x78 +#define IBR_HDR_PEX_ID 0x9C +#define IBR_HDR_UART_ID 0x69 +#define IBR_DEF_ATTRIB 0x00 + +enum kwbimage_cmd { + CMD_INVALID, + CMD_BOOT_FROM, + CMD_NAND_ECC_MODE, + CMD_NAND_PAGE_SIZE, + CMD_SATA_PIO_MODE, + CMD_DDR_INIT_DELAY, + CMD_DATA +}; + +enum kwbimage_cmd_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_DATA0, + CFG_DATA1 +}; + +/* typedefs */ +typedef struct bhr_t { + uint8_t blockid; /*0 */ + uint8_t nandeccmode; /*1 */ + uint16_t nandpagesize; /*2-3 */ + uint32_t blocksize; /*4-7 */ + uint32_t rsvd1; /*8-11 */ + uint32_t srcaddr; /*12-15 */ + uint32_t destaddr; /*16-19 */ + uint32_t execaddr; /*20-23 */ + uint8_t satapiomode; /*24 */ + uint8_t rsvd3; /*25 */ + uint16_t ddrinitdelay; /*26-27 */ + uint16_t rsvd2; /*28-29 */ + uint8_t ext; /*30 */ + uint8_t checkSum; /*31 */ +} bhr_t, *pbhr_t; + +struct reg_config { + uint32_t raddr; + uint32_t rdata; +}; + +typedef struct extbhr_t { + uint32_t dramregsoffs; + uint8_t rsrvd1[0x20 - sizeof(uint32_t)]; + struct reg_config rcfg[KWBIMAGE_MAX_CONFIG]; + uint8_t rsrvd2[7]; + uint8_t checkSum; +} extbhr_t, *pextbhr_t; + +struct kwb_header { + bhr_t kwb_hdr; + extbhr_t kwb_exthdr; +}; + +/* + * functions + */ +void init_kwb_image_type (void); + +#endif /* _KWBIMAGE_H_ */ diff --git a/tools/mkimage.c b/tools/mkimage.c index c43b207..ab6ea32 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -148,6 +148,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Kirkwood Boot image generation/list support */ + init_kwb_image_type (); /* Init FIT image generation/list support */ init_fit_image_type (); /* Init Default image generation/list support */ diff --git a/tools/mkimage.h b/tools/mkimage.h index 1e92825..47ebc19 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -140,6 +140,7 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void init_kwb_image_type (void); void init_default_image_type (void); void init_fit_image_type (void); -- 1.5.3.3

2 3

[U-Boot] Please pull u-boot-mpc85xx - master branch
by Kumar Gala 10 Sep '09

10 Sep '09

The following changes since commit 21170c80a83f1e60ce7f6f83005e06a5c2d15a8e: Poonam Aggrwal (1): ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Kumar Gala (2): ppc/85xx: Clean up do_reset ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address board/freescale/mpc8536ds/config.mk | 2 ++ board/freescale/mpc8572ds/config.mk | 2 ++ board/freescale/p1_p2_rdb/config.mk | 2 ++ board/freescale/p2020ds/config.mk | 2 ++ config.mk | 4 ++++ cpu/mpc85xx/cpu.c | 25 +++++++++---------------- cpu/mpc85xx/u-boot.lds | 10 +++++++--- 7 files changed, 28 insertions(+), 19 deletions(-)

2 1

[U-Boot] [PATCH 1/5] tools: mkimage: Include default/fit_image.o in the build dependency calculations
by Prafulla Wadaskar 10 Sep '09

10 Sep '09

This makes sure it gets rebuilt if any of the headers it includes are modified Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> Acked-by: Ron Lee <ron(a)debian.org> --- tools/Makefile | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 858b0e8..d5c23fd 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -93,7 +93,9 @@ EXT_OBJ_FILES-y += lib_generic/sha1.o # Source files located in the tools directory OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o +OBJ_FILES-y += default_image.o OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o +OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o -- 1.5.3.3

2 8

[U-Boot] [PATCH] ppc/85xx: Don't enable interrupts before we're ready
by Kumar Gala 10 Sep '09

10 Sep '09

From: Scott Wood <scottwood(a)freescale.com> We cannot handle any exceptions while running in AS1, as the exceptions will transition back to AS0 without a valid mapping. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- cpu/mpc85xx/start.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e21a4eb..eaed0e0 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -278,8 +278,8 @@ _start_e500: msync tlbwe - lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h - ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS@h + ori r6,r6,MSR_IS|MSR_DS@l lis r7,switch_as@h ori r7,r7,switch_as@l -- 1.6.0.6

1 0

[U-Boot] [PATCH v6 2/2 resend] arm: A320: Add support for Faraday A320 evaluation board
by ratbert.chuang＠gmail.com 10 Sep '09

10 Sep '09

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/faraday/a320evb/Makefile | 51 ++++++++ board/faraday/a320evb/a320evb.c | 73 +++++++++++ board/faraday/a320evb/config.mk | 35 +++++ board/faraday/a320evb/lowlevel_init.S | 118 +++++++++++++++++ cpu/arm920t/a320/Makefile | 47 +++++++ cpu/arm920t/a320/ftsmc020.c | 51 ++++++++ cpu/arm920t/a320/reset.S | 22 ++++ cpu/arm920t/a320/timer.c | 193 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/a320.h | 35 +++++ include/asm-arm/arch-a320/ftpmu010.h | 190 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/ftsdmc020.h | 103 +++++++++++++++ include/asm-arm/arch-a320/ftsmc020.h | 79 ++++++++++++ include/asm-arm/arch-a320/fttmr010.h | 73 +++++++++++ include/configs/a320evb.h | 222 +++++++++++++++++++++++++++++++++ 17 files changed, 1300 insertions(+), 0 deletions(-) create mode 100644 board/faraday/a320evb/Makefile create mode 100644 board/faraday/a320evb/a320evb.c create mode 100644 board/faraday/a320evb/config.mk create mode 100644 board/faraday/a320evb/lowlevel_init.S create mode 100644 cpu/arm920t/a320/Makefile create mode 100644 cpu/arm920t/a320/ftsmc020.c create mode 100644 cpu/arm920t/a320/reset.S create mode 100644 cpu/arm920t/a320/timer.c create mode 100644 include/asm-arm/arch-a320/a320.h create mode 100644 include/asm-arm/arch-a320/ftpmu010.h create mode 100644 include/asm-arm/arch-a320/ftsdmc020.h create mode 100644 include/asm-arm/arch-a320/ftsmc020.h create mode 100644 include/asm-arm/arch-a320/fttmr010.h create mode 100644 include/configs/a320evb.h diff --git a/MAINTAINERS b/MAINTAINERS index 79873f3..aa54bdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -533,6 +533,10 @@ Rick Bronson <rick(a)efn.org> AT91RM9200DK at91rm9200 +Po-Yu Chuang <ratbert(a)faraday-tech.com> + + a320evb FA526 (ARM920T-like) (a320 SoC) + George G. Davis <gdavis(a)mvista.com> assabet SA1100 diff --git a/MAKEALL b/MAKEALL index 5882ceb..7c742b6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -505,6 +505,7 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ + a320evb \ ap920t \ ap922_XA10 \ ap926ejs \ diff --git a/Makefile b/Makefile index c9d315a..a3fb0b8 100644 --- a/Makefile +++ b/Makefile @@ -2661,6 +2661,9 @@ shannon_config : unconfig ## ARM92xT Systems ######################################################################### +a320evb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320 + ######################################################################### ## Atmel AT91RM9200 Systems ######################################################################### diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile new file mode 100644 index 0000000..74f660d --- /dev/null +++ b/board/faraday/a320evb/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := a320evb.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c new file mode 100644 index 0000000..2aaa7a7 --- /dev/null +++ b/board/faraday/a320evb/a320evb.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + ftsmc020_init (); /* initialize Flash */ + return 0; +} + +int dram_init (void) +{ + void *sdram_base = PHYS_SDRAM_1; + unsigned long expected_size = PHYS_SDRAM_1_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size(sdram_base, expected_size); + + gd->bd->bi_dram[0].start = sdram_base; + gd->bd->bi_dram[0].size = actual_size; + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return 0; +} + +int board_eth_init (bd_t *bd) +{ + return ftmac100_initialize (bd); +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/faraday/a320evb/config.mk b/board/faraday/a320evb/config.mk new file mode 100644 index 0000000..aa25b98 --- /dev/null +++ b/board/faraday/a320evb/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2009 Faraday Technology +# Po-Yu Chuang <ratbert(a)faraday-tech.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM +# +# 1000'0000 to 1400'0000 +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# +# we load ourself to 13f8'0000 +# +# download area is 1200'0000 + +TEXT_BASE = 0x13f80000 diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S new file mode 100644 index 0000000..97718c0 --- /dev/null +++ b/board/faraday/a320evb/lowlevel_init.S @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/macro.h> +#include <asm/arch/ftsdmc020.h> + +/* + * parameters for the SDRAM controller + */ +#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0) +#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1) +#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR) +#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR) +#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR) + +#define TP0_D CONFIG_SYS_FTSDMC020_TP0 +#define TP1_D CONFIG_SYS_FTSDMC020_TP1 +#define CR_D1 FTSDMC020_CR_IPREC +#define CR_D2 FTSDMC020_CR_ISMR +#define CR_D3 FTSDMC020_CR_IREF + +#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(PHYS_SDRAM_1)) +#define ACR_D FTSDMC020_ACR_TOC(0x18) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + ldr r0, =CONFIG_FTSDMC020_BASE +1: + ldr r1, [r0, #FTSDMC020_OFFSET_CR] + cmp r1, #0 + bne 1b +.endm + +.globl lowlevel_init +lowlevel_init: + mov r11, lr + + led 0x0 + + bl init_sdmc + + led 0x1 + + /* everything is fine now */ + mov lr, r11 + mov pc, lr + +/* + * memory initialization + */ +init_sdmc: + led 0x10 + + /* set SDRAM register */ + + write32 TP0_A, TP0_D + led 0x11 + + write32 TP1_A, TP1_D + led 0x12 + + /* set to precharge */ + write32 CR_A, CR_D1 + led 0x13 + + wait_sdram + led 0x14 + + /* set mode register */ + write32 CR_A, CR_D2 + led 0x15 + + wait_sdram + led 0x16 + + /* set to refresh */ + write32 CR_A, CR_D3 + led 0x17 + + wait_sdram + led 0x18 + + write32 B0_BSR_A, B0_BSR_D + led 0x19 + + write32 ACR_A, ACR_D + led 0x1a + + mov pc, lr diff --git a/cpu/arm920t/a320/Makefile b/cpu/arm920t/a320/Makefile new file mode 100644 index 0000000..f030c53 --- /dev/null +++ b/cpu/arm920t/a320/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS += reset.o +COBJS += timer.o +COBJS += ftsmc020.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/a320/ftsmc020.c b/cpu/arm920t/a320/ftsmc020.c new file mode 100644 index 0000000..3d00fa8 --- /dev/null +++ b/cpu/arm920t/a320/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + +static void ftsmc020_setup_bank (unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf ("bank # %u invalid\n", bank); + return; + } + + writel (cfg->config, &smc->bank[bank].cr); + writel (cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init (void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (config); i++) + ftsmc020_setup_bank (i, &config[i]); +} diff --git a/cpu/arm920t/a320/reset.S b/cpu/arm920t/a320/reset.S new file mode 100644 index 0000000..12ca527 --- /dev/null +++ b/cpu/arm920t/a320/reset.S @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +.global reset_cpu +reset_cpu: + b reset_cpu diff --git a/cpu/arm920t/a320/timer.c b/cpu/arm920t/a320/timer.c new file mode 100644 index 0000000..bc134b6 --- /dev/null +++ b/cpu/arm920t/a320/timer.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + +#define TIMER_CLOCK 32768 +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init (void) +{ + unsigned int oscc; + unsigned int cr; + + debug ("%s()\n", __func__); + + /* disable timers */ + writel (0, &tmr->cr); + + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel (oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl (&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc |= FTPMU010_OSCC_RTCLSEL; + writel (oscc, &pmu->OSCC); + + /* setup timer */ + writel (TIMER_LOAD_VAL, &tmr->timer3_load); + writel (TIMER_LOAD_VAL, &tmr->timer3_counter); + writel (0, &tmr->timer3_match1); + writel (0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel (FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl (&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel (cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked (); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked (void) +{ + /* capure current decrementer value time */ + lastdec = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug ("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer (void) +{ + debug ("%s()\n", __func__); + reset_timer_masked (); +} + +/* + * return timer ticks + */ +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug ("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer (ulong base) +{ + debug ("%s(%lx)\n", __func__, base); + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + debug ("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug ("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks (void) +{ + debug ("%s()\n", __func__); + return get_timer (0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + debug ("%s()\n", __func__); + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h new file mode 100644 index 0000000..5c0a097 --- /dev/null +++ b/include/asm-arm/arch-a320/a320.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __A320_H +#define __A320_H + +/* + * Hardware register bases + */ +#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ +#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ +#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ +#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ +#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ + +#endif /* __A320_H */ + diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h new file mode 100644 index 0000000..7044131 --- /dev/null +++ b/include/asm-arm/arch-a320/ftpmu010.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#define FTPMU010_OFFSET_IDNMBR0 0x00 +#define FTPMU010_OFFSET_OSCC 0x08 +#define FTPMU010_OFFSET_PMODE 0x0C +#define FTPMU010_OFFSET_PMCR 0x10 +#define FTPMU010_OFFSET_PED 0x14 +#define FTPMU010_OFFSET_PEDSR 0x18 +#define FTPMU010_OFFSET_PMSR 0x20 +#define FTPMU010_OFFSET_PGSR 0x24 +#define FTPMU010_OFFSET_MFPSR 0x28 +#define FTPMU010_OFFSET_MISC 0x2C +#define FTPMU010_OFFSET_PDLLCR0 0x30 +#define FTPMU010_OFFSET_PDLLCR1 0x34 +#define FTPMU010_OFFSET_AHBMCLKOFF 0x38 +#define FTPMU010_OFFSET_APBMCLKOFF 0x3C +#define FTPMU010_OFFSET_DCSRCR0 0x40 +#define FTPMU010_OFFSET_DCSRCR1 0x44 +#define FTPMU010_OFFSET_DCSRCR2 0x48 +#define FTPMU010_OFFSET_SDRAMHTC 0x4C +#define FTPMU010_OFFSET_PSPR0 0x50 +#define FTPMU010_OFFSET_PSPR1 0x54 +#define FTPMU010_OFFSET_PSPR2 0x58 +#define FTPMU010_OFFSET_PSPR3 0x5C +#define FTPMU010_OFFSET_PSPR4 0x60 +#define FTPMU010_OFFSET_PSPR5 0x64 +#define FTPMU010_OFFSET_PSPR6 0x68 +#define FTPMU010_OFFSET_PSPR7 0x6C +#define FTPMU010_OFFSET_PSPR8 0x70 +#define FTPMU010_OFFSET_PSPR9 0x74 +#define FTPMU010_OFFSET_PSPR10 0x78 +#define FTPMU010_OFFSET_PSPR11 0x7C +#define FTPMU010_OFFSET_PSPR12 0x80 +#define FTPMU010_OFFSET_PSPR13 0x84 +#define FTPMU010_OFFSET_PSPR14 0x88 +#define FTPMU010_OFFSET_PSPR15 0x8C +#define FTPMU010_OFFSET_AHBDMA_RACCS 0x90 +#define FTPMU010_OFFSET_JSS 0x9C +#define FTPMU010_OFFSET_CFC_RACC 0xA0 +#define FTPMU010_OFFSET_SSP1_RACC 0xA4 +#define FTPMU010_OFFSET_UART1TX_RACC 0xA8 +#define FTPMU010_OFFSET_UART1RX_RACC 0xAC +#define FTPMU010_OFFSET_UART2TX_RACC 0xB0 +#define FTPMU010_OFFSET_UART2RX_RACC 0xB4 +#define FTPMU010_OFFSET_SDC_RACC 0xB8 +#define FTPMU010_OFFSET_I2SAC97_RACC 0xBC +#define FTPMU010_OFFSET_IRDATX_RACC 0xC0 +#define FTPMU010_OFFSET_USBD_RACC 0xC8 +#define FTPMU010_OFFSET_IRDARX_RACC 0xCC +#define FTPMU010_OFFSET_IRDA_RACC 0xD0 +#define FTPMU010_OFFSET_ED0_RACC 0xD4 +#define FTPMU010_OFFSET_ED1_RACC 0xD8 + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h new file mode 100644 index 0000000..0699772 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h new file mode 100644 index 0000000..43dfa61 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init (void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/asm-arm/arch-a320/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h new file mode 100644 index 0000000..fcc5563 --- /dev/null +++ b/include/configs/a320evb.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/a320.h> + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ + +/*----------------------------------------------------------------------- + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x13F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x00000000 +#define PHYS_FLASH_2 0x00400000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x00060000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif /* __CONFIG_H */ -- 1.6.3.3

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