September 2009 - U-Boot

[U-Boot] [PATCH] ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS
by Kumar Gala 11 Sep '09

11 Sep '09

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Makefile | 7 +------ include/configs/MPC8572DS.h | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 0c134f3..ae72553 100644 --- a/Makefile +++ b/Makefile @@ -2514,12 +2514,7 @@ MPC8569MDS_config: unconfig MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale + @$(MKCONFIG) -n $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale P2020DS_36BIT_config \ P2020DS_config: unconfig diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 55c1f29..9d59117 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_MPC8572DS_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- 1.6.0.6

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[U-Boot] [PATCH] ppc/85xx: Clean up do_reset
by Kumar Gala 10 Sep '09

10 Sep '09

There is no reason to do a run time check for e500 v1 based cores to determine if we have the GUTs RSTCR facility. Only the first generation of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if we are e500 v2 would miss future parts (like e500mc). Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/cpu.c | 25 +++++++++---------------- 1 files changed, 9 insertions(+), 16 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 8b3810f..bdd9ee4 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -153,27 +153,15 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - uint pvr; - uint ver; +/* Everything after the first generation of PQ3 parts has RSTCR */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) unsigned long val, msr; - pvr = get_pvr(); - ver = PVR_VER(pvr); - - if (ver & 1){ - /* e500 v2 core has reset control register */ - volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); - *rstcr = 0x2; /* HRESET_REQ */ - udelay(100); - } - /* - * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 - * Make sure MSR[DE] = 1 + * Make sure MSR[DE] = 1. This only resets the core. */ - msr = mfmsr (); msr |= MSR_DE; mtmsr (msr); @@ -181,6 +169,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); +#else + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */ + udelay(100); +#endif return 1; } -- 1.6.0.6

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[U-Boot] [PATCH v1 1/2] mkconfig: pass the board name to board config file
by Mingkai Hu 10 Sep '09

10 Sep '09

then we can handle the different config target in the board file, which simplify the top makefile for board that have multiple config targets. Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- mkconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/mkconfig b/mkconfig index b0bbbd1..9efd2fa 100755 --- a/mkconfig +++ b/mkconfig @@ -82,6 +82,7 @@ else > config.h # Create new config file fi echo "/* Automatically generated - do not edit */" >>config.h +echo "#define CONFIG_MK_${BOARD_NAME} 1" >>config.h echo "#include <configs/$1.h>" >>config.h echo "#include <asm/config.h>" >>config.h -- 1.6.4

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[U-Boot] [PATCH][v1] muas3001: remove BRG clock node fixup to use common mpc8260 code.
by Marcel Ziswiler 10 Sep '09

10 Sep '09

Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> --- board/muas3001/muas3001.c | 16 ---------------- 1 files changed, 0 insertions(+), 16 deletions(-) diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 8f83dd9..bf4ccb6 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -310,7 +310,6 @@ void ft_blob_update (void *blob, bd_t *bd) int ret, nodeoffset = 0; ulong memory_data[2] = {0}; ulong flash_data[4] = {0}; - ulong freq = 0; ulong speed = 0; memory_data[0] = cpu_to_be32 (bd->bi_memstart); @@ -359,21 +358,6 @@ void ft_blob_update (void *blob, bd_t *bd) "err:%s\n", fdt_strerror (nodeoffset)); } - /* brg clock */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg"); - if (nodeoffset >= 0) { - freq = cpu_to_be32 (bd->bi_brgfreq); - ret = fdt_setprop (blob, nodeoffset, "clock-frequency", &freq, - sizeof (unsigned long)); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node " - "err:%s\n", fdt_strerror (nodeoffset)); - } - /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); if (nodeoffset >= 0) { -- 1.6.0.4

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[U-Boot] [PATCH][v1] r7780mp: fix typo in Ethernet chip model number comment.
by Marcel Ziswiler 10 Sep '09

10 Sep '09

Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> --- include/configs/r7780mp.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 7738a17..71c570e 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -154,7 +154,7 @@ #define CONFIG_NET_MULTI #define CONFIG_RTL8169 */ -/* AX88696L Support(NE2000 base chip) */ +/* AX88796L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 -- 1.6.0.4

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[U-Boot] [PATCH][v3] ep8248: add support for device tree and secondary Ethernet interface.
by Marcel Ziswiler 10 Sep '09

10 Sep '09

Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> --- board/ep8248/ep8248.c | 16 ++++++++++++- include/configs/ep8248.h | 53 ++++++++++++++++++++-------------------------- 2 files changed, 37 insertions(+), 32 deletions(-) diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c index bc20ba7..eb11418 100644 --- a/board/ep8248/ep8248.c +++ b/board/ep8248/ep8248.c @@ -5,6 +5,10 @@ * Support for Embedded Planet EP8248 boards. * Tested on EP8248E. * + * Copyright (C) 2009 Noser Engineering AG + * Marcel Ziswiler <marcel.ziswiler(a)noser.com> + * Added support for device tree and secondary Ethernet interface + * * See file CREDITS for list of people who contributed to this * project. * @@ -35,8 +39,8 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1) const iop_conf_t iop_conf_tab[4][32] = { @@ -261,3 +265,11 @@ int checkboard(void) return 0; } + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup( blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index f7b3fde..b1dbe7d 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -4,6 +4,10 @@ * * U-Boot configuration for Embedded Planet EP8248 boards. * + * Copyright (C) 2009 Noser Engineering AG + * Marcel Ziswiler <marcel.ziswiler(a)noser.com> + * Added support for device tree and secondary Ethernet interface + * * See file CREDITS for list of people who contributed to this * project. * @@ -50,50 +54,41 @@ #define CONFIG_SYS_BCSR 0xFA000000 -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ +/* Pass open firmware flat device tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" + +/* Select ethernet configuration */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) +#define CONFIG_NET_MULTI +#define CONFIG_SYS_CPMFCR_RAMTYPE 0 +#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHER_ON_FCC1 1 /* - Rx clock is CLK10 * - Tx clock is CLK11 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHER_ON_FCC2 1 /* - Rx clock is CLK13 * - Tx clock is CLK14 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ +#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) #define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ @@ -113,8 +108,6 @@ #define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - #ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif -- 1.6.0.4

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[U-Boot] [PATCH][v1] mpc8260: remove Ethernet node fixup to use generic FDT code.
by Marcel Ziswiler 10 Sep '09

10 Sep '09

Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its configs for the common mpc8260 code to use generic Ethernet fixup. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)noser.com> --- board/keymile/mgcoge/mgcoge.c | 5 ----- board/muas3001/muas3001.c | 15 --------------- include/configs/mgcoge.h | 1 + include/configs/muas3001.h | 1 + 4 files changed, 2 insertions(+), 20 deletions(-) diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index d24a4b5..b16a01c 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -25,7 +25,6 @@ #include <mpc8260.h> #include <ioports.h> #include <malloc.h> -#include <net.h> #include <asm/io.h> #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -373,10 +372,6 @@ void ft_blob_update (void *blob, bd_t *bd) flash_reg[5] = cpu_to_be32 (info->size); fdt_set_node_and_value (blob, "/localbus/flash@5,0", "reg", flash_reg, sizeof (flash_reg)); - - /* MAC addr */ - fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address", - bd->bi_enetaddr, sizeof (u8) * 6); } void ft_board_setup (void *blob, bd_t *bd) diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index bf4ccb6..36caed8 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -342,21 +342,6 @@ void ft_blob_update (void *blob, bd_t *bd) printf ("ft_blob_update(): cannot find /localbus node " "err:%s\n", fdt_strerror (nodeoffset)); } - /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - uchar ethaddr[6]; - eth_getenv_enetaddr("ethaddr", ethaddr); - ret = fdt_setprop (blob, nodeoffset, "mac-address", ethaddr, - sizeof (uchar) * 6); - if (ret < 0) - printf ("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " - "property err:%s\n", fdt_strerror (ret)); - } else { - /* memory node is required in dts */ - printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror (nodeoffset)); - } /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 99ac8c1..55d1fc9 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -70,6 +70,7 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index f2d117c..c94daa3 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -74,6 +74,7 @@ #define CONFIG_ETHER_INDEX 1 #define CONFIG_ETHER_ON_FCC1 +#define CONFIG_HAS_ETH0 #define FCC_ENET /* -- 1.6.0.4

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[U-Boot] [PATCH] Remove "atmel_df_pow2" binary with "make clean"
by Wolfgang Denk 10 Sep '09

10 Sep '09

Commit 65f6f07b added support for the atmel_df_pow2 standalone program but missed to add a rule to remove it to the "clean" make target. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- Makefile | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 0449a5b..54610c6 100644 --- a/Makefile +++ b/Makefile @@ -3717,6 +3717,7 @@ grsim_leon2_config : unconfig clean: @rm -f $(obj)examples/standalone/82559_eeprom \ + $(obj)examples/standalone/atmel_df_pow2 \ $(obj)examples/standalone/eepro100_eeprom \ $(obj)examples/standalone/hello_world \ $(obj)examples/standalone/interrupt \ -- 1.6.0.6

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[U-Boot] Please pull ppc4xx/master
by Stefan Roese 10 Sep '09

10 Sep '09

The following changes since commit 6c97a20d0b2f56cb4f3745d94b1f96986e8cced5: Kumar Gala (1): ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Detlev Zundel (1): amcc-common.h: Use filenames from environment variables for update procedure. Matthias Fuchs (3): ppc4xx: Fix PMC405DE support ppc4xx: Allow overwriting pci target registers for all 4xx boards ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boards Stefan Roese (1): ppc4xx: Fix compilation warning in 4xx miiphy.c board/esd/pmc405de/Makefile | 5 ++++- cpu/ppc4xx/4xx_pci.c | 4 ++-- cpu/ppc4xx/miiphy.c | 2 +- include/configs/CPCI405.h | 2 ++ include/configs/CPCI4052.h | 2 ++ include/configs/CPCI405AB.h | 2 ++ include/configs/CPCI405DT.h | 2 ++ include/configs/PMC405.h | 2 ++ include/configs/PMC405DE.h | 2 ++ include/configs/amcc-common.h | 8 +++++--- 10 files changed, 24 insertions(+), 7 deletions(-)

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[U-Boot] [PATCH] Rename CONFIG_SYS_MDDRC memory constants for all mpc512x boards
by Martha M Stan 10 Sep '09

10 Sep '09

From: Martha Marx <mmarx(a)silicontkx.com> Signed-off-by: Martha Marx Stan <mmarx(a)silicontkx.com> --- cpu/mpc512x/fixed_sdram.c | 104 ++++++++++++------------ include/configs/aria.h | 190 +++++++++++++++++++++--------------------- include/configs/mecp5123.h | 78 +++++++++--------- include/configs/mpc5121ads.h | 86 ++++++++++---------- 4 files changed, 229 insertions(+), 229 deletions(-) diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903..5be02f7 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -46,68 +46,68 @@ long int fixed_sdram(void) sync_law(&im->sysconf.ddrlaw.ar); /* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); /* Initialize DDR Priority Manager */ - out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); - out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); - out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); - out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); - out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); - out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); - out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); - out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); - out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); - out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); - out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); - out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); - out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); - out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); - out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); - out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); - out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); - out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); - out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); - out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); - out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); - out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); - out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); + out_be32(&im->mddrc.prioman_config1, MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, MDDRCGRP_LUT4_AL); /* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2); /* Initialize DDR */ for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, DDR_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_EM3); + out_be32(&im->mddrc.ddr_command, DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN); return msize; } diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113..cafef9e 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -123,108 +123,108 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ - (1 << 30) | /* CKE */ \ - (1 << 29) | /* CLK_ON */ \ - (1 << 28) | /* CMD_MODE */ \ - (4 << 25) | /* DRAM_ROW_SELECT */ \ - (3 << 21) | /* DRAM_BANK_SELECT */ \ - (0 << 18) | /* SELF_REF_EN */ \ - (0 << 17) | /* 16BIT_MODE */ \ - (2 << 13) | /* RDLY */ \ - (0 << 12) | /* HALF_DQS_DLY */ \ - (1 << 11) | /* QUART_DQS_DLY */ \ - (2 << 8) | /* WDLY */ \ - (0 << 7) | /* EARLY_ODT */ \ - (1 << 6) | /* ON_DIE_TERMINATE */ \ - (0 << 5) | /* FIFO_OV_CLEAR */ \ - (0 << 4) | /* FIFO_UV_CLEAR */ \ - (0 << 1) | /* FIFO_OV_EN */ \ - (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS (Output Drive Strength) */ \ - (0 << 0) /* DLL */ \ - ) +#define MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ + (1 << 30) | /* CKE */ \ + (1 << 29) | /* CLK_ON */ \ + (1 << 28) | /* CMD_MODE */ \ + (4 << 25) | /* DRAM_ROW_SELECT */ \ + (3 << 21) | /* DRAM_BANK_SELECT */ \ + (0 << 18) | /* SELF_REF_EN */ \ + (0 << 17) | /* 16BIT_MODE */ \ + (2 << 13) | /* RDLY */ \ + (0 << 12) | /* HALF_DQS_DLY */ \ + (1 << 11) | /* QUART_DQS_DLY */ \ + (2 << 8) | /* WDLY */ \ + (0 << 7) | /* EARLY_ODT */ \ + (1 << 6) | /* ON_DIE_TERMINATE */ \ + (0 << 5) | /* FIFO_OV_CLEAR */ \ + (0 << 4) | /* FIFO_UV_CLEAR */ \ + (0 << 1) | /* FIFO_OV_EN */ \ + (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define MDDRC_SYS_CFG_RUN (MDDRC_SYS_CFG & ~(1 << 28)) +#define MDDRC_TIME_CFG1 0x55D81189 +#define MDDRC_TIME_CFG2 0x34790863 + +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x030C3D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define DDR_MICRON_EMR2 0x01020000 +#define DDR_MICRON_EMR3 0x01030000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS (Output Drive Strength) */ \ + (0 << 0) /* DLL */ \ + ) /* * Backward compatible definitions, * so we do not have to change cpu/mpc512x/fixed_sdram.c */ -#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) +#define DDR_EM2 (DDR_MICRON_EMR2) +#define DDR_EM3 (DDR_MICRON_EMR3) +#define DDR_EN_DLL (DDR_MICRON_EMR) +#define DDR_OCD_DEFAULT (DDR_MICRON_EMR_OCD) /* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111 /* * NOR FLASH on the Local Bus diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae00..cb8198b 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -111,47 +111,47 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define MDDRC_SYS_CFG 0xFA804A00 +#define MDDRC_SYS_CFG_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1 0x68EC1168 +#define MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111 /* * NOR FLASH on the Local Bus diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174d..5df51e3 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -131,53 +131,53 @@ * [04:00] DRAM tRPA */ #ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 +#define MDDRC_SYS_CFG 0xF8604A00 +#define MDDRC_SYS_CFG_RUN 0xE8604A00 +#define MDDRC_TIME_CFG1 0x54EC1168 +#define MDDRC_TIME_CFG2 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG 0xFA804A00 +#define MDDRC_SYS_CFG_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1 0x68EC1168 +#define MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111 /* * NOR FLASH on the Local Bus -- 1.5.2.4

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