July 2009 - U-Boot

[U-Boot] [PATCH] mpc83xx: fix duplicate MONITOR_LEN definition caused by merge foo
by Kim Phillips 18 Jul '09

18 Jul '09

commits 4a9932a4364b548773bc131bf85e24a2ec15f2b0 and c9646ed758804fa1fa6c1425369a4eee5d618b1d merged and generated this build error: Configuring for MPC837XERDB board... In file included from /home/r1aaha/git/u-boot/include/config.h:3, from include/common.h:35: /home/r1aaha/git/u-boot/include/configs/MPC837XERDB.h:233:1: warning: "CONFIG_SYS_MONITOR_LEN" redefined /home/r1aaha/git/u-boot/include/configs/MPC837XERDB.h:232:1: warning: this is the location of the previous definition take the larger value of the two, to allow for -mmultiple-broken compilers, such as gcc 4.4. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- include/configs/MPC837XERDB.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 807a534..9132718 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -230,7 +230,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* -- 1.6.3.3

2 1

[U-Boot] [PATCH V2] ppc4xx: Add 405EP based PMC405DE board
by Matthias Fuchs 18 Jul '09

18 Jul '09

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/esd/pmc405de/Makefile | 51 ++++ board/esd/pmc405de/config.mk | 23 ++ board/esd/pmc405de/pmc405de.c | 590 +++++++++++++++++++++++++++++++++++++++++ board/esd/pmc405de/u-boot.lds | 133 +++++++++ include/configs/PMC405DE.h | 373 ++++++++++++++++++++++++++ 8 files changed, 1175 insertions(+), 0 deletions(-) create mode 100644 board/esd/pmc405de/Makefile create mode 100644 board/esd/pmc405de/config.mk create mode 100644 board/esd/pmc405de/pmc405de.c create mode 100644 board/esd/pmc405de/u-boot.lds create mode 100644 include/configs/PMC405DE.h diff --git a/MAINTAINERS b/MAINTAINERS index 575a7ec..484040c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -171,6 +171,7 @@ Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> PCI405 PPC405GP PLU405 PPC405EP PMC405 PPC405GP + PMC405DE PPC405EP PMC440 PPC440EPx VOH405 PPC405EP VOM405 PPC405EP diff --git a/MAKEALL b/MAKEALL index 020ff73..f36a5fd 100755 --- a/MAKEALL +++ b/MAKEALL @@ -237,6 +237,7 @@ LIST_4xx=" \ PIP405 \ PLU405 \ PMC405 \ + PMC405DE \ PMC440 \ PPChameleonEVB \ quad100hd \ diff --git a/Makefile b/Makefile index 090e645..a5d397b 100644 --- a/Makefile +++ b/Makefile @@ -1492,6 +1492,9 @@ PLU405_config: unconfig PMC405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd +PMC405DE_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405de esd + PMC440_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile new file mode 100644 index 0000000..cec88f1 --- /dev/null +++ b/board/esd/pmc405de/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +COBJS += ../common/cmd_loadpci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esd/pmc405de/config.mk b/board/esd/pmc405de/config.mk new file mode 100644 index 0000000..ae855dc --- /dev/null +++ b/board/esd/pmc405de/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c new file mode 100644 index 0000000..ca26d5c --- /dev/null +++ b/board/esd/pmc405de/pmc405de.c @@ -0,0 +1,590 @@ +/* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd.eu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/4xx_pci.h> +#include <command.h> +#include <malloc.h> + +#define CPLD_VERSION (CONFIG_SYS_CPLD_BASE + 0) +#define CPLD_VERSION_MASK 0x0f +#define CPLD_STATUS (CONFIG_SYS_CPLD_BASE + 4) +#define CPLD_CONTROL (CONFIG_SYS_CPLD_BASE + 8) +#define CPLD_CONTROL_POSTLED_N 0x01 +#define CPLD_CONTROL_POSTLED_GATE 0x02 +#define CPLD_CONTROL_RESETOUT_N 0x40 +#define CPLD_CONTROL_RESETOUT_N_GATE 0x80 + +DECLARE_GLOBAL_DATA_PTR; + +extern void __ft_board_setup(void *blob, bd_t *bd); +extern void pll_write(u32 a, u32 b); + +static int wait_for_pci_ready_done; + +static int is_monarch(void); +static int pci_is_66mhz(void); +static int board_revision(void); +static int cpld_revision(void); + +int board_early_init_f(void) +{ + u32 pllmr0, pllmr1; + + /* + * check M66EN and patch PLB:PCI divider for 66MHz PCI + * + * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1 + * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2 + * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2 + * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3 + * + * finally call pll_write() which will do a chip reset + * and never return. + */ + pllmr0 = mfdcr(CPC0_PLLMR0); + pllmr1 = mfdcr(CPC0_PLLMR1); + + if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) { + /* fCPU=333MHz, fPLB=111MHz */ + if (pci_is_66mhz()) { + if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != + PLLMR0_PCI_PLB_DIV_1) { + pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | + PLLMR0_PCI_PLB_DIV_1, pllmr1); + } + } else { + if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != + PLLMR0_PCI_PLB_DIV_2) { + pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | + PLLMR0_PCI_PLB_DIV_2, pllmr1); + } + } + } else { + /* fCPU=133|266MHz, fPLB=133MHz */ + if (pci_is_66mhz()) { + if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != + PLLMR0_PCI_PLB_DIV_2) { + pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | + PLLMR0_PCI_PLB_DIV_2, pllmr1); + } + } else { + if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != + PLLMR0_PCI_PLB_DIV_3) { + pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | + PLLMR0_PCI_PLB_DIV_3, pllmr1); + } + } + } + + /* + * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive + * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive + * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive + * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive + * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive + */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: + * - set ready timeout to 512 ebc-clks -> ca. 15 us + * - EBC lines are always driven + */ + mtebc(epcr, 0xa8400000); + + return 0; +} + +int misc_init_r(void) +{ + int i; + + if (!is_monarch()) { + /* PCI configuration done: release EREADY */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO_EREADY); + out_be32((void*)GPIO0_TCR, + in_be32((void*)GPIO0_TCR) | CONFIG_SYS_GPIO_EREADY); + } + + /* turn off POST LED */ + out_8((void*)CPLD_CONTROL, + CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE); + + /* turn on LEDs: RUN, A, B */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & + ~(CONFIG_SYS_GPIO_LEDRUN_N | + CONFIG_SYS_GPIO_LEDA_N | + CONFIG_SYS_GPIO_LEDB_N)); + + for (i=0; i < 200; i++) + udelay(1000); + + /* turn off LEDs: A, B */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | + (CONFIG_SYS_GPIO_LEDA_N | + CONFIG_SYS_GPIO_LEDB_N)); + + return (0); +} + +static int is_monarch(void) +{ + if (in_be32((void*)GPIO0_IR) & CONFIG_SYS_GPIO_MONARCH_N) + return 0; + return 1; +} + +static int pci_is_66mhz(void) +{ + if (in_be32((void*)GPIO0_IR) & CONFIG_SYS_GPIO_M66EN) + return 1; + return 0; +} + +static int board_revision(void) +{ + return ((in_be32((void*)GPIO0_IR) & CONFIG_SYS_GPIO_HWREV_MASK) >> + CONFIG_SYS_GPIO_HWREV_SHIFT); +} + +static int cpld_revision(void) +{ + return ((in_8((void*)CPLD_VERSION) & CPLD_VERSION_MASK)); +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + puts("Board: esd GmbH - PMC-CPU/405-DE"); + + gd->board_type = board_revision(); + printf(", Rev 1.%ld, ", gd->board_type); + + if (!is_monarch()) + puts("non-"); + + printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n", + pci_is_66mhz() ? "66" : "33", cpld_revision()); + + return 0; +} + + +static void wait_for_pci_ready(void) +{ + int i; + char *s = getenv("pcidelay"); + + /* only wait once */ + if (wait_for_pci_ready_done) + return; + + /* + * We have our own handling of the pcidelay variable. + * Using CONFIG_PCI_BOOTDELAY enables pausing for host + * and adapter devices. For adapter devices we do not + * want this. + */ + if (s) { + int ms = simple_strtoul(s, NULL, 10); + printf("PCI: Waiting for %d ms\n", ms); + for (i=0; i<ms; i++) + udelay(1000); + } + + if (!(in_be32((void*)GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)) { + printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); + while (1) { + if (ctrlc()) { + puts("abort\n"); + break; + } + if (in_be32((void*)GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) { + printf("done\n"); + break; + } + } + } + + wait_for_pci_ready_done = 1; +} + +/* + * Overwrite weak is_pci_host() + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + */ +int is_pci_host(struct pci_controller *hose) +{ + char *s; + + if (!is_monarch()) { + /* + * Overwrite PCI identification when running in + * non-monarch mode + * This should be moved into pci_target_init() + * when it is sometimes available for 405 CPUs + */ + pci_write_config_word(PCIDEVID_405GP, + PCI_SUBSYSTEM_ID, + CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); + pci_write_config_word(PCIDEVID_405GP, + PCI_CLASS_SUB_CODE, + CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); + } + + s = getenv("pciscan"); + if (s == NULL) { + if (is_monarch()) { + wait_for_pci_ready(); + return 1; + } else { + return 0; + } + } else { + if (!strcmp(s, "yes")) + return 1; + } + + return 0; +} + +/* + * Overwrite weak pci_pre_init() + * + * The default implementation enables the 405EP + * internal PCI arbiter. We do not want that + * on a PMC module. + */ +int pci_pre_init(struct pci_controller *hose) +{ + return 1; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in non-monarch mode. + */ + if (!is_monarch()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, " + "err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_SYS_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable(unsigned dev_addr, int state) +{ + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO0. */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & + ~CONFIG_SYS_GPIO_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO0. */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | + CONFIG_SYS_GPIO_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void*)GPIO0_OR) & + CONFIG_SYS_GPIO_EEPROM_WP)); + break; + } + } + return state; +} + +int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); + if (state < 0) { + puts("Query of write access state failed.\n"); + } else { + printf("Write access for device 0x%0x is %sabled.\n", + CONFIG_SYS_I2C_EEPROM_ADDR, + state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable( + CONFIG_SYS_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable( + CONFIG_SYS_I2C_EEPROM_ADDR, 1); + } + if (state < 0) + puts ("Setup of write access state failed.\n"); + } + + return state; +} + +U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, + "Enable / disable / query EEPROM write access", + "" +); +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ + +int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + u8 data[0x20]; + int ret; + + if (argc < 2) { + printf("Usage:\nsbe %s\n", cmdtp->help); + return -1; + } + + memset(data, 0, sizeof(data)); + + if (argc > 1) { + if (!strcmp(argv[1], "133")) { + /* + * CPU: 133MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ + printf("Bootstrapping for 133MHz\n"); + data[0x00] = 0x19; + data[0x19] = 0x40; + data[0x1a] = 0x12; + data[0x1b] = 0x12; + data[0x1c] = 0x42; + data[0x1d] = 0x3e; + } else if (!strcmp(argv[1], "266")) { + /* + * CPU: 266MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ + printf("Bootstrapping for 266MHz\n"); + data[0x00] = 0x19; + data[0x19] = 0x50; + data[0x1a] = 0x22; + data[0x1b] = 0x2d; + data[0x1c] = 0x42; + data[0x1d] = 0x3e; + } else if (!strcmp(argv[1], "333")) { + /* + * CPU: 333MHz + * PLB/SDRAM/MAL: 111MHz + * OPB: 55MHz + * EBC: 55MHz + * PCI: 55MHz (111MHz on M66EN=1) + */ + printf("Bootstrapping for 333MHz\n"); + data[0x00] = 0x19; + data[0x19] = 0x60; + data[0x1a] = 0x29; + data[0x1b] = 0x2d; + data[0x1c] = 0x42; + data[0x1d] = 0xbe; + } else { + printf("Usage:\nsbe %s\n", cmdtp->help); + return -1; + } + } + + printf("Writing boot EEPROM ...\n"); + ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0, data, 0x20); + ret |= eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0x40, data, 0x20); + if (ret) + printf("bootstrap_eeprom_write failed\n"); + else + printf("done (dump via 'i2c md 50 0.1 20')\n"); + + return 0; +} +U_BOOT_CMD( + sbe, 2, 0, do_setup_bootstrap_eeprom, + "setup bootstrap eeprom", + "<cpufreq:133|266|333>" +); + +#if defined(CONFIG_PRAM) +#include <environment.h> +extern env_t *env_ptr; + +int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 pram, nextbase, base; + char *v; + u32 param; + ulong *lptr; + + v = getenv("pram"); + if (v) + pram = simple_strtoul(v, NULL, 10); + else { + printf("Error: pram undefined. Please define pram in KiB\n"); + return 1; + } + + base = gd->bd->bi_memsize; +#if defined(CONFIG_LOGBUFFER) + base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; +#endif + /* + * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE + */ + param = base - (pram << 10); + printf("PARAM: @%08x\n", param); + debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base); + + /* clear entire PA ram */ + memset((void*)param, 0, (pram << 10)); + + /* reserve 4k for pointer field */ + nextbase = base - 4096; + lptr = (ulong*)(base); + + /* + * *(--lptr) = item_size; + * *(--lptr) = base - item_base = distance from field top; + */ + + /* env is first (4k aligned) */ + nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); + memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ + *(--lptr) = base - nextbase; /* offset | type=0 */ + + /* free section */ + *(--lptr) = nextbase - param; /* size */ + *(--lptr) = (base - param) | 126; /* offset | type=126 */ + + /* terminate pointer field */ + *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); + *(--lptr) = 0; /* offset=0 -> terminator */ + return 0; +} +U_BOOT_CMD( + painit, 1, 1, do_painit, + "prepare PciAccess system", + "" +); +#endif /* CONFIG_PRAM */ + +int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + out_be32((void*)GPIO0_TCR, + in_be32((void*)GPIO0_TCR) | CONFIG_SYS_GPIO_SELFRST_N); + return 0; +} +U_BOOT_CMD( + selfreset, 1, 1, do_selfreset, + "assert self-reset# signal", + "" +); + +int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc > 1) { + if (argv[1][0] == '0') { + /* assert */ + printf("PMC-RESETOUT# asserted\n"); + out_8((void*)CPLD_CONTROL, + CPLD_CONTROL_RESETOUT_N_GATE); + } else { + /* deassert */ + printf("PMC-RESETOUT# deasserted\n"); + out_8((void*)CPLD_CONTROL, + CPLD_CONTROL_RESETOUT_N | + CPLD_CONTROL_RESETOUT_N_GATE); + } + } else { + printf("PMC-RESETOUT# is %s\n", + (in_8((void*)CPLD_CONTROL) & CPLD_CONTROL_RESETOUT_N) ? + "inactive" : "active"); + } + return 0; +} +U_BOOT_CMD( + resetout, 2, 1, do_resetout, + "assert PMC-RESETOUT# signal", + "" +); diff --git a/board/esd/pmc405de/u-boot.lds b/board/esd/pmc405de/u-boot.lds new file mode 100644 index 0000000..8c01016 --- /dev/null +++ b/board/esd/pmc405de/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h new file mode 100644 index 0000000..e5ef863 --- /dev/null +++ b/include/configs/PMC405DE.h @@ -0,0 +1,373 @@ +/* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs(a)esd.eu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* This is a PPC405 CPU */ +#define CONFIG_4xx 1 /* ...member of PPC4xx family */ +#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 + +#define CONFIG_PPC4xx_EMAC +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */ + +#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_PRAM 0 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ + +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ + +#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ + +#undef CONFIG_SYS_EXT_SERIAL_CLOCK +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +/* + * PCI stuff + */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +/* + * PCI identification + */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH +#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */ +#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */ +#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC +#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST + +#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH + +#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */ +#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ +#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +/* + * FLASH organization + */ +#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */ +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xfe000000 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) + +/* + * Environment in EEPROM setup + */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x100 +#define CONFIG_ENV_SIZE 0x700 + +/* + * I2C EEPROM (24W16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_WREN 1 + +/* + * RTC + */ +#define CONFIG_RTC_RX8025 + +/* + * External Bus Controller (EBC) Setup + * (max. 55MHZ EBC clock) + */ +/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000) + +/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_CPLD_BASE 0xef000000 +#define CONFIG_SYS_EBC_PB1AP 0x00800000 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) + +/* + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CONFIG_SYS_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +/* inside SDRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR +/* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * GPIO Configuration + */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ +} \ +} + +#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */ +#define CONFIG_SYS_GPIO_HWREV_SHIFT 27 +#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */ +#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */ +#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */ +#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */ +#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */ +#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */ +#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */ +#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */ + +/* + * Default speed selection (cpu_plb_opb_ebc) in mhz. + * This value will be set if iic boot eprom is disabled. + */ +#undef CONFIG_SYS_FCPU333MHZ +#define CONFIG_SYS_FCPU266MHZ +#undef CONFIG_SYS_FCPU133MHZ + +#if defined(CONFIG_SYS_FCPU333MHZ) +/* + * CPU: 333MHz + * PLB/SDRAM/MAL: 111MHz + * OPB: 55MHz + * EBC: 55MHz + * PCI: 55MHz (111MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#endif + +#if defined(CONFIG_SYS_FCPU266MHZ) +/* + * CPU: 266MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#endif + +#if defined(CONFIG_SYS_FCPU133MHZ) +/* + * CPU: 133MHz + * PLB/SDRAM/MAL: 133MHz + * OPB: 66MHz + * EBC: 44MHz + * PCI: 44MHz (66MHz on M66EN=1) + */ +#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#endif + +#endif /* __CONFIG_H */ -- 1.6.1

2 5

[U-Boot] [PATCH 2/2 v3] Remove legacy NAND and disk on chip references from boards.
by Scott Wood 18 Jul '09

18 Jul '09

Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- Grr, did "git commit --amend" rather than "git commit --amend -a" on v2, so it didn't pick up the changes. :-P board/atc/atc.c | 7 --- board/bmw/bmw.c | 8 --- board/cpu86/cpu86.c | 7 --- board/cpu87/cpu87.c | 7 --- board/delta/nand.c | 4 -- board/esd/common/auto_update.c | 50 ------------------ board/g2000/g2000.c | 15 ------ board/gen860t/gen860t.c | 12 ----- board/mcc200/mcc200.c | 7 --- board/mpl/common/common_util.c | 9 --- board/netphone/netphone.c | 16 ------ board/netta/netta.c | 15 ------ board/netta2/netta2.c | 16 ------ board/netvia/netvia.c | 15 ------ board/omap2420h4/omap2420h4.c | 23 --------- board/pcippc2/pcippc2.c | 5 -- board/pm520/pm520.c | 7 --- board/pm826/pm826.c | 7 --- board/pm828/pm828.c | 7 --- board/rbc823/rbc823.c | 12 ----- board/samsung/smdk6400/smdk6400.c | 11 ---- board/sixnet/sixnet.c | 5 -- board/stxxtc/stxxtc.c | 16 ------ board/svm_sc8xx/svm_sc8xx.c | 7 --- board/zylonite/nand.c | 4 -- include/common.h | 3 - include/configs/BMW.h | 4 -- include/configs/CATcenter.h | 8 --- include/configs/CPU86.h | 10 ---- include/configs/CPU87.h | 4 -- include/configs/G2000.h | 20 ------- include/configs/GEN860T.h | 17 ------ include/configs/MIP405.h | 10 ---- include/configs/NETPHONE.h | 87 -------------------------------- include/configs/NETTA.h | 100 ------------------------------------- include/configs/NETTA2.h | 87 -------------------------------- include/configs/NETVIA.h | 79 ----------------------------- include/configs/PCIPPC2.h | 12 ----- include/configs/PCIPPC6.h | 12 ----- include/configs/PIP405.h | 4 -- include/configs/PM520.h | 19 ------- include/configs/PM826.h | 14 ----- include/configs/PM828.h | 13 ----- include/configs/PPChameleonEVB.h | 26 ---------- include/configs/RBC823.h | 9 --- include/configs/SXNI855T.h | 67 ------------------------- include/configs/TQM85xx.h | 2 - include/configs/VCMA9.h | 38 -------------- include/configs/at91rm9200dk.h | 30 ----------- include/configs/csb637.h | 32 ------------ include/configs/delta.h | 9 --- include/configs/m501sk.h | 5 -- include/configs/omap2420h4.h | 36 ------------- include/configs/sbc2410x.h | 23 --------- include/configs/stxxtc.h | 82 ------------------------------ include/configs/svm_sc8xx.h | 4 -- include/configs/zylonite.h | 8 --- 57 files changed, 0 insertions(+), 1166 deletions(-) diff --git a/board/atc/atc.c b/board/atc/atc.c index 936c031..fe8efe2 100644 --- a/board/atc/atc.c +++ b/board/atc/atc.c @@ -379,13 +379,6 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c index 870011e..fe4b027 100644 --- a/board/bmw/bmw.c +++ b/board/bmw/bmw.c @@ -117,14 +117,6 @@ sys_led_msg(char* msg) LED_REG(3) = msg[0]; } -/* - * Map onboard TSOP-16MB DOC FLASH chip. - */ -void doc_init (void) -{ - doc_probe(DOC_BASE_ADDR); -} - #define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR) /* Read from NVRAM */ diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c index bc7ebfe..943f981 100644 --- a/board/cpu86/cpu86.c +++ b/board/cpu86/cpu86.c @@ -311,10 +311,3 @@ phys_size_t initdram (int board_type) return (psize); } - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index 057a34c..693524b 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -322,13 +322,6 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/delta/nand.c b/board/delta/nand.c index aff7c54..e87d502 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -23,7 +23,6 @@ #include <common.h> #if defined(CONFIG_CMD_NAND) -#if !defined(CONFIG_NAND_LEGACY) #include <nand.h> #include <asm/arch/pxa-regs.h> @@ -550,7 +549,4 @@ int board_nand_init(struct nand_chip *nand) return 0; } -#else - #error "U-Boot legacy NAND support not available for Monahans DFC." -#endif #endif diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 33aeb46..c4a49e2 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -27,9 +27,6 @@ #include <command.h> #include <image.h> #include <asm/byteorder.h> -#if defined(CONFIG_NAND_LEGACY) -#include <linux/mtd/nand_legacy.h> -#endif #include <fat.h> #include <part.h> @@ -58,20 +55,6 @@ extern int flash_sect_erase(ulong, ulong); extern int flash_sect_protect (int, ulong, ulong); extern int flash_write (char *, ulong, ulong); -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) -/* references to names in cmd_nand.c */ -#define NANDRW_READ 0x01 -#define NANDRW_WRITE 0x00 -#define NANDRW_JFFS2 0x02 -#define NANDRW_JFFS2_SKIP 0x04 -extern struct nand_chip nand_dev_desc[]; -extern int nand_legacy_rw(struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf); -extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, - size_t len, int clean); -#endif - extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; int au_check_cksum_valid(int i, long nbytes) @@ -158,9 +141,6 @@ int au_do_update(int i, long sz) int off, rc; uint nbytes; int k; -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) - int total; -#endif hdr = (image_header_t *)LOAD_ADDR; #if defined(CONFIG_FIT) @@ -240,15 +220,6 @@ int au_do_update(int i, long sz) au_image[i].name); debug ("flash_sect_erase(%lx, %lx);\n", start, end); flash_sect_erase (start, end); - } else { -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) - printf ("Updating NAND FLASH with image %s\n", - au_image[i].name); - debug ("nand_legacy_erase(%lx, %lx);\n", start, end); - rc = nand_legacy_erase (nand_dev_desc, start, - end - start + 1, 0); - debug ("nand_legacy_erase returned %x\n", rc); -#endif } udelay(10000); @@ -273,18 +244,7 @@ int au_do_update(int i, long sz) rc = flash_write ((char *)addr, start, (nbytes + 1) & ~1); } else { -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) - debug ("nand_legacy_rw(%p, %lx, %x)\n", - addr, start, nbytes); - rc = nand_legacy_rw (nand_dev_desc, - NANDRW_WRITE | NANDRW_JFFS2, - start, nbytes, (size_t *)&total, - (uchar *)addr); - debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", - rc, total, nbytes); -#else rc = -1; -#endif } if (rc != 0) { printf ("Flashing failed due to error %d\n", rc); @@ -297,16 +257,6 @@ int au_do_update(int i, long sz) if (au_image[i].type != AU_NAND) { rc = crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)); - } else { -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) - rc = nand_legacy_rw (nand_dev_desc, - NANDRW_READ | NANDRW_JFFS2 | - NANDRW_JFFS2_SKIP, - start, nbytes, (size_t *)&total, - (uchar *)addr); - rc = crc32 (0, (uchar *)(addr + off), - image_get_data_size (hdr)); -#endif } if (rc != image_get_dcrc (hdr)) { printf ("Image %s Bad Data Checksum After COPY\n", diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 218f1be..f6f4719 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -148,21 +148,6 @@ phys_size_t initdram (int board_type) return ret; } - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - nand_probe(CONFIG_SYS_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } -} -#endif - - #if 0 /* test-only !!! */ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 008f765..126dccd 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -219,18 +219,6 @@ phys_size_t initdram (int board_type) } /* - * Disk On Chip (DOC) Millenium initialization. - * The DOC lives in the CS2* space - */ -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - printf ("Probing at 0x%.8x: ", DOC_BASE); - doc_probe (DOC_BASE); -} -#endif - -/* * Miscellaneous intialization */ int misc_init_r (void) diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 9fa1d3a..40f8c81 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -321,10 +321,3 @@ void ide_set_reset (int idereset) } #endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 243e3eb..aa409d4 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -563,15 +563,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe(MULTI_PURPOSE_SOCKET_ADDR); -} -#endif - - #ifdef CONFIG_VIDEO /****************************************************** * Routines to display the Board information diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index 53d3172..ce5f051 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -597,22 +597,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) - -#include <linux/mtd/nand_legacy.h> - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CONFIG_SYS_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - #ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) diff --git a/board/netta/netta.c b/board/netta/netta.c index 02fd94c..38c9d89 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -555,21 +555,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY) - -#include <linux/mtd/nand_legacy.h> - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif - #if defined(CONFIG_CMD_PCMCIA) int pcmcia_init(void) diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index 2ce33cf..3b0191d 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -595,22 +595,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) - -#include <linux/mtd/nand_legacy.h> - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CONFIG_SYS_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - #ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index 0b032c4..5606996 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -415,18 +415,3 @@ int board_early_init_f(void) return 0; } - -#if defined(CONFIG_CMD_NAND) - -#include <linux/mtd/nand_legacy.h> - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE); - - printf ("%4lu MB\n", totlen >> 20); -} -#endif diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 0fe9380..8d18239 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -31,10 +31,6 @@ #include <asm/arch/mem.h> #include <i2c.h> #include <asm/mach-types.h> -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; -#endif DECLARE_GLOBAL_DATA_PTR; @@ -846,22 +842,3 @@ void update_mux(u32 btype,u32 mtype) } } } - -#if defined(CONFIG_CMD_NAND) -void nand_init(void) -{ - extern flash_info_t flash_info[]; - - nand_probe(CONFIG_SYS_NAND_ADDR); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { - print_size(nand_dev_desc[0].totlen, "\n"); - } - -#ifdef CONFIG_SYS_JFFS2_MEM_NAND - flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; - flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ - flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ - flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ -#endif -} -#endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index 7985f7d..e7af89b 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -147,11 +147,6 @@ void pci_init_board (void) cpc710_pci_enable_timeout (); } -void doc_init (void) -{ - doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); -} - void pcippc2_cpci3264_init (void) { pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 9da1041..15614fd 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -315,13 +315,6 @@ void ide_set_reset (int idereset) } #endif -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - int board_eth_init(bd_t *bis) { cpu_eth_init(bis); /* Built in FEC comes first */ diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c index 19e7a00..305aff9 100644 --- a/board/pm826/pm826.c +++ b/board/pm826/pm826.c @@ -311,13 +311,6 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c index 4a3b2fd..6e1878c 100644 --- a/board/pm828/pm828.c +++ b/board/pm828/pm828.c @@ -344,13 +344,6 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif - #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index b294906..5cfa970 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -255,15 +255,3 @@ static long int dram_size (long int mamr_value, long int *base, return (get_ram_size (base, maxsize)); } - -void doc_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig (UPMB, (uint *) static_table, - sizeof (static_table) / sizeof (uint)); - memctl->memc_mbmr = MAMR_DSA_1_CYCL; - - doc_probe (FLASH_BASE1_PRELIM); -} diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index bd2e45a..52cd174 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -107,17 +107,6 @@ ulong virt_to_phy_smdk6400(ulong addr) } #endif -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY) -#include <linux/mtd/nand.h> -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; -void nand_init(void) -{ - nand_probe(CONFIG_SYS_NAND_BASE); - if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) - print_size(nand_dev_desc[0].totlen, "\n"); -} -#endif - ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) { if (banknum == 0) { /* non-CFI boot flash */ diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 6e39b01..edb5d13 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -33,11 +33,6 @@ # include <status_led.h> #endif -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; -#endif - DECLARE_GLOBAL_DATA_PTR; #define ORMASK(size) ((-size) & OR_AM_MSK) diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index a1a36c4..717dbe2 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -574,22 +574,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) - -#include <linux/mtd/nand_legacy.h> - -extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; - -void nand_init(void) -{ - unsigned long totlen; - - totlen = nand_probe(CONFIG_SYS_NAND_BASE); - printf ("%4lu MB\n", totlen >> 20); -} -#endif - #ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index 4390e49..c243035 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -152,10 +152,3 @@ phys_size_t initdram (int board_type) udelay(200); return (size_b0 ); } - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index 899445e..bec54cb 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -23,7 +23,6 @@ #include <common.h> #if defined(CONFIG_CMD_NAND) -#ifdef CONFIG_NEW_NAND_CODE #include <nand.h> #include <asm/arch/pxa-regs.h> @@ -554,7 +553,4 @@ int board_nand_init(struct nand_chip *nand) return 0; } -#else - #error "U-Boot legacy NAND support not available for Monahans DFC." -#endif #endif diff --git a/include/common.h b/include/common.h index a6c7c07..bcdcd72 100644 --- a/include/common.h +++ b/include/common.h @@ -238,9 +238,6 @@ int source (ulong addr, const char *fit_uname); extern ulong load_addr; /* Default Load Address */ -/* common/cmd_doc.c */ -void doc_probe(unsigned long physadr); - /* common/cmd_nvedit.c */ int env_init (void); void env_relocate (void); diff --git a/include/configs/BMW.h b/include/configs/BMW.h index 24ffb00..98f6396 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -81,13 +81,9 @@ #include <config_cmd_default.h> #define CONFIG_CMD_DATE -#define CONFIG_CMD_DOC #define CONFIG_CMD_ELF -/* CONFIG_CMD_DOC required legacy NAND support */ -#define CONFIG_NAND_LEGACY - #if 0 #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 39f41e6..229a513 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -209,16 +209,8 @@ /* For CATcenter there is only NAND on the module */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 #define NAND_NO_RB -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index cf21fd9..6d76d9f 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -146,15 +146,6 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ /*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- * Miscellaneous configuration options */ @@ -179,7 +170,6 @@ #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_NFS diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 489378a..83b010c 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -182,7 +182,6 @@ #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DATE -#define CONFIG_CMD_DOC #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C @@ -190,9 +189,6 @@ #define CONFIG_CMD_PCI #endif - -#define CONFIG_NAND_LEGACY - /* * Miscellaneous configurable options */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index bf9fd82..6819c3e 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -196,32 +196,12 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CONFIG_SYS_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) #endif /*----------------------------------------------------------------------- diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 8f18ab2..12f879a 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -244,10 +244,6 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_BEDBUG -#if !defined(CONFIG_SC) - #define CONFIG_CMD_DOC -#endif - #ifdef CONFIG_POST #define CONFIG_CMD_DIAG #endif @@ -279,9 +275,6 @@ #define CONFIG_FPGA_VIRTEX2 #define CONFIG_SYS_FPGA_PROG_FEEDBACK - -#define CONFIG_NAND_LEGACY - /* * Verbose help from command monitor. */ @@ -738,16 +731,6 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /* - * Disk On Chip (millenium) configuration - */ -#if !defined(CONFIG_SC) -#define CONFIG_SYS_MAX_DOC_DEVICE 1 -#undef CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM -#undef CONFIG_SYS_DOC_PASSIVE_PROBE -#endif - -/* * FEC interrupt assignment */ #define FEC_INTERRUPT SIU_LEVEL1 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index da9b1cf..7ac9342 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -84,12 +84,9 @@ #if !defined(CONFIG_MIP405T) #define CONFIG_CMD_USB - #define CONFIG_CMD_DOC #endif -#define CONFIG_NAND_LEGACY - #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /************************************************************** @@ -384,13 +381,6 @@ #define CONFIG_ISO_PARTITION /* Experimental */ /************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM -/************************************************************ * Keyboard support ************************************************************/ #undef CONFIG_ISA_KEYBOARD diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 796938a..76ca916 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -120,7 +120,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_NAND #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -497,95 +496,9 @@ #define DSP_BASE 0xF1000000 #define NAND_BASE 0xF1010000 -/****************************************************************/ - -/* NAND */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ - } while(0) - -#if CONFIG_NETPHONE_VERSION == 1 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#elif CONFIG_NETPHONE_VERSION == 2 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - /*****************************************************************************/ #define CONFIG_SYS_DIRECT_FLASH_TFTP -#define CONFIG_SYS_DIRECT_NAND_TFTP /*****************************************************************************/ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 724e807..4f9f9fe 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -134,7 +134,6 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII -#define CONFIG_CMD_NAND #define CONFIG_CMD_NFS #define CONFIG_CMD_PCMCIA #define CONFIG_CMD_PING @@ -616,105 +615,6 @@ #define ER_BASE 0xF1020000 #define DUMMY_BASE 0xF1FF0000 -/****************************************************************/ - -/* NAND */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* #define NAND_NO_RB */ - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \ - } while(0) - -#ifndef NAND_NO_RB -#define NAND_WAIT_READY(nand) \ - do { \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \ - WATCHDOG_RESET(); \ - } \ - } while (0) -#else -#define NAND_WAIT_READY(nand) udelay(12) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00100000 -#define CONFIG_JFFS2_PART_OFFSET 0x00200000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nand0=netta-nand" -#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)" -*/ - /*****************************************************************************/ #define CONFIG_SYS_DIRECT_FLASH_TFTP diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index a14b2dd..d060cb7 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -121,7 +121,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_NAND #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_MII @@ -498,95 +497,9 @@ #define DSP_BASE 0xF1000000 #define NAND_BASE 0xF1010000 -/****************************************************************/ - -/* NAND */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \ - } while(0) - -#if CONFIG_NETTA2_VERSION == 1 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#elif CONFIG_NETTA2_VERSION == 2 -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - /*****************************************************************************/ #define CONFIG_SYS_DIRECT_FLASH_TFTP -#define CONFIG_SYS_DIRECT_NAND_TFTP /*****************************************************************************/ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index f97bdcb..7149b92 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -106,11 +106,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_CMD_NAND -#endif - - #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R @@ -393,80 +388,6 @@ #endif -/*****************************************************************************/ - -#define CONFIG_NAND_LEGACY - -#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 - -/* NAND */ -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0040; \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0100; \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= 0x0080; \ - } while(0) - -#define NAND_WAIT_READY(nand) \ - do { \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \ - ; \ - } while (0) - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - -#endif /*****************************************************************************/ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 5951d00..99a8c4a 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -75,7 +75,6 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_ELF #define CONFIG_CMD_NFS #define CONFIG_CMD_PCI @@ -84,8 +83,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#define CONFIG_NAND_LEGACY - /* * Miscellaneous configurable options */ @@ -251,15 +248,6 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- RTC m48t59 */ #define CONFIG_RTC_MK48T59 diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index a683a8f..66e6d24 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -75,7 +75,6 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_ELF #define CONFIG_CMD_NFS #define CONFIG_CMD_PCI @@ -86,8 +85,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#define CONFIG_NAND_LEGACY - /* * Miscellaneous configurable options */ @@ -253,15 +250,6 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ /*----------------------------------------------------------------------- - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#undef CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - -/*----------------------------------------------------------------------- RTC m48t59 */ #define CONFIG_RTC_MK48T59 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index e301599..962b29e 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -71,14 +71,10 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_MII #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_DOC #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES #define CONFIG_CMD_BSP - -#define CONFIG_NAND_LEGACY - #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /************************************************************** diff --git a/include/configs/PM520.h b/include/configs/PM520.h index ff73ef9..f9687d2 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -86,12 +86,6 @@ #define CONFIG_USB_STORAGE #endif -#if !defined(CONFIG_BOOT_ROM) -/* DoC requires legacy NAND for now */ -#define CONFIG_NAND_LEGACY -#endif - - /* * BOOTP options */ @@ -117,10 +111,6 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB -#if !defined(CONFIG_BOOT_ROM) -#define CONFIG_CMD_DOC -#endif - #if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI #endif @@ -186,15 +176,6 @@ #define CONFIG_RTC_PCF8563 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 -/* - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM #define CONFIG_SYS_DOC_BASE 0xE0000000 #define CONFIG_SYS_DOC_SIZE 0x00100000 diff --git a/include/configs/PM826.h b/include/configs/PM826.h index b58f529..636bd26 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -169,7 +169,6 @@ #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_NFS @@ -179,19 +178,6 @@ #define CONFIG_CMD_PCI #endif - -#define CONFIG_NAND_LEGACY - -/* - * Disk-On-Chip configuration - */ - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - /* * Miscellaneous configurable options */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 96c86f7..9d620af 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -169,7 +169,6 @@ #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_NFS @@ -179,18 +178,6 @@ #define CONFIG_CMD_PCI #endif - -/* - * Disk-On-Chip configuration - */ -#define CONFIG_NAND_LEGACY - -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ - -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - /* * Miscellaneous configurable options */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 16baf8c..9e54bf8 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -309,32 +309,6 @@ } \ } while(0) -#if 0 -#define SECTORSIZE 512 -#define NAND_NO_RB - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#ifdef NAND_NO_RB -/* constant delay (see also tR in the datasheet) */ -#define NAND_WAIT_READY(nand) do { \ - udelay(12); \ -} while (0) -#else -/* use the R/B pin */ -/* TBD */ -#endif - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -#endif /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index f36244d..00ac6cf 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -114,7 +114,6 @@ #define CONFIG_CMD_CDP #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG -#define CONFIG_CMD_DOC #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT @@ -329,14 +328,6 @@ #endif -/************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CONFIG_SYS_DOC_SHORT_TIMEOUT -#define CONFIG_SYS_DOC_SUPPORT_2000 -#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM - /*----------------------------------------------------------------------- * *----------------------------------------------------------------------- diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index cac04b4..8ee8cbf 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -163,75 +163,8 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NAND #define CONFIG_CMD_DATE - -#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS - -/* - * JFFS2 partitions - * - */ -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS - -/* -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x00780000 -#define CONFIG_JFFS2_PART_OFFSET 0x00080000 -*/ - -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00200000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand" -#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)" -*/ - -/* NAND flash support */ -#define CONFIG_NAND_LEGACY -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -/* DFBUSY is available on Port C, bit 12; 0 if busy */ -#define NAND_WAIT_READY(nand) \ - while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008)); -#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr)) -#define WRITE_NAND(d, adr) \ - do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0) -#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) -#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */ -#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */ -#define CE_LO 0x04 /* 1 selects chip (CE low) */ -#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0) -#define NAND_DISABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO) -#define NAND_ENABLE_CE(nand) \ - nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_CLRALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETALE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | CLE_LO) -#define NAND_CTL_CLRCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO) -#define NAND_CTL_SETCLE(nandptr) \ - nand_setcr((nandptr) + 1, CE_LO | ALE_LO) - /* * Miscellaneous configurable options */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6f13c63..d44fb07 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -351,8 +351,6 @@ /* NAND FLASH */ #ifdef CONFIG_NAND -#undef CONFIG_NAND_LEGACY - #define CONFIG_NAND_FSL_UPM 1 #define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 7edea6a..6051480 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -246,42 +246,4 @@ #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 -/*----------------------------------------------------------------------- - * NAND flash settings - */ -#if defined(CONFIG_CMD_NAND) - -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define NAND_WAIT_READY(nand) NF_WaitRB() - -#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) -#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) - - -#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) -#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) -#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) -#define WRITE_NAND(d, adr) NF_Write(d) -#define READ_NAND(adr) NF_Read() -/* the following functions are NOP's because S3C24X0 handles this in hardware */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 -#define CONFIG_MTD_NAND_ECC_JFFS2 1 - -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 56128c1..2017b66 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -117,38 +117,8 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -#define CONFIG_CMD_NAND - -#define CONFIG_NAND_LEGACY - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ #include <asm/arch/AT91RM9200.h> /* needed for port definitions */ -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/csb637.h b/include/configs/csb637.h index e1cdc7f..7a57696 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -121,38 +121,6 @@ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_PING -#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#include <asm/arch/AT91RM9200.h> /* needed for port definitions */ -#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) -#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) - -#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - -#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/delta.h b/include/configs/delta.h index e7186e8..9c46c5b 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -220,8 +220,6 @@ /* * NAND Flash */ -#undef CONFIG_NAND_LEGACY - #define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ #undef CONFIG_SYS_NAND1_BASE @@ -255,13 +253,6 @@ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 1 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - #define CONFIG_SYS_NO_FLASH 1 #define CONFIG_ENV_IS_IN_NAND 1 diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index 1e7d90e..32a8194 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -162,11 +162,6 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 ">>" #define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 1803b13..9c18842 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -147,42 +147,6 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_BOOTPATH - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) -#define NAND_WAIT_READY(nand) udelay(10) - -#define NAND_NO_RB 1 - -#define CONFIG_SYS_NAND_WP -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) - #define CONFIG_BOOTDELAY 3 #ifdef NFS_BOOT_DEFAULTS diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index eab9629..f3dc7fe 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -201,29 +201,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_S3C2410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define NAND_WAIT_READY(nand) NF_WaitRB() -#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) -#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) -#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) -#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) -#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) -#define WRITE_NAND(d, adr) NF_Write(d) -#define READ_NAND(adr) NF_Read() -/* the following functions are NOP's because S3C24X0 handles this in hardware */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */ #endif /* CONFIG_CMD_NAND */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 147233d..d16262b 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -118,7 +118,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -#define CONFIG_CMD_NAND #define CONFIG_CMD_NFS #define CONFIG_CMD_PING @@ -446,90 +445,9 @@ #define NAND_SIZE 0x00010000 /* 64K */ #define NAND_BASE 0xF1000000 -/****************************************************************/ - -/* NAND */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_BASE NAND_BASE -#define CONFIG_MTD_NAND_ECC_JFFS2 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_MTD_NAND_UNSAFE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#undef NAND_NO_RB - -#define SECTORSIZE 512 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ -#define NAND_DISABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ - } while(0) - -#define NAND_ENABLE_CE(nand) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ - } while(0) - -#define NAND_CTL_CLRALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_SETALE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ - } while(0) - -#define NAND_CTL_CLRCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ - } while(0) - -#define NAND_CTL_SETCLE(nandptr) \ - do { \ - (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ - } while(0) - -#ifndef NAND_NO_RB -#define NAND_WAIT_READY(nand) \ - do { \ - int _tries = 0; \ - while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ - if (++_tries > 100000) \ - break; \ - } while (0) -#else -#define NAND_WAIT_READY(nand) udelay(12) -#endif - -#define WRITE_NAND_COMMAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND_ADDRESS(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define WRITE_NAND(d, adr) \ - do { \ - *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ - } while(0) - -#define READ_NAND(adr) \ - ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) - /*****************************************************************************/ #define CONFIG_SYS_DIRECT_FLASH_TFTP -#define CONFIG_SYS_DIRECT_NAND_TFTP /*****************************************************************************/ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 3917a1b..425f472 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -147,12 +147,8 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC #define CONFIG_CMD_DATE - -#define CONFIG_NAND_LEGACY - /* * Miscellaneous configurable options */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 15c3708..0500042 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -193,7 +193,6 @@ /* * NAND Flash */ -#define CONFIG_NEW_NAND_CODE #define CONFIG_SYS_NAND0_BASE 0x0 #undef CONFIG_SYS_NAND1_BASE @@ -227,13 +226,6 @@ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 1 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - #define CONFIG_SYS_NO_FLASH 1 #define CONFIG_ENV_IS_IN_NAND 1 -- 1.5.6.rc1.6.gc53ad

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[U-Boot] [PATCH] EUKREA CPUIMX27 : update boot script
by Eric Benard 18 Jul '09

18 Jul '09

Update bootargs's mtdparts to be able to use latest kernel (imx_nand renamed to mxc_nand) Signed-off-by: Eric Benard <ebenard(a)eukrea.com> --- board/eukrea_cpuimx27/env/bin/boot | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/eukrea_cpuimx27/env/bin/boot b/board/eukrea_cpuimx27/env/bin/boot index dfb59aa..7bbff2d 100644 --- a/board/eukrea_cpuimx27/env/bin/boot +++ b/board/eukrea_cpuimx27/env/bin/boot @@ -31,7 +31,7 @@ else bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" fi -bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts" +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" if [ $kernel = net ]; then if [ x$ip = xdhcp ]; then -- 1.6.0.4

3 2

[U-Boot] [PATCH 1/1] LPC2468 support
by Remco Poelstra 18 Jul '09

18 Jul '09

This patch includes the LPC2468 processor from NXP. Included is a working board example. Signed-off-by: Remco Poelstra <remco.poelstra+u-boot(a)duran-audio.com> --- http://www.beryllium.net/~remco/u-boot.diff (144kb)

5 33

[U-Boot] [PATCH] pcm030: fix out-of-tree building
by Wolfgang Denk 18 Jul '09

18 Jul '09

Commit c9969947, which added support for the pcm030 board (aka phyCORE-MPC5200B-tiny), broke out-of-tree building. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 9e6346f..9ff846e 100644 --- a/Makefile +++ b/Makefile @@ -698,7 +698,7 @@ o2dnt_config: unconfig pcm030_config \ pcm030_LOWBOOT_config: unconfig - @ >include/config.h + @ >$(obj)include/config.h @[ -z "$(findstring LOWBOOT_,$@)" ] || \ { echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \ echo "... with LOWBOOT configuration" ; \ -- 1.6.0.6

1 0

[U-Boot] [PATCH] MPC837XERDB: fix warning: "CONFIG_SYS_MONITOR_LEN" redefined
by Wolfgang Denk 18 Jul '09

18 Jul '09

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- include/configs/MPC837XERDB.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 807a534..9132718 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -230,7 +230,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* -- 1.6.0.6

1 0

[U-Boot] [PATCH] MIP405T: fix compile problem
by Wolfgang Denk 18 Jul '09

18 Jul '09

The "stdio/device: rework function naming convention" patch (commit 52cb4d4f) broke the MIP405T board; this patch fixes it. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/mpl/common/common_util.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 243e3eb..f3632c2 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -429,7 +429,7 @@ void check_env(void) } -extern device_t *stdio_devices[]; +extern struct stdio_dev *stdio_devices[]; extern char *stdio_names[]; void show_stdio_dev(void) -- 1.6.0.6

1 0

[U-Boot] [PATCH] NAND: Fix warning Please define CONFIG_SYS_64BIT_VSPRINTF...
by Wolfgang Denk 18 Jul '09

18 Jul '09

Commit 8d2effea added a warning for configurations that use NAND without defining the (then necessary) CONFIG_SYS_64BIT_VSPRINTF but failed to fix the affected boards. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- include/configs/ASH405.h | 6 ++++-- include/configs/CMS700.h | 2 ++ include/configs/HH405.h | 2 ++ include/configs/HUB405.h | 2 ++ include/configs/IDS8247.h | 2 ++ include/configs/PLU405.h | 2 ++ include/configs/PPChameleonEVB.h | 3 +++ include/configs/TQM8272.h | 2 ++ include/configs/TQM85xx.h | 2 ++ include/configs/VOH405.h | 2 ++ include/configs/WUH405.h | 2 ++ include/configs/acadia.h | 2 ++ include/configs/kilauea.h | 2 ++ include/configs/quad100hd.h | 2 ++ include/configs/sc3.h | 1 + include/configs/socrates.h | 2 ++ 16 files changed, 34 insertions(+), 2 deletions(-) diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 2ee4f80..694a87b 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -157,8 +157,10 @@ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CONFIG_SYS_NAND_QUIET 1 + +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index ae8494d..2384925 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -165,6 +165,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 9233523..1a2266f 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -219,6 +219,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index ea502d4..518d94d 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -160,6 +160,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 51e012c..4c4af05 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -265,6 +265,8 @@ #define CONFIG_SYS_NAND0_BASE 0xE1000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + #endif /* CONFIG_CMD_NAND */ /*----------------------------------------------------------------------- diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 7f2337b..2e41526 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -183,6 +183,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /* * PCI stuff */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 16baf8c..6331464 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -210,6 +210,9 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ + +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /* * nand device 1 on dave (PPChameleonEVB) needs more time, * so we just introduce additional wait in nand_wait(), diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 9cac696..6c462af 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -439,6 +439,8 @@ WRITE_NAND(d, addr); \ } while(0) +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + #endif /* CONFIG_CMD_NAND */ #define CONFIG_PCI diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6f13c63..cc3649e 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -374,6 +374,8 @@ #define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + #endif /* CONFIG_NAND */ /* diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 38a1d0d..17397e8 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -169,6 +169,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 5c281a1..dbfa1aa 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -157,6 +157,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9ffd86b..b710107 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -265,6 +265,8 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 97bac99..df1b061 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -217,6 +217,8 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 3ea854b..d63c43e 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -225,6 +225,8 @@ #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 97e1da2..7e00ab8 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -426,6 +426,7 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x77D00000 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5b91b4d..35feed0 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -188,6 +188,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + /* LIME GDC */ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -- 1.6.0.6

1 0

[U-Boot] [PATCH] CPCI750: fix compile problem
by Wolfgang Denk 18 Jul '09

18 Jul '09

Commit bc0d3296 removed ppc_error_no.h from Marvell boards but forgot to update board/esd/cpci750/mv_eth.h Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/esd/cpci750/mv_eth.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h index c57e679..b761135 100644 --- a/board/esd/cpci750/mv_eth.h +++ b/board/esd/cpci750/mv_eth.h @@ -37,7 +37,7 @@ #include <common.h> #include <net.h> #include "mv_regs.h" -#include "../../Marvell/common/ppc_error_no.h" +#include <asm/errno.h> /************************************************************************* -- 1.6.0.6

1 0