July 2009 - U-Boot

[U-Boot] Can't start Linux if U-Boot built with CONFIG_WATCHDOG
by Matthew Lear 26 Aug '15

26 Aug '15

Hello all, I've added watchdog support based on U-Boot (git) for the m68k coldfire mcf54455evb platform. I've fed the patch to the maintainer to help in development. However, I am unable to start my m68k w/MMU coldfire Linux kernel from U-Boot if U-Boot is built with CONFIG_WATCHDOG regardless if the watchdog_enable(), watchdog_reset() and watchdog_disable() functions touch hardware or not. I initially thought this was a problem with enabling the watchdog somehow (ie when Linux started, some hw configuration in the device was getting upset or corrupted etc resulting in the failure), but when I commented out the code from the above functions that actually accesses the hw (ie to enable, kick and disable the watchdog timer hw block), Linux is still unable to start. In fact, I don't think Linux actually gets started! That's the problem. If I rebuild the same U-Boot code base with CONFIG_WATCHDOG undefined, Linux can start just fine. As far as I can tell, there are no functional differences in building U-Boot with or without CONFIG_WATCHDOG enabled when the functions above are stubs and do absolutely nothing at all. If I build U-Boot with debug, what I see is as follows: ## Transferring control to Linux (at address 40020000) ... BIV ...and then the board is dead. I occasionally see something like the following from U-Boot: *** Unexpected exception *** Vector Number: 4 Format: 04 Fault Status: 0 PC: 4fdbfdc8 SR: 00002700 SP: 4fd72a64 D0: 00000004 D1: 000003f9 D2: 4fdb4202 D3: 004fa3da D4: 00000000 D5: 4fdc7c8c D6: 122c0034 D7: 4fd82f76 A0: 4033cb98 A1: 4025aa39 A2: 40020000 A3: 4fdbfdc8 A4: 00000000 A5: 4fdc5800 A6: 4fd72afb *** Please Reset Board! *** The 'BIV' is relevant because in my 2.6.29 kernel src arch/m68k/include/asm/bootinfo_mm.h, BOOTINFOV_MAGIC is defined to be 0x4249561A which is BIV^Z. This ascii text is located in the kernel image header info: >From arch/m68k/coldfire/head.S: .section ".text.head","ax" ENTRY(_stext) bras 1f /* Jump over bootinfo version numbers */ .long BOOTINFOV_MAGIC .long 0 And from U-Boot itself: -> md ${loadaddr} 40010000: 27051956 97342d7d 4a54afd5 00300000 '..V.4-}JT...0.. 40010010: 40020000 40020000 8a006fc1 050c0200 @...@.....o..... 40010020: 4c696e75 78204b65 726e656c 20496d61 Linux Kernel Ima 40010030: 67650000 00000000 00000000 00000000 ge.............. 40010040: 60084249 561a0000 00004ef9 40304000 `.BIV.....N.@0@. I suspect that the failure of starting Linux is caused by some mismatch in data structures (or versions there of) shared/copied between Linux and U-Boot and that this data has somehow changed when U-Boot is built with CONFIG_WATCHDOG #defined. However, I can't find any evidence of this in the U-Boot code base. The bras instruction above must be key and I suspect that this is the area causing the problem. Can anybody offer any advice / explanation of what exactly could be going on and why? I wouldn't have expected that defining CONFIG_WATCHDOG would change anything as fundamental as this. Apologies for the cross-post (U-Boot and m68k kernel dev) but I hope to get opinions/feedback/help from both communities. Any assistance very much appreciated indeed. Many thanks, -- Matt

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[U-Boot] [PATCH] fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
by Kumar Gala 30 Aug '13

30 Aug '13

sys_eeprom.c: In function 'do_mac': sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules sys_eeprom.c: In function 'mac_read_from_eeprom': sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/sys_eeprom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ae5304a..3e1e332 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -78,12 +78,14 @@ static int has_been_read = 0; #ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif #ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif /** -- 1.6.0.6

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[U-Boot-Users] minimum bdi config to read flash on 85xx
by robert lazarski 28 May '13

28 May '13

Hi all, On our custom 8548 board, we can't read our flash correctly. We have one 1Gb bank of spansion S29GL01GP flash and we get: atum>mdh 0xf8000000 0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 The big problem we have now: is this a hardware issue or a bdi config issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone help us track our flash issues down to be hardware, config file, or some combination? The hardware guys think the board is fine. We've been deep into the manuals of both the 8548 and the bdi and can't find anything wrong. Here's the config, thanks for any help! ;bdiGDB configuration file for ATUM 8548 ;--------------------------------------------------- ; [INIT] ; ; ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001d ;LAWAR0 : DDR 1GB WM32 0xe0000C28 0xf8000000 ;LAWBAR1 : @0xf8000000 WM32 0xe0000C30 0x8040001a ;LAWAR1 : Local Bus 128MB for S29GL01GP ; ; Setup Flash chip select WM32 0xe0005000 0xf8001001 ;BR0 WM32 0xe0005004 0xf8000E65 ;OR0 ; CS0_BNDS WM32 0xe0002000 0x0000000f ; DDR CS0 ; CS0_CONFIG WM32 0xe0002080 0x80000102 ; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; TIMING_CFG_1 WM32 0xe0002108 0x38355322 ; TIMING_CFG_2 WM32 0xe000210C 0x039048c7 ; DDR_SDRAM_MODE WM32 0xe0002118 0x00000432 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x05150100 ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000000 ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 DELAY 200 ; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xc3000000 ;================= end flash programming ===================== ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 5000 ;let U-boot code setup the system STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [REGS] FILE $reg8548.def [HOST] IP 10.101.43.10 FILE vmlinux.8548 FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e500.bin PROMPT atum> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes - 1Gb BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin FORMAT BIN 0xF8000000 ERASE 0xF8000000 ;erase sector 0 [REGS] FILE $reg8548.def

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[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

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[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

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[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

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[U-Boot] [RFC] CDC Ethernet support + USB Gadget in U-boot
by Remy Bohmer 19 Jan '12

19 Jan '12

Hello All, We (Thomas Smits and I) have been working on CDC Ethernet support in U-boot. We ported the Linux Gadget and CDC Ethernet driver to U-boot and added support for the Atmel AT91SAM9261-EK kit. Support for other cores can be added easily. Although it is still work in progress, it is already working stable. I also have a patch for adding RNDIS support on top of this series, but that is not finished/stable yet. The series is quite huge, and still in development, so I decided to not post this series inline. I made the tree public via the U-boot-usb tree, 'cdc' branch ( http://git.denx.de/?p=u-boot/u-boot-usb.git;a=shortlog;h=refs/heads/cdc) I would like to stabilise this code in a separate branch until it is mature enough for mainline integration, I will keep this branch always ahead mainline. So, any comments on this code are welcome! But, even more welcome are patches on top of it to make it even better and add more board support for it. Kind Regards, Remy

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[U-Boot] Uboot for Mips
by Rahanesh 13 Sep '11

13 Sep '11

Hi All, I am currently working on MIPS board. I have a 32MB RAM. The address that is shown in uboot when i type bdinfo if 0x80000000 and size is 0x1000000(16MB). I want to increase the size to 32 MB as board has 32 MB RAM. Interesting Finding: When i write any data to 0x80000000 the same data is being written into 0x81000000. Same for all address in the range (data in 0x80000000 - 0x80ffffff is same as 0x81000000 - 0x81ffffff ). It seems that there is a dual mapping . What might be the reason? Please help -- View this message in context: http://www.nabble.com/Uboot-for-Mips-tp24366921p24366921.html Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] [PATCH] ppc4xx: Generic architecture for xilinx ppc405(v3)
by Ricardo Ribalda Delgado 24 Dec '10

24 Dec '10

As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)uam.es> --- v2 Includes changes propossed by Stefan Roese -Remove unneeded init.S -PPC404 ->PPC405 v3 rebased to ppc4xx/master CREDITS | 1 + MAINTAINERS | 1 + Makefile | 16 ++ board/xilinx/ppc405-generic/.gitignore | 1 + board/xilinx/ppc405-generic/Makefile | 60 ++++++++ board/xilinx/ppc405-generic/config.mk | 25 ++++ board/xilinx/ppc405-generic/u-boot-ram.lds | 134 ++++++++++++++++++ board/xilinx/ppc405-generic/u-boot-rom.lds | 144 ++++++++++++++++++++ .../xilinx/ppc405-generic/xilinx_ppc405_generic.c | 59 ++++++++ board/xilinx/ppc405-generic/xparameters.h | 36 +++++ cpu/ppc4xx/start.S | 3 +- include/configs/xilinx-ppc405-generic.h | 58 ++++++++ include/configs/xilinx-ppc405.h | 126 +++++++++++++++++ 13 files changed, 663 insertions(+), 1 deletions(-) create mode 100644 board/xilinx/ppc405-generic/.gitignore create mode 100644 board/xilinx/ppc405-generic/Makefile create mode 100644 board/xilinx/ppc405-generic/config.mk create mode 100644 board/xilinx/ppc405-generic/u-boot-ram.lds create mode 100644 board/xilinx/ppc405-generic/u-boot-rom.lds create mode 100644 board/xilinx/ppc405-generic/xilinx_ppc405_generic.c create mode 100644 board/xilinx/ppc405-generic/xparameters.h create mode 100644 include/configs/xilinx-ppc405-generic.h create mode 100644 include/configs/xilinx-ppc405.h diff --git a/CREDITS b/CREDITS index 3767322..9ddf0d2 100644 --- a/CREDITS +++ b/CREDITS @@ -407,6 +407,7 @@ N: Ricardo Ribalda Delgado E: ricardo.ribalda(a)uam.es D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval D: Virtex ppc440 generic architecture +D: Virtex ppc405 generic architecture W: http://www.ii.uam.es/~rribalda N: Stefan Roese diff --git a/MAINTAINERS b/MAINTAINERS index 60cb6a6..a5d1038 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -320,6 +320,7 @@ Ricardo Ribalda <ricardo.ribalda(a)uam.es> ml507 PPC440x5 v5fx30teval PPC440x5 xilinx-pp440-generic PPC440x5 + xilinx-pp405-generic PPC405 Stefan Roese <sr(a)denx.de> diff --git a/Makefile b/Makefile index fceb8a2..66922eb 100644 --- a/Makefile +++ b/Makefile @@ -1518,6 +1518,22 @@ sycamore_config: unconfig WUH405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd +xilinx-ppc405-generic_flash_config: unconfig + @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic + @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\ + > $(obj)board/xilinx/ppc405-generic/config.tmp + @echo "TEXT_BASE := 0xFE360000" \ + >> $(obj)board/xilinx/ppc405-generic/config.tmp + @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx + +xilinx-ppc405-generic_config: unconfig + @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic + @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\ + > $(obj)board/xilinx/ppc405-generic/config.tmp + @echo "TEXT_BASE := 0x04000000" \ + >> $(obj)board/xilinx/ppc405-generic/config.tmp + @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx + xilinx-ppc440-generic_flash_config: unconfig @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\ diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore new file mode 100644 index 0000000..b644f59 --- /dev/null +++ b/board/xilinx/ppc405-generic/.gitignore @@ -0,0 +1 @@ +config.tmp diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile new file mode 100644 index 0000000..b56bb49 --- /dev/null +++ b/board/xilinx/ppc405-generic/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +endif + +INCS := +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ppc405-generic/config.mk b/board/xilinx/ppc405-generic/config.mk new file mode 100644 index 0000000..6d76755 --- /dev/null +++ b/board/xilinx/ppc405-generic/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp diff --git a/board/xilinx/ppc405-generic/u-boot-ram.lds b/board/xilinx/ppc405-generic/u-boot-ram.lds new file mode 100644 index 0000000..0004d61 --- /dev/null +++ b/board/xilinx/ppc405-generic/u-boot-ram.lds @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ppc405-generic/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds new file mode 100644 index 0000000..d2bac9f --- /dev/null +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c new file mode 100644 index 0000000..9bd1770 --- /dev/null +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +ulong __get_PCI_freq(void) +{ + return 0; +} + +ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC405 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 0000000..e8e8ced --- /dev/null +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 31902a0..882ef21 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -918,7 +918,8 @@ _start: ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l mtdccr r4 -#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ + && !defined (CONFIG_XILINX_405) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h new file mode 100644 index 0000000..5036c62 --- /dev/null +++ b/include/configs/xilinx-ppc405-generic.h @@ -0,0 +1,58 @@ +/* + * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt <schardt(a)team-ctech.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_GEN_H +#define __CONFIG_GEN_H + +#include "../board/xilinx/ppc405-generic/xparameters.h" + +/* sdram */ +#define CONFIG_SYS_SDRAM_SIZE_MB 256 + +/* environment */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_SYS_ENV_OFFSET 0x3F0000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) +#define CONFIG_ENV_OVERWRITE 1 + +/*Misc*/ +#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define MTDIDS_DEFAULT "nor0=ppc405-flash" +#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" + +#include <configs/xilinx-ppc405.h> +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h new file mode 100644 index 0000000..7458470 --- /dev/null +++ b/include/configs/xilinx-ppc405.h @@ -0,0 +1,126 @@ +/* + * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt <schardt(a)team-ctech.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* cpu parameter */ +#define CONFIG_4xx 1 +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 + +/* memory map */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* u-boot commands configuration */ +#include <config_cmd_default.h> + +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + /* Initial Memory map for Linux */ +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SHIFT 2 + +/* stack */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_FLASH_CF 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_PROTECTION + +/* serial communication */ +#ifdef XPAR_UARTLITE_0_BASEADDR +#define CONFIG_XILINX_UARTLITE +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } +#else +#ifdef XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } +#endif +#endif + +/* cmd config */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +#endif -- 1.5.6.5

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[U-Boot] [PATCH] cmd_elf: CONFIG_ELF_SIMPLE_LOAD: load ELFs according to PHDRs
by Mike Frysinger 06 Oct '10

06 Oct '10

The current ELF loading function does a lot of work above and beyond a simple "loading". It ignores the real load addresses and loads things into their virtual (runtime) address. This is undesirable when we just want it to load an ELF and let the ELF do the actual C runtime init. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_elf.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 3ebb6d9..7b82749 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -276,6 +276,32 @@ int valid_elf_image (unsigned long addr) * A very simple elf loader, assumes the image is valid, returns the * entry point address. * ====================================================================== */ +#ifdef CONFIG_ELF_SIMPLE_LOAD +unsigned long load_elf_image (unsigned long addr) +{ + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + unsigned long entry; + size_t i; + + ehdr = (Elf32_Ehdr *) addr; + phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); + + entry = ehdr->e_entry; + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *) phdr->p_paddr; + void *src = (void *) addr + phdr->p_offset; + printf ("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + memcpy (dst, src, phdr->p_filesz); + ++phdr; + } + + return entry; +} +#else unsigned long load_elf_image (unsigned long addr) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ @@ -327,6 +353,7 @@ unsigned long load_elf_image (unsigned long addr) return ehdr->e_entry; } +#endif /* ====================================================================== */ U_BOOT_CMD( -- 1.6.0.3

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