July 2009 - U-Boot

[U-Boot] [PATCH] ppc4xx: Replace 4xx lowercase SPR references
by Matthias Fuchs 24 Jul '09

24 Jul '09

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- This patch replaces my patch from yesterday titled [PATCH V2] ppc4xx: use SPRN_TCR macro instead of tcr board/esd/pmc440/pmc440.c | 2 +- board/mpl/mip405/mip405.c | 2 +- board/mpl/pip405/pip405.c | 2 +- board/netstal/hcu5/hcu5.c | 8 +- board/netstal/hcu5/sdram.c | 4 +- board/netstal/mcu25/mcu25.c | 2 +- cpu/ppc4xx/cpu.c | 8 +- cpu/ppc4xx/cpu_init.c | 2 +- cpu/ppc4xx/interrupts.c | 18 ++-- cpu/ppc4xx/speed.c | 3 +- cpu/ppc4xx/start.S | 206 +++++++++++++++++++++--------------------- include/asm-ppc/processor.h | 46 ++++++++++ include/ppc405.h | 55 ------------ include/ppc440.h | 93 ------------------- post/cpu/ppc4xx/fpu.c | 6 +- 15 files changed, 178 insertions(+), 279 deletions(-) diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 2ab944d..f22a1c2 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -142,7 +142,7 @@ int board_early_init_f(void) reg |= CPR0_ICFG_RLI_MASK; mtcpr(clk_icfg, reg); - mtspr(dbcr0, 0x20000000); /* do chip reset */ + mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ } /* diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 24caa46..1738f54 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -688,7 +688,7 @@ int misc_init_r (void) start=get_timer(0); /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); } diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index f31a5e8..677437d 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -669,7 +669,7 @@ int misc_init_r (void) /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); } diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 6f4ec29..5eb33d3 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -89,8 +89,8 @@ int board_early_init_f(void) /* * Initiate system reset in debug control register DBCR */ - dbcr = mfspr(dbcr0); - mtspr(dbcr0, dbcr | CHIP_RESET); + dbcr = mfspr(SPRN_DBCR0); + mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif @@ -307,14 +307,14 @@ int misc_init_r(void) /* We cannot easily enable trace before, as there are other * routines messing around with sdr0_pfc1. And I do not need it. */ - if (mfspr(dbcr0) & 0x80000000) { + if (mfspr(SPRN_DBCR0) & 0x80000000) { /* External debugger alive * enable trace facilty for Lauterbach * CCR0[DTB]=0 Enable broadcast of trace information * SDR0_PFC0[TRE] Trace signals are enabled instead of * GPIO49-63 */ - mtspr(ccr0, mfspr(ccr0) &~ (CCR0_DTB)); + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB)); mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE); } return 0; diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index f59bd7d..5c2ec35 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -144,7 +144,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) u32 *magicPtr; u32 magic; - if ((mfspr(dbcr0) & 0x80000000) == 0) { + if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) { /* only if no external debugger is alive! * Check whether vxWorks is using EDR logging, if yes zero * also PostMortem and user reserved memory @@ -182,7 +182,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) * If not done, then we could get an interrupt later on when * exceptions are enabled. */ - mtspr(mcsr, mfspr(mcsr)); + mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 66ed95f..67c1b0b 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -77,7 +77,7 @@ int board_early_init_f (void) out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR ); out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); - mtspr(ccr0, 0x00700000); + mtspr(SPRN_CCR0, 0x00700000); return 0; } diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index fb3837c..e12a784 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -272,7 +272,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1) mtdcr (cpc0_sys0, sys0); mtdcr (cpc0_sys1, sys1); mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ + mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ return 1; } @@ -654,12 +654,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) board_reset(); #else #if defined(CONFIG_SYS_4xx_RESET_TYPE) - mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28); + mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28); #else /* * Initiate system reset in debug control register DBCR */ - mtspr(dbcr0, 0x30000000); + mtspr(SPRN_DBCR0, 0x30000000); #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */ #endif /* defined(CONFIG_BOARD_RESET) */ @@ -697,7 +697,7 @@ void reset_4xx_watchdog(void) /* * Clear TSR(WIS) bit */ - mtspr(tsr, 0x40000000); + mtspr(SPRN_TSR, 0x40000000); } #endif /* CONFIG_WATCHDOG */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bbd795d..65092fb 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -123,7 +123,7 @@ void reconfigure_pll(u32 new_cpu_freq) /* Reset processor if configuration changed */ if (reset_needed) { __asm__ __volatile__ ("sync; isync"); - mtspr(dbcr0, 0x20000000); + mtspr(SPRN_DBCR0, 0x20000000); } #endif } diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 494bd8c..6db8421 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -102,15 +102,15 @@ int interrupt_init_cpu (unsigned *decrementer_count) * Init PIT */ #if defined(CONFIG_440) - val = mfspr( tcr ); + val = mfspr( SPRN_TCR ); val &= (~0x04400000); /* clear DIS & ARE */ - mtspr( tcr, val ); - mtspr( dec, 0 ); /* Prevent exception after TSR clear*/ - mtspr( decar, 0 ); /* clear reload */ - mtspr( tsr, 0x08000000 ); /* clear DEC status */ + mtspr( SPRN_TCR, val ); + mtspr( SPRN_DEC, 0 ); /* Prevent exception after TSR clear*/ + mtspr( SPRN_DECAR, 0 ); /* clear reload */ + mtspr( SPRN_TSR, 0x08000000 ); /* clear DEC status */ val = gd->bd->bi_intfreq/1000; /* 1 msec */ - mtspr( decar, val ); /* Set auto-reload value */ - mtspr( dec, val ); /* Set inital val */ + mtspr( SPRN_DECAR, val ); /* Set auto-reload value */ + mtspr( SPRN_DEC, val ); /* Set inital val */ #else set_pit(gd->bd->bi_intfreq / 1000); #endif @@ -126,9 +126,9 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Enable PIT */ - val = mfspr(tcr); + val = mfspr(SPRN_TCR); val |= 0x04400000; - mtspr(tcr, val); + mtspr(SPRN_TCR, val); /* * Set EVPR to 0 diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index ed6e55b..e1a634c 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -394,7 +394,8 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqUART = sysInfo->freqPLB; /* Figure which timer source to use */ - if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ + if (mfspr(SPRN_CCR1) & 0x0080) { + /* External Clock, assume same as SYS_CLK */ temp = sysInfo->freqProcessor / 2; /* Max extern clock speed */ if (CONFIG_SYS_CLK_FREQ > temp) sysInfo->freqTmrClk = temp; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 582c781..90e66d9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -297,7 +297,7 @@ _start_440: | Core bug fix. Clear the esr +-----------------------------------------------------------------*/ li r0,0 - mtspr esr,r0 + mtspr SPRN_ESR,r0 /*----------------------------------------------------------------*/ /* Clear and set up some registers. */ /*----------------------------------------------------------------*/ @@ -305,16 +305,16 @@ _start_440: dccci r0,r0 /* NOTE: operands not used for 440 */ sync li r0,0 - mtspr srr0,r0 - mtspr srr1,r0 - mtspr csrr0,r0 - mtspr csrr1,r0 + mtspr SPRN_SRR0,r0 + mtspr SPRN_SRR1,r0 + mtspr SPRN_CSRR0,r0 + mtspr SPRN_CSRR1,r0 /* NOTE: 440GX adds machine check status regs */ #if defined(CONFIG_440) && !defined(CONFIG_440GP) - mtspr mcsrr0,r0 - mtspr mcsrr1,r0 - mfspr r1,mcsr - mtspr mcsr,r1 + mtspr SPRN_MCSRR0,r0 + mtspr SPRN_MCSRR1,r0 + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 #endif /*----------------------------------------------------------------*/ @@ -326,27 +326,27 @@ _start_440: */ lis r1,0x0030 /* store gathering & broadcast disable */ ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 + mtspr SPRN_CCR0,r1 /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ - mfspr r1,dbcr0 + mfspr r1,SPRN_DBCR0 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ bne skip_debug_init /* if set, don't clear debug register */ - mtspr dbcr0,r0 - mtspr dbcr1,r0 - mtspr dbcr2,r0 - mtspr iac1,r0 - mtspr iac2,r0 - mtspr iac3,r0 - mtspr dac1,r0 - mtspr dac2,r0 - mtspr dvc1,r0 - mtspr dvc2,r0 - - mfspr r1,dbsr - mtspr dbsr,r1 /* Clear all valid bits */ + mtspr SPRN_DBCR0,r0 + mtspr SPRN_DBCR1,r0 + mtspr SPRN_DBCR2,r0 + mtspr SPRN_IAC1,r0 + mtspr SPRN_IAC2,r0 + mtspr SPRN_IAC3,r0 + mtspr SPRN_DAC1,r0 + mtspr SPRN_DAC2,r0 + mtspr SPRN_DVC1,r0 + mtspr SPRN_DVC2,r0 + + mfspr r1,SPRN_DBSR + mtspr SPRN_DBSR,r1 /* Clear all valid bits */ skip_debug_init: #if defined (CONFIG_440SPE) @@ -364,68 +364,68 @@ skip_debug_init: | j. TCS: Timebase increments from CPU clock. +-----------------------------------------------------------------*/ li r0,0 - mtspr ccr1, r0 + mtspr SPRN_CCR1, r0 /*----------------------------------------------------------------+ | Reset the timebase. | The previous write to CCR1 sets the timebase source. +-----------------------------------------------------------------*/ - mtspr tbl, r0 - mtspr tbu, r0 + mtspr SPRN_TBWL, r0 + mtspr SPRN_TBWU, r0 #endif /*----------------------------------------------------------------*/ /* Setup interrupt vectors */ /*----------------------------------------------------------------*/ - mtspr ivpr,r0 /* Vectors start at 0x0000_0000 */ + mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ li r1,0x0100 - mtspr ivor0,r1 /* Critical input */ + mtspr SPRN_IVOR0,r1 /* Critical input */ li r1,0x0200 - mtspr ivor1,r1 /* Machine check */ + mtspr SPRN_IVOR1,r1 /* Machine check */ li r1,0x0300 - mtspr ivor2,r1 /* Data storage */ + mtspr SPRN_IVOR2,r1 /* Data storage */ li r1,0x0400 - mtspr ivor3,r1 /* Instruction storage */ + mtspr SPRN_IVOR3,r1 /* Instruction storage */ li r1,0x0500 - mtspr ivor4,r1 /* External interrupt */ + mtspr SPRN_IVOR4,r1 /* External interrupt */ li r1,0x0600 - mtspr ivor5,r1 /* Alignment */ + mtspr SPRN_IVOR5,r1 /* Alignment */ li r1,0x0700 - mtspr ivor6,r1 /* Program check */ + mtspr SPRN_IVOR6,r1 /* Program check */ li r1,0x0800 - mtspr ivor7,r1 /* Floating point unavailable */ + mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ li r1,0x0c00 - mtspr ivor8,r1 /* System call */ + mtspr SPRN_IVOR8,r1 /* System call */ li r1,0x0a00 - mtspr ivor9,r1 /* Auxiliary Processor unavailable */ + mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ li r1,0x0900 - mtspr ivor10,r1 /* Decrementer */ + mtspr SPRN_IVOR10,r1 /* Decrementer */ li r1,0x1300 - mtspr ivor13,r1 /* Data TLB error */ + mtspr SPRN_IVOR13,r1 /* Data TLB error */ li r1,0x1400 - mtspr ivor14,r1 /* Instr TLB error */ + mtspr SPRN_IVOR14,r1 /* Instr TLB error */ li r1,0x2000 - mtspr ivor15,r1 /* Debug */ + mtspr SPRN_IVOR15,r1 /* Debug */ /*----------------------------------------------------------------*/ /* Configure cache regions */ /*----------------------------------------------------------------*/ - mtspr inv0,r0 - mtspr inv1,r0 - mtspr inv2,r0 - mtspr inv3,r0 - mtspr dnv0,r0 - mtspr dnv1,r0 - mtspr dnv2,r0 - mtspr dnv3,r0 - mtspr itv0,r0 - mtspr itv1,r0 - mtspr itv2,r0 - mtspr itv3,r0 - mtspr dtv0,r0 - mtspr dtv1,r0 - mtspr dtv2,r0 - mtspr dtv3,r0 + mtspr SPRN_INV0,r0 + mtspr SPRN_INV1,r0 + mtspr SPRN_INV2,r0 + mtspr SPRN_INV3,r0 + mtspr SPRN_DNV0,r0 + mtspr SPRN_DNV1,r0 + mtspr SPRN_DNV2,r0 + mtspr SPRN_DNV3,r0 + mtspr SPRN_ITV0,r0 + mtspr SPRN_ITV1,r0 + mtspr SPRN_ITV2,r0 + mtspr SPRN_ITV3,r0 + mtspr SPRN_DTV0,r0 + mtspr SPRN_DTV1,r0 + mtspr SPRN_DTV2,r0 + mtspr SPRN_DTV3,r0 /*----------------------------------------------------------------*/ /* Cache victim limits */ @@ -434,17 +434,17 @@ skip_debug_init: */ lis r1,0x0001 ori r1,r1,0xf800 - mtspr ivlim,r1 - mtspr dvlim,r1 + mtspr SPRN_IVLIM,r1 + mtspr SPRN_DVLIM,r1 /*----------------------------------------------------------------+ |Initialize MMUCR[STID] = 0. +-----------------------------------------------------------------*/ - mfspr r0,mmucr + mfspr r0,SPRN_MMUCR addis r1,0,0xFFFF ori r1,r1,0xFF00 and r0,r0,r1 - mtspr mmucr,r0 + mtspr SPRN_MMUCR,r0 /*----------------------------------------------------------------*/ /* Clear all TLB entries -- TID = 0, TS = 0 */ @@ -516,9 +516,9 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ b _start 3: li r0,0 - mtspr srr1,r0 /* Keep things disabled for now */ + mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ mflr r1 - mtspr srr0,r1 + mtspr SPRN_SRR0,r1 rfi #endif /* CONFIG_440 */ @@ -622,12 +622,12 @@ _start: /*----------------------------------------------------------------*/ li r0,0x0000 lis r1,0xffff - mtspr dec,r0 /* prevent dec exceptions */ - mtspr tbl,r0 /* prevent fit & wdt exceptions */ - mtspr tbu,r0 - mtspr tsr,r1 /* clear all timer exception status */ - mtspr tcr,r0 /* disable all */ - mtspr esr,r0 /* clear exception syndrome register */ + mtspr SPRN_DEC,r0 /* prevent dec exceptions */ + mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ + mtspr SPRN_TBWU,r0 + mtspr SPRN_TSR,r1 /* clear all timer exception status */ + mtspr SPRN_TCR,r0 /* disable all */ + mtspr SPRN_ESR,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */ /*----------------------------------------------------------------*/ @@ -638,10 +638,10 @@ _start: #if defined(CONFIG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff - mtspr dbsr,r1 /* Clear all status bits */ + mtspr SPRN_DBSR,r1 /* Clear all status bits */ lis r0,CONFIG_SYS_INIT_DBCR@h ori r0,r0,CONFIG_SYS_INIT_DBCR@l - mtspr dbcr0,r0 + mtspr SPRN_DBCR0,r0 isync #endif @@ -680,17 +680,17 @@ _start: /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ lis r1,0x0201 ori r1,r1,0xf808 - mtspr dvlim,r1 + mtspr SPRN_DVLIM,r1 lis r1,0x0808 ori r1,r1,0x0808 - mtspr dnv0,r1 - mtspr dnv1,r1 - mtspr dnv2,r1 - mtspr dnv3,r1 - mtspr dtv0,r1 - mtspr dtv1,r1 - mtspr dtv2,r1 - mtspr dtv3,r1 + mtspr SPRN_DNV0,r1 + mtspr SPRN_DNV1,r1 + mtspr SPRN_DNV2,r1 + mtspr SPRN_DNV3,r1 + mtspr SPRN_DTV0,r1 + mtspr SPRN_DTV1,r1 + mtspr SPRN_DTV2,r1 + mtspr SPRN_DTV3,r1 msync isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ @@ -809,7 +809,7 @@ _start: /* Set up some machine state registers. */ /*----------------------------------------------------------------------- */ addi r0,r0,0x0000 /* initialize r0 to zero */ - mtspr esr,r0 /* clear Exception Syndrome Reg */ + mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */ mttcr r0 /* timer control register */ mtexier r0 /* disable all interrupts */ addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ @@ -919,7 +919,7 @@ _start: /*----------------------------------------------------------------------- */ addi r4,r0,0x0000 #if !defined(CONFIG_405EX) - mtspr sgr,r4 + mtspr SPRN_SGR,r4 #else /* * On 405EX, completely clearing the SGR leads to PPC hangup @@ -928,9 +928,9 @@ _start: */ lis r3,0x0000 ori r3,r3,0x7FFC - mtspr sgr,r3 + mtspr SPRN_SGR,r3 #endif - mtspr dcwr,r4 + mtspr SPRN_DCWR,r4 mtesr r4 /* clear Exception Syndrome Reg */ mttcr r4 /* clear Timer Control Reg */ mtxer r4 /* clear Fixed-Point Exception Reg */ @@ -1266,8 +1266,8 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr csrr0,r2 - mtspr csrr1,r0 + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -1297,8 +1297,8 @@ mck_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr mcsrr0,r2 - mtspr mcsrr1,r0 + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -1448,17 +1448,17 @@ relocate_code: /* set TFLOOR/NFLOOR to 0 again */ lis r6,0x0001 ori r6,r6,0xf800 - mtspr dvlim,r6 + mtspr SPRN_DVLIM,r6 lis r6,0x0000 ori r6,r6,0x0000 - mtspr dnv0,r6 - mtspr dnv1,r6 - mtspr dnv2,r6 - mtspr dnv3,r6 - mtspr dtv0,r6 - mtspr dtv1,r6 - mtspr dtv2,r6 - mtspr dtv3,r6 + mtspr SPRN_DNV0,r6 + mtspr SPRN_DNV1,r6 + mtspr SPRN_DNV2,r6 + mtspr SPRN_DNV3,r6 + mtspr SPRN_DTV0,r6 + mtspr SPRN_DTV1,r6 + mtspr SPRN_DTV2,r6 + mtspr SPRN_DTV3,r6 msync isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ @@ -1478,8 +1478,8 @@ relocate_code: isync /* Clear all potential pending exceptions */ - mfspr r1,mcsr - mtspr mcsr,r1 + mfspr r1,SPRN_MCSR + mtspr SPRN_MCSR,r1 #ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ #else @@ -1723,9 +1723,9 @@ trap_init: __440_msr_set: addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ - mtspr srr1,r7 + mtspr SPRN_SRR1,r7 mflr r7 - mtspr srr0,r7 + mtspr SPRN_SRR0,r7 rfi __440_msr_continue: #endif @@ -2059,7 +2059,7 @@ pll_wait: * Not sure if this is needed... */ addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ /* execution will continue from the poweron */ /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 65546ad..2c0c0ce 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -96,6 +96,10 @@ #define CONFIG_BOOKE #endif +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -166,6 +170,9 @@ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ @@ -173,6 +180,10 @@ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define DCWR_COPY 0 /* Copy-back */ @@ -184,7 +195,20 @@ #endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif #define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ @@ -269,16 +293,34 @@ #define ICCR_NOCACHE 0 /* Noncacheable */ #define ICCR_CACHE 1 /* Cacheable */ #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#endif #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#ifdef CONFIG_BOOKE +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#endif #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#endif #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ @@ -297,6 +339,9 @@ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#endif #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ @@ -315,6 +360,7 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ + #ifdef CONFIG_BOOKE #define SPRN_SVR 0x3FF /* System Version Register */ #else diff --git a/include/ppc405.h b/include/ppc405.h index 917afec..a17dd35 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -32,61 +32,6 @@ #define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ #endif -/*--------------------------------------------------------------------- */ -/* Special Purpose Registers */ -/*--------------------------------------------------------------------- */ - #define srr2 0x3de /* save/restore register 2 */ - #define srr3 0x3df /* save/restore register 3 */ - - /* - * 405 does not really have CSRR0/1 but SRR2/3 are used during critical - * exception for the exact same purposes - let's alias them and have a - * common handling in crit_return() and CRIT_EXCEPTION - */ - #define csrr0 srr2 - #define csrr1 srr3 - - #define dbsr 0x3f0 /* debug status register */ - #define dbcr0 0x3f2 /* debug control register 0 */ - #define dbcr1 0x3bd /* debug control register 1 */ - #define iac1 0x3f4 /* instruction address comparator 1 */ - #define iac2 0x3f5 /* instruction address comparator 2 */ - #define iac3 0x3b4 /* instruction address comparator 3 */ - #define iac4 0x3b5 /* instruction address comparator 4 */ - #define dac1 0x3f6 /* data address comparator 1 */ - #define dac2 0x3f7 /* data address comparator 2 */ - #define dccr 0x3fa /* data cache control register */ - #define iccr 0x3fb /* instruction cache control register */ - #define esr 0x3d4 /* execption syndrome register */ - #define dear 0x3d5 /* data exeption address register */ - #define evpr 0x3d6 /* exeption vector prefix register */ - #define tsr 0x3d8 /* timer status register */ - #define tcr 0x3da /* timer control register */ - #define pit 0x3db /* programmable interval timer */ - #define sgr 0x3b9 /* storage guarded reg */ - #define dcwr 0x3ba /* data cache write-thru reg*/ - #define sler 0x3bb /* storage little-endian reg */ - #define cdbcr 0x3d7 /* cache debug cntrl reg */ - #define icdbdr 0x3d3 /* instr cache dbug data reg*/ - #define ccr0 0x3b3 /* core configuration register */ - #define dvc1 0x3b6 /* data value compare register 1 */ - #define dvc2 0x3b7 /* data value compare register 2 */ - #define pid 0x3b1 /* process ID */ - #define su0r 0x3bc /* storage user-defined register 0 */ - #define zpr 0x3b0 /* zone protection regsiter */ - - #define tbl 0x11c /* time base lower - privileged write */ - #define tbu 0x11d /* time base upper - privileged write */ - - #define sprg4r 0x104 /* Special purpose general 4 - read only */ - #define sprg5r 0x105 /* Special purpose general 5 - read only */ - #define sprg6r 0x106 /* Special purpose general 6 - read only */ - #define sprg7r 0x107 /* Special purpose general 7 - read only */ - #define sprg4w 0x114 /* Special purpose general 4 - write only */ - #define sprg5w 0x115 /* Special purpose general 5 - write only */ - #define sprg6w 0x116 /* Special purpose general 6 - write only */ - #define sprg7w 0x117 /* Special purpose general 7 - write only */ - /****************************************************************************** * Special for PPC405GP ******************************************************************************/ diff --git a/include/ppc440.h b/include/ppc440.h index 01f6eaf..6ce53a6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -48,99 +48,6 @@ #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ -/*--------------------------------------------------------------------- */ -/* Special Purpose Registers */ -/*--------------------------------------------------------------------- */ -#define xer_reg 0x001 -#define lr_reg 0x008 -#define dec 0x016 /* decrementer */ -#define srr0 0x01a /* save/restore register 0 */ -#define srr1 0x01b /* save/restore register 1 */ -#define pid 0x030 /* process id */ -#define decar 0x036 /* decrementer auto-reload */ -#define csrr0 0x03a /* critical save/restore register 0 */ -#define csrr1 0x03b /* critical save/restore register 1 */ -#define dear 0x03d /* data exception address register */ -#define esr 0x03e /* exception syndrome register */ -#define ivpr 0x03f /* interrupt prefix register */ -#define usprg0 0x100 /* user special purpose register general 0 */ -#define usprg1 0x110 /* user special purpose register general 1 */ -#define tblr 0x10c /* time base lower, read only */ -#define tbur 0x10d /* time base upper, read only */ -#define sprg1 0x111 /* special purpose register general 1 */ -#define sprg2 0x112 /* special purpose register general 2 */ -#define sprg3 0x113 /* special purpose register general 3 */ -#define sprg4 0x114 /* special purpose register general 4 */ -#define sprg5 0x115 /* special purpose register general 5 */ -#define sprg6 0x116 /* special purpose register general 6 */ -#define sprg7 0x117 /* special purpose register general 7 */ -#define tbl 0x11c /* time base lower (supervisor)*/ -#define tbu 0x11d /* time base upper (supervisor)*/ -#define pir 0x11e /* processor id register */ -#define dbsr 0x130 /* debug status register */ -#define dbcr0 0x134 /* debug control register 0 */ -#define dbcr1 0x135 /* debug control register 1 */ -#define dbcr2 0x136 /* debug control register 2 */ -#define iac1 0x138 /* instruction address compare 1 */ -#define iac2 0x139 /* instruction address compare 2 */ -#define iac3 0x13a /* instruction address compare 3 */ -#define iac4 0x13b /* instruction address compare 4 */ -#define dac1 0x13c /* data address compare 1 */ -#define dac2 0x13d /* data address compare 2 */ -#define dvc1 0x13e /* data value compare 1 */ -#define dvc2 0x13f /* data value compare 2 */ -#define tsr 0x150 /* timer status register */ -#define tcr 0x154 /* timer control register */ -#define ivor0 0x190 /* interrupt vector offset register 0 */ -#define ivor1 0x191 /* interrupt vector offset register 1 */ -#define ivor2 0x192 /* interrupt vector offset register 2 */ -#define ivor3 0x193 /* interrupt vector offset register 3 */ -#define ivor4 0x194 /* interrupt vector offset register 4 */ -#define ivor5 0x195 /* interrupt vector offset register 5 */ -#define ivor6 0x196 /* interrupt vector offset register 6 */ -#define ivor7 0x197 /* interrupt vector offset register 7 */ -#define ivor8 0x198 /* interrupt vector offset register 8 */ -#define ivor9 0x199 /* interrupt vector offset register 9 */ -#define ivor10 0x19a /* interrupt vector offset register 10 */ -#define ivor11 0x19b /* interrupt vector offset register 11 */ -#define ivor12 0x19c /* interrupt vector offset register 12 */ -#define ivor13 0x19d /* interrupt vector offset register 13 */ -#define ivor14 0x19e /* interrupt vector offset register 14 */ -#define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440) -#define mcsrr0 0x23a /* machine check save/restore register 0 */ -#define mcsrr1 0x23b /* mahcine check save/restore register 1 */ -#define mcsr 0x23c /* machine check status register */ -#endif -#define inv0 0x370 /* instruction cache normal victim 0 */ -#define inv1 0x371 /* instruction cache normal victim 1 */ -#define inv2 0x372 /* instruction cache normal victim 2 */ -#define inv3 0x373 /* instruction cache normal victim 3 */ -#define itv0 0x374 /* instruction cache transient victim 0 */ -#define itv1 0x375 /* instruction cache transient victim 1 */ -#define itv2 0x376 /* instruction cache transient victim 2 */ -#define itv3 0x377 /* instruction cache transient victim 3 */ -#define dnv0 0x390 /* data cache normal victim 0 */ -#define dnv1 0x391 /* data cache normal victim 1 */ -#define dnv2 0x392 /* data cache normal victim 2 */ -#define dnv3 0x393 /* data cache normal victim 3 */ -#define dtv0 0x394 /* data cache transient victim 0 */ -#define dtv1 0x395 /* data cache transient victim 1 */ -#define dtv2 0x396 /* data cache transient victim 2 */ -#define dtv3 0x397 /* data cache transient victim 3 */ -#define dvlim 0x398 /* data cache victim limit */ -#define ivlim 0x399 /* instruction cache victim limit */ -#define rstcfg 0x39b /* reset configuration */ -#define dcdbtrl 0x39c /* data cache debug tag register low */ -#define dcdbtrh 0x39d /* data cache debug tag register high */ -#define icdbtrl 0x39e /* instruction cache debug tag register low */ -#define icdbtrh 0x39f /* instruction cache debug tag register high */ -#define mmucr 0x3b2 /* mmu control register */ -#define ccr0 0x3b3 /* core configuration register 0 */ -#define ccr1 0x378 /* core configuration for 440x5 only */ -#define icdbdr 0x3d3 /* instruction cache debug data register */ -#define dbdr 0x3f3 /* debug data register */ - /****************************************************************************** * DCRs & Related ******************************************************************************/ diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index fff4169..e9b96dd 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -34,7 +34,7 @@ int fpu_status(void) { - if (mfspr(ccr0) & CCR0_DAPUIB) + if (mfspr(SPRN_CCR0) & CCR0_DAPUIB) return 0; /* Disabled */ else return 1; /* Enabled */ @@ -43,14 +43,14 @@ int fpu_status(void) void fpu_disable(void) { - mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB); + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) | CCR0_DAPUIB); mtmsr(mfmsr() & ~MSR_FP); } void fpu_enable(void) { - mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB); + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) & ~CCR0_DAPUIB); mtmsr(mfmsr() | MSR_FP); } -- 1.6.1

3 4

[U-Boot] ubi attaching error (UBI error: ubi_read_volume_table)
by naveen yadav 24 Jul '09

24 Jul '09

Hi All, I am using flex-onenand for my u-boot. i have added the patch for flex-onenand and UBI and UBIFS published by kyungmin park. I have done following steps: 1. first command # onenand erase 0x40000 0x200000 2. second command # mtdparts default 3. third commad # mtdparts 4. forth command # ubi part u-boot (i got error UBI error: ubi_read_volume_table: the layout volume was not found attach_by_scanning-4 UBI error: ubi_init: cannot attach mtd1 UBI error: ubi_init: UBI error: cannot initialize UBI, error -22 UBI init error -22 ) a) first command out put 1. # mtdparts default ---mtdparts_init--- last_ids : onenand0=onenand env_ids : onenand0=onenand last_parts: mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) env_parts : mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) last_partition : onenand0,0 env_partition : <NULL> no partition variable set, setting... --- current_save --- => partition onenand0,0 --- index partitions --- --- mtd_part_info: partition number 0 for device onenand0 (onenand) => mtddevnum 0, => mtddevname u-boot 2. second command output # mtdparts ---mtdparts_init--- last_ids : onenand0=onenand env_ids : onenand0=onenand last_parts: mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) env_parts : mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) last_partition : onenand0,0 env_partition : onenand0,0 ---list_partitions--- device onenand0 <onenand>, # parts = 6 #: name size offset mask_flags 0: u-boot 0x00200000 0x00040000 0 1: params 0x00040000 0x00240000 0 2: kernel 0x00200000 0x00280000 0 3: rootfs 0x01000000 0x00480000 0 4: fs 0x02000000 0x01480000 0 5: ubifs 0x3c480000 0x03480000 0 --- mtd_part_info: partition number 0 for device onenand0 (onenand) active partition: onenand0,0 - (u-boot) 0x00200000 @ 0x00040000 defaults: mtdids : onenand0=onenand mtdparts: mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs),3 2m(fs),-(ubifs) 3. Third command output # ubi part u-boot ---mtdparts_init--- last_ids : onenand0=onenand env_ids : onenand0=onenand last_parts: mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) env_parts : mtdparts=onenand:2m@256k(u-boot),256k(params),2m(kernel),16m(rootfs) ,32m(fs),-(ubifs) last_partition : onenand0,0 env_partition : onenand0,0 448 do_ubi -1454 do_ubi -2466 do_ubi -5--- find_dev_and_part --- id = u-boot --- find_dev_and_part --- id = u-boot Creating 1 MTD partitions on "onenand0": 0x%lx-0x%lx : "" UBI: attaching mtd1 to ubi0 ubi_attach_mtd_dev UBI: min_io_size 2048 UBI: hdrs_min_io_size 512 UBI: ec_hdr_alsize 512 UBI: vid_hdr_alsize 512 UBI: vid_hdr_offset 512 UBI: vid_hdr_aloffset 512 UBI: vid_hdr_shift 0 UBI: leb_start 2048 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 129024 bytes UBI: smallest flash I/O unit: 2048 UBI: sub-page size: 512 UBI: VID header offset: 512 (aligned 512) UBI: data offset: 2048 UBI error: ubi_read_volume_table: the layout volume was not found attach_by_scanning-4 UBI error: ubi_init: cannot attach mtd1 UBI error: ubi_init: UBI error: cannot initialize UBI, error -22 UBI init error -22

2 1

[U-Boot] [PATCH] ppc4xx: /PLLOUTB/CPU clock/ Default bootstrap options A, B, C, D
by Rupjyoti Sarmah 24 Jul '09

24 Jul '09

Unstable 440EPx operation due to default bootsrtap options settings. The 440EPx fixed bootstrap options A,B,C,D sets PLL FWDVA to a value 1 that results PLLOUTB being greater than the CPU clock frequency. This results unstable 440EPx operation causing hang conditions. This is a patch fixing this problem. The patch touches two files speed.c and cpu_init.c. Signed off by Rupjyoti Sarmah < rsarmah(a)amcc.com > from Applied Micro ---------------------------------- diff --git a/a/u-boot-2009.06/cpu/ppc4xx/cpu_init.c b/b/u-boot-2009.06/cpu/ppc4xx/cpu_init.c old mode 100644 new mode 100755 index 577d33f..eb50c3c --- a/a/u-boot-2009.06/cpu/ppc4xx/cpu_init.c +++ b/b/u-boot-2009.06/cpu/ppc4xx/cpu_init.c @@ -1,4 +1,4 @@ -/* + /* * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * @@ -32,10 +32,19 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CONFIG_SYS_PLL_RECONFIG -#define CONFIG_SYS_PLL_RECONFIG 0 +#ifndef CFG_PLL_RECONFIG +#define CFG_PLL_RECONFIG 0 #endif + +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + + + + void reconfigure_pll(u32 new_cpu_freq) { #if defined(CONFIG_440EPX) @@ -47,6 +56,7 @@ void reconfigure_pll(u32 new_cpu_freq) perdv0, target_perdv0, /* CLK_PERD */ spcid0, target_spcid0; /* CLK_SPCID */ + /* Reconfigure clocks if necessary. * See PPC440EPx User's Manual, sections 8.2 and 14 */ if (new_cpu_freq == 667) { @@ -111,17 +121,105 @@ void reconfigure_pll(u32 new_cpu_freq) mtcpr(clk_spcid, reg); reset_needed = 1; } + } + +/* +440EPx fixed bootstrap options A, B, D, and E currently set PLL FWDVA to a +divisor value = 1. This results in the PLLOUTB being greater than the CPU +clock frequency which causes unstable 440EPx operation resulting in various +software hang conditions. The user manual and the data sheet both specify that +a FWDVB = 1 is not a valid setting. + +If the customer uses the IIC attached EEPROM to set bootstrap options, this is +not a problem. Some customers choose to use one of the fixed bootstrap options +(A, B, D, or E)and do not have an EEPROM to use for programmable bootstrap +options. This requires that FWDVA and PRBDV0 be re-programmed early in the chip +initialization process by software. The procedure for re-programming the PLL +is defined in the 440EPx user manual section 8.3, Bootstrap Options. +*/ + + + + + + + - /* Set reload inhibit so configuration will persist across - * processor resets */ + /* Get current value of FWDVA.*/ + + mfcpr(clk_plld, reg); + temp = (reg & PLLD_FWDVA_MASK) >> 16; + /* Check to see if FWDVA has */ + /* been set to a value of 1. if*/ + /* it has we must modify it. */ + + if (temp == 1) { + + mfcpr(clk_plld, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + + /* Load register that contains */ + /* current boot strapping */ + /* option. */ mfcpr(clk_icfg, reg); - reg &= ~CPR0_ICFG_RLI_MASK; - reg |= 1 << 31; - mtcpr(clk_icfg, reg); - } + /* Shift strapping option into */ + /* low 3 bits. */ + reg = (reg >> 28); + + switch(reg) { + case BOOT_STRAP_OPTION_A: + case BOOT_STRAP_OPTION_B: + case BOOT_STRAP_OPTION_D: + case BOOT_STRAP_OPTION_E: + /* Get current value of FWDVA.*/ + /* Assign current FWDVA to */ + /* new FWDVB. */ + mfcpr(clk_plld, reg); + target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; + fwdvb = target_fwdvb ? target_fwdvb : 8; + /* Get current value of FWDVB.*/ + /* Assign current FWDVB to */ + /* new FWDVA. */ + target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; + fwdva = target_fwdva ? target_fwdva : 16; + /* Update clk_plld with */ + /* switched FWDVA and FWDVB. */ + reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | PLLD_FBDV_MASK | PLLD_LFBDV_MASK); + reg |= ((fwdva == 16 ? 0 : fwdva) << 16) | + ((fwdvb == 8 ? 0 : fwdvb) << 8) | + ((fbdv == 32 ? 0 : fbdv) << 24) | + (lfbdv == 64 ? 0 : lfbdv); + mtcpr(clk_plld, reg); + /* Acknowledge that a reset */ + /* is required. */ + + reset_needed = 1; + break; + + default: + /* All other case are OK. */ + /* Nothing to do. */ + break; + } - /* Reset processor if configuration changed */ - if (reset_needed) { + } + + if (reset_needed) { + /* Set reload inhibit so */ + /* configuration will persist */ + /* across processor reset. */ + mfcpr(clk_icfg, reg); + reg &= ~CPR0_ICFG_RLI_MASK; + reg |= 1 << 31; + mtcpr(clk_icfg, reg); + /* Reset processor if */ + /* configuration changed. */ __asm__ __volatile__ ("sync; isync"); mtspr(dbcr0, 0x20000000); } @@ -142,32 +240,34 @@ cpu_init_f (void) u32 val; #endif - reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); + reconfigure_pll(CFG_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#ifndef CONFIG_KAVORKA +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ -#if defined(CONFIG_SYS_GPIO0_OR) - out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */ +#if defined(CFG_GPIO0_OR) + out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ #endif -#if defined(CONFIG_SYS_GPIO0_ODR) - out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */ +#if defined(CFG_GPIO0_ODR) + out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ #endif - out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ - out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); - out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ - out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); - out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); -#if defined(CONFIG_SYS_GPIO0_ISR2H) - out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H); - out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L); + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); +#if defined(CFG_GPIO0_ISR2H) + out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H); + out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L); #endif -#if defined (CONFIG_SYS_GPIO0_TCR) - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ +#if defined (CFG_GPIO0_TCR) + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ #endif -#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */ +#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */ +#endif /* ifndef CONFIG_KAVORKA */ #if defined (CONFIG_405EP) /* @@ -181,14 +281,14 @@ cpu_init_f (void) mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ -#if defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if defined(CFG_4xx_GPIO_TABLE) gpio_set_chip_configuration(); -#endif /* CONFIG_SYS_4xx_GPIO_TABLE */ +#endif /* CFG_4xx_GPIO_TABLE */ /* * External Bus Controller (EBC) Setup */ -#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +#if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_405)) @@ -209,47 +309,47 @@ cpu_init_f (void) asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); #endif - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); + mtebc(pb0ap, CFG_EBC_PB0AP); + mtebc(pb0cr, CFG_EBC_PB0CR); #endif -#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP); - mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR); +#if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1)) + mtebc(pb1ap, CFG_EBC_PB1AP); + mtebc(pb1cr, CFG_EBC_PB1CR); #endif -#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP); - mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR); +#if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2)) + mtebc(pb2ap, CFG_EBC_PB2AP); + mtebc(pb2cr, CFG_EBC_PB2CR); #endif -#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); +#if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3)) + mtebc(pb3ap, CFG_EBC_PB3AP); + mtebc(pb3cr, CFG_EBC_PB3CR); #endif -#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP); - mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR); +#if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) + mtebc(pb4ap, CFG_EBC_PB4AP); + mtebc(pb4cr, CFG_EBC_PB4CR); #endif -#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP); - mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR); +#if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5)) + mtebc(pb5ap, CFG_EBC_PB5AP); + mtebc(pb5cr, CFG_EBC_PB5CR); #endif -#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP); - mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR); +#if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6)) + mtebc(pb6ap, CFG_EBC_PB6AP); + mtebc(pb6cr, CFG_EBC_PB6CR); #endif -#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP); - mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR); +#if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7)) + mtebc(pb7ap, CFG_EBC_PB7AP); + mtebc(pb7cr, CFG_EBC_PB7CR); #endif -#if defined (CONFIG_SYS_EBC_CFG) - mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG); +#if defined (CFG_EBC_CFG) + mtebc(EBC0_CFG, CFG_EBC_CFG); #endif #if defined(CONFIG_WATCHDOG) @@ -261,9 +361,9 @@ cpu_init_f (void) #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif -#if defined(CONFIG_SYS_4xx_RESET_TYPE) +#if defined(CFG_4xx_RESET_TYPE) val &= ~0x30000000; /* clear WRC bits */ - val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ + val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif mtspr(tcr, val); @@ -321,10 +421,34 @@ cpu_init_f (void) */ int cpu_init_r (void) { +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) + bd_t *bd = gd->bd; + unsigned long reg; #if defined(CONFIG_405GP) uint pvr = get_pvr(); +#endif /* + * Write Ethernetaddress into on-chip register + */ + reg = 0x00000000; + reg |= bd->bi_enetaddr[0]; /* set high address */ + reg = reg << 8; + reg |= bd->bi_enetaddr[1]; + out32 (EMAC_IAH, reg); + + reg = 0x00000000; + reg |= bd->bi_enetaddr[2]; /* set low address */ + reg = reg << 8; + reg |= bd->bi_enetaddr[3]; + reg = reg << 8; + reg |= bd->bi_enetaddr[4]; + reg = reg << 8; + reg |= bd->bi_enetaddr[5]; + out32 (EMAC_IAL, reg); + +#if defined(CONFIG_405GP) + /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. */ @@ -332,6 +456,7 @@ int cpu_init_r (void) mtdcr(ecr, 0x60606000); } #endif /* defined(CONFIG_405GP) */ +#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ - return 0; + return (0); } diff --git a/a/u-boot-2009.06/cpu/ppc4xx/speed.c b/b/u-boot-2009.06/cpu/ppc4xx/speed.c old mode 100644 new mode 100755 index ed6e55b..d21bd82 --- a/a/u-boot-2009.06/cpu/ppc4xx/speed.c +++ b/b/u-boot-2009.06/cpu/ppc4xx/speed.c @@ -148,7 +148,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO * to make sure it is within the proper range. * spec: VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV - * Note freqVCO is calculated in MHz to avoid errors introduced by rounding. + * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding. */ if (sysInfo->pllFwdDiv == 1) { sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;

2 1

[U-Boot] [PATCH] ppc440SPe: PCIe PLL lock error
by Rupjyoti Sarmah 24 Jul '09

24 Jul '09

u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of PLL lock. This fix touches only one file 4xx_pcie.c Signed off by Rupjyoti Sarmah < rsarmah(a)amcc.com > from Applied Micro ------------------------------------------------------------------------ --------------------- diff --git a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c old mode 100644 new mode 100755 index 07fbb0e..ce95abc --- a/a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c +++ b/b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c @@ -369,33 +369,40 @@ static int check_error(void) */ int ppc4xx_init_pcie(void) { - int time_out = 20; + int time_out = 20; /* PCIe PLL lock retry count */ /* Set PLL clock receiver to LVPECL */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); if (check_error()) + { + printf("ERROR: ppc4xx_init_pcie(): PCIe setting reference clock receiver failed: PESDR0_PLLLCT1 = (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT1)); return -1; + } + /* Did resistance calibration work? */ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) { - printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", + printf("ERROR: ppc4xx_init_pcie(): PCIe resistance calibration failed (bit 15=0): PESDR0_PLLLCT2 = (0x%08x)\n", SDR_READ(PESDR0_PLLLCT2)); return -1; } - /* De-assert reset of PCIe PLL, wait for lock */ + + /* Take PCIe PLL out of reset, wait for lock */ SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); - udelay(3); + udelay(300); /* 300 uS is maximum time lock should take, per 440SPe user's manual */ while (time_out) { - if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { /* Read PLL lock status register PLLLCTS in user's manual */ time_out--; - udelay(1); + udelay(20); /* Wait 20 uS more if needed */ } else break; } if (!time_out) { - printf("PCIE: VCO output not locked\n"); + printf("ERROR: ppc4xx_init_pcie(): PCIe - PCIe PLL VCO output not locked to reference clock (bit 3=0): PESDR0_PLLLCTS = (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT3)); return -1; } return 0; @@ -1169,3 +1176,4 @@ int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) return 0; } #endif /* CONFIG_440SPE && CONFIG_PCI */ +

2 1

Re: [U-Boot] kirkwood openRD-base / PCI support
by Dieter Kiermaier 24 Jul '09

24 Jul '09

Am Freitag 24 Juli 2009 05:59:41 schrieb Prafulla Wadaskar: > > > -----Original Message----- > > From: Dieter Kiermaier [mailto:dk-arm-linux@gmx.de] > > Sent: Thursday, July 23, 2009 6:25 PM > > To: u-boot(a)lists.denx.de > > Cc: Prafulla Wadaskar; Simon Kagstrom > > Subject: kirkwood openRD-base / PCI support > > > > Hi Prafulla, hi list, > > > > is there anywhere pci support available for u-boot on > > openrd-base board? > > I've googled and searched the list archive but aren't > > sucessful :-( It looks like there is no PCI support until > > now, Are there any plans to do this from marvell side? > > > > I use Simons patches for initial openrd-base support and try > > to get up kirkwoods PCI port. > > u-boot without PCI is running fine on my openrd-base board. > > Dear Dieter > PCIe port on Kirkwood SOC can be enabled in the u-boot by defining CONFIG_KIRKWOOD_PCIE_INIT in board configuration header file. > This enables PCIe interface to work from kernel, > I have tested it for MV88F6281GTW_GE board. > > Apart from this there is no PCIe support yet enabled in u-boot for kirkwood at this moment > Mmh, so I fear I have to wait a while. I've enabled CONFIG_KIRKWOOD_PCIE_INIT allready. And also written an empty #ifdef CONFIG_KIRKWOOD_PCIE_INIT void pci_init_board() { printf("kirkwood: pci_init_board() called\n"); } #endif /* CONFIG_KIRKWOOD_PCIE_IN */ #endif in cpu.c The function is called on bootup - nice. But if I try pci 0 on the u-boot prompt it gives me Marvell>> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ pci_bus_to_hose() failed pci_bus_to_hose() failed pci_bus_to_hose() failed pci_bus_to_hose() failed pci_bus_to_hose() failed pci_bus_to_hose() failed ... What is not really suprisingly. but then I was a bit confused what else is needed ;-) It looks like I have to learn about some basic PCI frameworks inside u-boot first. Also there are a few other tasks on my desk which have to be done first so I stopped working on it for the moment. But nevertheless, if there are any news regarding PCIe it would be nice if you could keep me up to date! Dieter > Regards.. > Prafulla . . > > > > > Many thanks, > > Dieter > > > > > > > >

1 0

[U-Boot] Support for Calao USB A9263 board based on AT91SAM9263 CPU
by Thomas Petazzoni 24 Jul '09

24 Jul '09

Hello, Here is a patch that adds the support for the Calao USB A9263 board. This is my first board support contribution to U-Boot, so don't hesitate to comment and suggest improvements. Thanks, Thomas --- Support for the Calao USB A9263 board The Calao USB A9263 board is a board manufactured and sold by Calao Systems <http://www.calao-systems.com>. Its components are very similar to the AT91SAM9263EK board, so its configuration is based on the configuration of this board. There are however some differences: different clocks, no LCD, etc. Signed-off-by: Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> MAKEALL | 1 Makefile | 3 board/usb-a9263/Makefile | 56 +++++++++++++ board/usb-a9263/config.mk | 1 board/usb-a9263/led.c | 44 ++++++++++ board/usb-a9263/partition.c | 37 ++++++++ board/usb-a9263/usb-a9263.c | 189 ++++++++++++++++++++++++++++++++++++++++++++ include/configs/usb-a9263.h | 188 +++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 519 insertions(+) diff --git a/MAKEALL b/MAKEALL index f4599d6..6581427 100755 --- a/MAKEALL +++ b/MAKEALL @@ -590,6 +590,7 @@ LIST_at91=" \ mp2usb \ m501sk \ pm9263 \ + usb-a9263 \ " ######################################################################### diff --git a/Makefile b/Makefile index bcc81c9..176885f 100644 --- a/Makefile +++ b/Makefile @@ -2785,6 +2785,9 @@ at91sam9rlek_config : unconfig pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 +usb_a9263_config : unconfig + $(MKCONFIG) -a usb-a9263 arm arm926ejs usb-a9263 NULL at91 + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/usb-a9263/Makefile b/board/usb-a9263/Makefile new file mode 100644 index 0000000..18325e0 --- /dev/null +++ b/board/usb-a9263/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += usb-a9263.o +COBJS-y += led.o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/usb-a9263/config.mk b/board/usb-a9263/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/usb-a9263/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/usb-a9263/led.c b/board/usb-a9263/led.c new file mode 100644 index 0000000..82c5388 --- /dev/null +++ b/board/usb-a9263/led.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); +} diff --git a/board/usb-a9263/partition.c b/board/usb-a9263/partition.c new file mode 100644 index 0000000..94ec265 --- /dev/null +++ b/board/usb-a9263/partition.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf(a)atmel.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/board/usb-a9263/usb-a9263.c b/board/usb-a9263/usb-a9263.c new file mode 100644 index 0000000..0f00e82 --- /dev/null +++ b/board/usb-a9263/usb-a9263.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of USB-A9263-Board */ + gd->bd->bi_arch_number = MACH_TYPE_USB_A9263; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/include/configs/usb-a9263.h b/include/configs/usb-a9263.h new file mode 100644 index 0000000..6bf6c8f --- /dev/null +++ b/include/configs/usb-a9263.h @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> + * + * Configuration settings for the Calao USB-A9263 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9263" +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_CALAO_USB_A9263 1 /* on an Calao USB A 9263 Board */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#undef CONFIG_LCD + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ +#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ +#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1c << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB_SEARCH_PHY 1 +#define CONFIG_ETHADDR 00:0D:00:0D:00:AB + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:2m(kernel)ro,-(root) "\ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- Thomas Petazzoni, Free Electrons Kernel, drivers and embedded Linux development, consulting, training and support. http://free-electrons.com

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[U-Boot] DaVinci serial bug with ns16550.c
by Andrew Dyer 24 Jul '09

24 Jul '09

We noticed in the TI distribution of u-boot (1.2.0) that if you point the u-boot ns16550.c serial driver at a UART other than uart0, it doesn't work. We believe the issue also exists in the current version. The root problem is that the MDR1 register in the UART defaults to disabled. We believe the RBL (rom boot loader) in the part initializes this register as part of it's startup for UART0, but running on one of the other uarts, it doesn't get initialized. There are #ifdefs to take care of this condition for OMAP, but not DaVinci. See lines 20-22 and 33-39 below (taken from the gitweb view of the u-boot tree). In particular we are using DM6467, but I'm guessing this would be applicable to others in the family. Sorry I don't have a patch for git - we are only working with the TI version for now. 17 void NS16550_init (NS16550_t com_port, int baud_divisor) 18 { 19 com_port->ier = 0x00; 20 #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) 21 com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ 22 #endif 23 com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; 24 com_port->dll = 0; 25 com_port->dlm = 0; 26 com_port->lcr = UART_LCRVAL; 27 com_port->mcr = UART_MCRVAL; 28 com_port->fcr = UART_FCRVAL; 29 com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; 30 com_port->dll = baud_divisor & 0xff; 31 com_port->dlm = (baud_divisor >> 8) & 0xff; 32 com_port->lcr = UART_LCRVAL; 33 #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) 34 #if defined(CONFIG_APTIX) 35 com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ 36 #else 37 com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ 38 #endif 39 #endif /* CONFIG_OMAP */ 40 }

1 0

[U-Boot] arm: pRAM support?
by Andreas Huber 24 Jul '09

24 Jul '09

Hello, We are using the pRAM feature (CONFIG_PRAM) on the PPC architecture. As we are switching to an ARM architecture (Kirkwood) I am wondering if there is an equivalent U-Boot feature for this (CONFIG_PRAM did not work). /Andreas

5 5

[U-Boot] [PATCH 1/2] arm nomadik: add gpio support
by Alessandro Rubini 24 Jul '09

24 Jul '09

From: Alessandro Rubini <rubini(a)unipv.it> Signed-off-by: Alessandro Rubini <rubini(a)unipv.it> Acked-by: Andrea Gallo <andrea.gallo(a)stericsson.com> --- board/st/nhk8815/Makefile | 2 +- board/st/nhk8815/gpio.c | 99 +++++++++++++++++++++++++++++++++++++++++++++ board/st/nhk8815/gpio.h | 42 +++++++++++++++++++ 3 files changed, 142 insertions(+), 1 deletions(-) create mode 100644 board/st/nhk8815/gpio.c create mode 100644 board/st/nhk8815/gpio.h diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile index b37fe53..80a1ab6 100644 --- a/board/st/nhk8815/Makefile +++ b/board/st/nhk8815/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := nhk8815.o +COBJS := nhk8815.o gpio.o SOBJS := platform.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/st/nhk8815/gpio.c b/board/st/nhk8815/gpio.c new file mode 100644 index 0000000..e0857b6 --- /dev/null +++ b/board/st/nhk8815/gpio.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "gpio.h" + +static unsigned long gpio_base[4] = { + NOMADIK_GPIO0_BASE, + NOMADIK_GPIO1_BASE, + NOMADIK_GPIO2_BASE, + NOMADIK_GPIO3_BASE +}; + +enum gpio_registers { + GPIO_DAT = 0x00, /* data register */ + GPIO_DATS = 0x04, /* data set */ + GPIO_DATC = 0x08, /* data clear */ + GPIO_PDIS = 0x0c, /* pull disable */ + GPIO_DIR = 0x10, /* direction */ + GPIO_DIRS = 0x14, /* direction set */ + GPIO_DIRC = 0x18, /* direction clear */ + GPIO_AFSLA = 0x20, /* alternate function select A */ + GPIO_AFSLB = 0x24, /* alternate function select B */ +}; + +static inline unsigned long gpio_to_base(int gpio) +{ + return gpio_base[gpio / 32]; +} + +static inline u32 gpio_to_bit(int gpio) +{ + return 1 << (gpio & 0x1f); +} + +void nmk_gpio_af(int gpio, int alternate_function) +{ + unsigned long base = gpio_to_base(gpio); + u32 bit = gpio_to_bit(gpio); + u32 afunc, bfunc; + + /* alternate function is 0..3, with one bit per register */ + afunc = readl(base + GPIO_AFSLA) & ~bit; + bfunc = readl(base + GPIO_AFSLB) & ~bit; + if (alternate_function & 1) afunc |= bit; + if (alternate_function & 2) bfunc |= bit; + writel(afunc, base + GPIO_AFSLA); + writel(bfunc, base + GPIO_AFSLB); +} + +void nmk_gpio_dir(int gpio, int dir) +{ + unsigned long base = gpio_to_base(gpio); + u32 bit = gpio_to_bit(gpio); + + if (dir) + writel(bit, base + GPIO_DIRS); + else + writel(bit, base + GPIO_DIRC); +} + +void nmk_gpio_set(int gpio, int val) +{ + unsigned long base = gpio_to_base(gpio); + u32 bit = gpio_to_bit(gpio); + + if (val) + writel(bit, base + GPIO_DATS); + else + writel(bit, base + GPIO_DATC); +} + +int nmk_gpio_get(int gpio) +{ + unsigned long base = gpio_to_base(gpio); + u32 bit = gpio_to_bit(gpio); + + return readl(base + GPIO_DAT) & bit; +} diff --git a/board/st/nhk8815/gpio.h b/board/st/nhk8815/gpio.h new file mode 100644 index 0000000..1d3c9ce --- /dev/null +++ b/board/st/nhk8815/gpio.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __NMK_GPIO_H__ +#define __NMK_GPIO_H__ + +/* + * These functions are called from the soft-i2c driver, but + * are also used by board files to set output bits. + */ + +enum nmk_af { /* alternate function settings */ + GPIO_GPIO = 0, + GPIO_ALT_A, + GPIO_ALT_B, + GPIO_ALT_C +}; + +extern void nmk_gpio_af(int gpio, int alternate_function); +extern void nmk_gpio_dir(int gpio, int dir); +extern void nmk_gpio_set(int gpio, int val); +extern int nmk_gpio_get(int gpio); + +#endif /* __NMK_GPIO_H__ */ -- 1.6.0.2

2 1

[U-Boot] unable to see jffs2 partition
by E Robertson 23 Jul '09

23 Jul '09

Hi all, I've been trying unsuccessfully to see my jffs2 partition I've created by the mtdtools under linux. If their a known issue with this? Is their a size limit? Maybe the way it's created? I do not have a problem with this partition from linux but also never looked at it from the u-boot. I can change partitions but "ls" shows partition is empty when their are files. ... #define CONFIG_CMD_JFFS2 1 /** JFFS2 Support */ #define CONFIG_CMD_MTDPARTS 1 #define CONFIG_JFFS2_CMDLINE 1 #undef CONFIG_CMD_FLASH #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" #define CONFIG_JFFS2_PART_OFFSET 0x0 #define CONFIG_JFFS2_PART_SIZE 0x5000000 #define MTDPARTS_DEFAULT "mtdparts=nand:80M(IMGS),-(DATA)" #define MTDIDS_DEFAULT "nand0=nand" ... Thanks, E!

1 1