July 2009 - U-Boot

[U-Boot] MPC8541 - Ethernet on FCC
by Alemao 30 Jul '09

30 Jul '09

Hi all, My MPC8541 board has 4 ethernet ports, 2 TSEC's e 2 FCC's. Each one is connected to a PHY, and all PHY's are connected to the MDIO bus. For TSEC's, PHY address is defined with: #define TSEC1_PHY_ADDR 4 #define TSEC1_PHY_ADDR 2 But I didn't find where to set FCC PHY address. Is it not needed? In almost all boards thats use ethernet FCC, I saw the flag FCC_PSMR_LPB seted: #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) Why loopback is seted by default? Cheers, -- Alemao

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[U-Boot] [PATCH] ppc4xx: Remove check for PPC460EX from CompactCenter
by Dirk Eibach 30 Jul '09

30 Jul '09

Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- board/gdsys/compactcenter/compactcenter.c | 26 +++++++++----------------- 1 files changed, 9 insertions(+), 17 deletions(-) diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/compactcenter/compactcenter.c index 477ef70..f448ef9 100644 --- a/board/gdsys/compactcenter/compactcenter.c +++ b/board/gdsys/compactcenter/compactcenter.c @@ -41,8 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - u32 pvr = get_pvr(); - /* * Setup the interrupt controller polarities, triggers, etc. */ @@ -95,16 +93,14 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) { - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - } + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); /* Trigger board component reset */ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); @@ -250,7 +246,6 @@ int misc_init_r(void) { u32 sdr0_srst1 = 0; u32 eth_cfg; - u32 pvr = get_pvr(); /* * Set EMAC mode/configuration (GMII, SGMII, RGMII...). @@ -264,10 +259,7 @@ int misc_init_r(void) /* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - else - eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; + eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; mtsdr(SDR0_ETH_CFG, eth_cfg); /* -- 1.5.6.5

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[U-Boot] [PATCH v2] ppc4xx: amcc: Set CONFIG_SYS_BOOTMAPSZ to 16MB for big kernels
by Stefan Roese 30 Jul '09

30 Jul '09

This patch changes CONFIG_SYS_BOOTMAPSZ from 8MB to 16MB which is the initial TLB on 40x PPC's in the Linux kernel. With this change even bigger Linux kernels (> 8MB) can be booted. This patch also sets CONFIG_SYS_BOOTM_LEN to 16MB (default 8MB) to enable decompression of bigger images. Signed-off-by: Stefan Roese <sr(a)denx.de> --- This patch replaces the orinal patch "[PATCH v2] ppc4xx: amcc: Set CONFIG_SYS_BOOTMAPSZ to 16MB to enable booting of big kernels". v2: - Patch subject line now a bit shorter - Increase CONFIG_SYS_BOOTM_LEN to 16MB too include/configs/amcc-common.h | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 3b733c0..275adcc 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -137,10 +137,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ /* * Internal Definitions -- 1.6.3.4

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[U-Boot] [PATCH] ppc4xx: Add support for PPC460EX/460GT rev B chip to AMCC Canyonlands
by Stefan Roese 30 Jul '09

30 Jul '09

This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo(a)amcc.com> Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/canyonlands/canyonlands.c | 26 +++++++++++++++++--------- 1 files changed, 17 insertions(+), 9 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 5071c8d..710a0af 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -94,13 +94,23 @@ static inline void board_cpld_write(int offset, int data) out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); out_8((void *)(CONFIG_SYS_CPLD_DATA), data); } +#else +static int pvr_460ex(void) +{ + u32 pvr = get_pvr(); + + if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) || + (pvr == PVR_460EX_RB)) + return 1; + + return 0; +} #endif /* defined(CONFIG_ARCHES) */ int board_early_init_f(void) { #if !defined(CONFIG_ARCHES) u32 sdr0_cust0; - u32 pvr = get_pvr(); #endif /* @@ -175,7 +185,7 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) { + if (pvr_460ex()) { /* * Configure USB-STP pins as alternate and not GPIO * It seems to be neccessary to configure the STP pins as GPIO @@ -234,17 +244,16 @@ int get_cpu_num(void) int checkboard(void) { char *s = getenv("serial#"); - u32 pvr = get_pvr(); - if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) { - printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); - gd->board_type = BOARD_GLACIER; - } else { + if (pvr_460ex()) { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) gd->board_type = BOARD_CANYONLANDS_PCIE; else gd->board_type = BOARD_CANYONLANDS_SATA; + } else { + printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); + gd->board_type = BOARD_GLACIER; } switch (gd->board_type) { @@ -498,7 +507,6 @@ int misc_init_r(void) { u32 sdr0_srst1 = 0; u32 eth_cfg; - u32 pvr = get_pvr(); u8 val; /* @@ -513,7 +521,7 @@ int misc_init_r(void) /* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) + if (pvr_460ex()) eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; else eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; -- 1.6.3.4

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[U-Boot] [PATCH] ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips
by Stefan Roese 30 Jul '09

30 Jul '09

This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo(a)amcc.com> Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/cpu.c | 23 +++++++++++++++++++++++ include/asm-ppc/processor.h | 2 ++ include/ppc440.h | 5 +++++ 3 files changed, 30 insertions(+), 0 deletions(-) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index e12a784..e9861ab 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -285,6 +285,9 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 reg; +#endif #if !defined(CONFIG_IOP480) char addstr[64] = ""; @@ -526,6 +529,7 @@ int checkcpu (void) strcpy(addstr, "No RAID 6 support"); break; +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) case PVR_460EX_RA: puts("EX Rev. A"); strcpy(addstr, "No Security/Kasumi support"); @@ -536,6 +540,15 @@ int checkcpu (void) strcpy(addstr, "Security/Kasumi support"); break; + case PVR_460EX_RB: + puts("EX Rev. B"); + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00100000) + strcpy(addstr, "No Security/Kasumi support"); + else + strcpy(addstr, "Security/Kasumi support"); + break; + case PVR_460GT_RA: puts("GT Rev. A"); strcpy(addstr, "No Security/Kasumi support"); @@ -546,6 +559,16 @@ int checkcpu (void) strcpy(addstr, "Security/Kasumi support"); break; + case PVR_460GT_RB: + puts("GT Rev. B"); + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00100000) + strcpy(addstr, "No Security/Kasumi support"); + else + strcpy(addstr, "Security/Kasumi support"); + break; +#endif + case PVR_460SX_RA: puts("SX Rev. A"); strcpy(addstr, "Security support"); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2c0c0ce..2841104 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -883,8 +883,10 @@ #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ diff --git a/include/ppc440.h b/include/ppc440.h index 6ce53a6..e6dc740 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1156,6 +1156,11 @@ #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 + /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ #define SDR0_ETH_PLL 0x4102 #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ -- 1.6.3.4

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[U-Boot] [PATCH] ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM's
by Stefan Roese 30 Jul '09

30 Jul '09

Some Canyonlands boards are equipped with different SODIMM's. This is no problem with the "normal" NOR booting Canyonlands U-Boot, since it automatically detects the SODIMM's via SPD data and correctly configures them. But the NAND booting version is different. Here we only have 4k of image size to completely setup the hardware, including DDR2 setup. So we need to use a fixed DDR2 setup here. This doesn't work for different SODIMM's right now. Currently only this Crucial SODIMM is support: CT6464AC667.8FB (dual ranked) Now some boards are shipped with this SODIMM: CT6464AC667.4FE (single ranked) This patch now supports both SODIMM's by configuring first for the dual ranked DIMM. A quick shows, if this module is really installed. If this test fails, the DDR2 controller is re-configured for the single ranked SODIMM. Tested with those SODIMM's: CT6464AC667.8FB (dual ranked) CT6464AC667.4FE (single ranked) Signed-off-by: Stefan Roese <sr(a)denx.de> --- nand_spl/board/amcc/canyonlands/ddr2_fixed.c | 79 +++++++++++++++++++++----- 1 files changed, 65 insertions(+), 14 deletions(-) diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c index 371bbb3..ed1888c 100644 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,17 @@ #include <asm/io.h> #include <asm/processor.h> +/* + * This code can configure those two Crucial SODIMM's: + * + * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) + * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) + * + */ + +#define TEST_ADDR 0x10000000 +#define TEST_MAGIC 0x11223344 + static void wait_init_complete(void) { u32 val; @@ -35,7 +46,13 @@ static void wait_init_complete(void) } while (!(val & 0x80000000)); } -phys_size_t initdram(int board_type) +static void ddr_start(void) +{ + mtsdram(SDRAM_MCOPT2, 0x28000000); + wait_init_complete(); +} + +static void ddr_init_common(void) { /* * Reset the DDR-SDRAM controller. @@ -49,17 +66,12 @@ phys_size_t initdram(int board_type) * enabled. This will only work for the same memory * configuration as used here: * - * Crucial CT6464AC667.8FB - 512MB SO-DIMM - * */ mtsdram(SDRAM_MCOPT2, 0x00000000); - mtsdram(SDRAM_MCOPT1, 0x05122000); mtsdram(SDRAM_MODT0, 0x01000000); - mtsdram(SDRAM_CODT, 0x02800021); mtsdram(SDRAM_WRDTR, 0x82000823); mtsdram(SDRAM_CLKTR, 0x40000000); mtsdram(SDRAM_MB0CF, 0x00000201); - mtsdram(SDRAM_MB1CF, 0x00000201); mtsdram(SDRAM_RTR, 0x06180000); mtsdram(SDRAM_SDTR1, 0x80201000); mtsdram(SDRAM_SDTR2, 0x42103243); @@ -82,17 +94,56 @@ phys_size_t initdram(int board_type) mtsdram(SDRAM_INITPLR13, 0x80810040); mtsdram(SDRAM_INITPLR14, 0x00000000); mtsdram(SDRAM_INITPLR15, 0x00000000); - - mtsdram(SDRAM_MCOPT2, 0x28000000); - - wait_init_complete(); + mtsdram(SDRAM_RDCC, 0x40000000); + mtsdram(SDRAM_RQDC, 0x80000038); + mtsdram(SDRAM_RFDC, 0x00000257); mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */ +} - mtsdram(SDRAM_RDCC, 0x40000000); - mtsdram(SDRAM_RQDC, 0x80000038); - mtsdram(SDRAM_RFDC, 0x00000257); +phys_size_t initdram(int board_type) +{ + /* + * First try init for this module: + * + * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) + */ + + ddr_init_common(); + + /* + * Crucial CT6464AC667.8FB - 512MB SO-DIMM + */ + mtdcr(SDRAM_R0BAS, 0x0000F800); + mtdcr(SDRAM_R1BAS, 0x0400F800); + mtsdram(SDRAM_MCOPT1, 0x05122000); + mtsdram(SDRAM_CODT, 0x02800021); + mtsdram(SDRAM_MB1CF, 0x00000201); + + ddr_start(); + + /* + * Now test if the dual-ranked module is really installed + * by checking an address in the upper 256MByte region + */ + out_be32((void *)TEST_ADDR, TEST_MAGIC); + if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) { + /* + * The test failed, so we assume that the single + * ranked module is installed: + * + * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) + */ + + ddr_init_common(); + + mtdcr(SDRAM_R0BAS, 0x0000F000); + mtsdram(SDRAM_MCOPT1, 0x05322000); + mtsdram(SDRAM_CODT, 0x00800021); + + ddr_start(); + } return CONFIG_SYS_MBYTES_SDRAM << 20; } -- 1.6.3.4

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[U-Boot] [PATCH] ppc4xx: amcc: Move "kernel_addr_r" etc to higher locations (> 16MB)
by Stefan Roese 30 Jul '09

30 Jul '09

This patch moves the load addresses for kernel, fdt and ramdisk to higher addresses (>= 16MB). This enables booting of bigger kernel images (e.g. lockdep enabled). Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/amcc-common.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index e82b5ed..70b2d3d 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -214,9 +214,9 @@ " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \ CONFIG_ADDMISC \ "initrd_high=30000000\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=800000\0" \ - "ramdisk_addr_r=C00000\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr_r=1800000\0" \ + "ramdisk_addr_r=1900000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \ -- 1.6.3.4

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[U-Boot] U-boot hangs in MPC82xx
by GurumurthyGowdar 30 Jul '09

30 Jul '09

hello heiko, sorry this is our custom board. not the mainline board. Regards, Gurumurthy

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[U-Boot] Test
by Tuma 30 Jul '09

30 Jul '09

Test Message. -- Software Developer General Satellite Corp.

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Re: [U-Boot] U-boot hangs in mtest in MPC8280 Board
by GurumurthyGowdar 30 Jul '09

30 Jul '09

On Thu, 30 Jul 2009 16:14:30 +0530 wrote >Hello GurumurthyGowdar, > >GurumurthyGowdar wrote: >> On Thu, 30 Jul 2009 12:54:31 +0530 wrote >>> Hello GurumurthyGowdar, >>> >>> GurumurthyGowdar wrote: >>>> i am using MPC8280 in our board which has 512MB of SDRAM i.e. from micron. >>> Is this board in mainline, so I can look in the Source Code? >> yes this board is in mainline.only one board. > >And which board is it? means ? it is MPC8280 based board called remote I/O board >As I saw in your log, it uses the "normal" mtest. Try to use > >CONFIG_SYS_ALT_MEMTEST how to use this...where to add...command for this test?? > >instead. (Hopefully, this is available in 1.3.1 ...) > >>> Which u-boot version? >> U-boot version is 1.3.1. > >Hmm.. this is very old ... which is the latest version of u-boot ,can i upgrade the current version of u-boot to latest version i.e. from u-boot 1.3.1 to latest u-boot without reinstalling ELDK > >>> Which SDRAMs? >> SDRAM is MT48LC32M16A2 from Micron. >>>> when i give command mtest only for 1MB to check memory test from U-boot, machine check and program exception is coming after 40 - 60mins later it hangs giving program check exception >>> Hmm... maybe problems with your SDRAMs? >> if it is SDRAM problem it should not work for 1hour also i think. > >Why not? ok > >>> Is this error shown always after 40-60 mins, not sometimes also earlier? >> maximum i am able to run mtest for 1hr 30 mins. sometimes it hangs with 45mins also. > >Not earlier? sometimes earlier but rare > >Hmm... > >>> Can you boot a Linux Kernel for example? >> No. our job is to only give the board with U-boot boot loader, Linux booting is done by our client. > >But you can try it ... >This would help here, to stress more the SDRAMs ... also you >can do better memtests there/with it. i got one new error which is below :- U-Boot 1.3.1 (Jul 27 2009 - 17:27:10) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 4, 60x Bus Freq 16-50 , Core Freq 50-150 - dfbrg 1, corecnf 0x10, busdf 4, cpmdf 1, plldf 0, pllmf 4, pcidf 3 - vco_out 500000000, scc_clk 125000000, brg_clk 31250000 - cpu_clk 300000000, cpm_clk 250000000, bus_clk 100000000 CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 300 MHz Board: MPC8280 Based Remote IO CARD.SLN Technologies Pvt Ltd. I2C: ready DRAM: 512 MB FLASH: 256.5 MB *** Warning - bad CRC, using default environment NIP: 1FFE8A88 XER: 00000000 LR: 1FFE89CC REGS: 1ffa1df0 TRAP: 0700 DAR: 00000000 MSR: 00083002 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: 00729878 1FFA1EE0 EFFFFFFF 28EE0928 1FFAB424 00006BC4 1FFA201D 3D313135 GPR08: 1FFF0314 00000000 0028EE09 E6635C01 1FFA1CB0 FFF7FEFF 1FFFE000 DFFD2000 GPR16: 1FFF6E00 00000000 00000000 00000000 00003002 00000001 00000000 1FFD5098 GPR24: 1FFD57D4 01000000 1FFA1F20 00000000 1FFA2008 1FFA1F6C 1FFFEB88 1FFF715C Call backtrace: Program Check Exception U-Boot 1.3.1 (Jul 27 2009 - 17:27:10) MPC8260 Reset Status: Check Stop, External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 4, 60x Bus Freq 16-50 , Core Freq 50-150 - dfbrg 1, corecnf 0x10, busdf 4, cpmdf 1, plldf 0, pllmf 4, pcidf 3 - vco_out 500000000, scc_clk 125000000, brg_clk 31250000 - cpu_clk 300000000, cpm_clk 250000000, bus_clk 100000000 CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 300 MHz Board: MPC8280 Based Remote IO CARD.SLN Technologies Pvt Ltd. I2C: ready DRAM: 512 MB FLASH: Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. Caused by (from msr): Machine check in kernel mode. it hangs here only....if i do manual hardware reset it hangs in DRAM : 512MB as below U-Boot 1.3.1 (Jul 27 2009 - 17:27:10) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 4, 60x Bus Freq 16-50 , Core Freq 50-150 - dfbrg 1, corecnf 0x10, busdf 4, cpmdf 1, plldf 0, pllmf 4, pcidf 3 - vco_out 500000000, scc_clk 125000000, brg_clk 31250000 - cpu_clk 300000000, cpm_clk 250000000, bus_clk 100000000 CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 300 MHz Board: MPC8280 Based Remote IO CARD.SLN Technologies Pvt Ltd. I2C: ready DRAM: 512 MB it hangs here only if i press manual hardware reset many times also. if i power off & switch on then it reboots in normal way again. > >>>> i have checked the SDRAM configuration settings everything is fine as per the device datasheet. >>>> >>>> please i want to know where is the problem, what is the cause for this exception. why memory test fails after 40-60mins. >>>> >>>> error output is as attached:- >>>> >>>> MPC8260 Reset Status: Check Stop, External Soft, External Hard >>>> >>>> MPC8260 Clock Configuration >>>> - Bus-to-Core Mult 5x, VCO Div 2, 60x Bus Freq 20-60 , Core Freq 100-300 >>>> - dfbrg 1, corecnf 0x1b, busdf 7, cpmdf 1, plldf 0, pllmf 7, pcidf 3 >>>> - vco_out 528000000, scc_clk 132000000, brg_clk 33000000 >>>> - cpu_clk 330000000, cpm_clk 264000000, bus_clk 66000000 >>>> >>>> CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 330 MHz >>>> Board: MPC8280 Based Remote IO CARD.SLN Technologies Pvt Ltd. >>>> I2C: ready >>>> DRAM: 512 MB >>>> FLASH: 256.5 MB > >If this is one chip, are there really 256,5 MB ? > >>>> *** Warning - bad CRC, using default environment >>>> >>>> NIP: 1FFE8A30 XER: 00000000 LR: 1FFE899CC REGS: 1ffa1df0 TRAP: 0700 DAR: 00000000 >>>> MSR: 00083002 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 >>>> >>>> GPR00: 446BA781 1FFA1EE0 EFFFFFFF 3A858DD6 1FFA9F3C 000080C4 1FFA201D 3D313135 >>>> GPR08: 1FFF0314 NIP: 1FFE9648 XER: 20000000 LR: 1FFE93DC REGS: 1ffa1a68 TRAP: 0700 DAR: 00000000 >>>> MSR: 00083002 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 >>>> >>>> GPR00: 00000030 1FFA1B58 EFFFFFFF 1FFA1C1C 00000000 00000010 FFFFFFFF 00000030 >>>> GPR08: 00000041 00000000 00000000 00000002 1FFA1B60 FFF7FEFF 1FFFE000 DFFD2000 >>>> GPR16: 1FFF1240 1FFF1214 1FFF127C 1FFA1EA0 00003002 1FFA1DE0 1FFF47F8 1FFA1BD0 >>>> GPR24: 1FFA1C14 00000041 1FFF094C 00000000 1FFF47A8 1FFA1F6C 1FFF$EBBC FFFFFFFF >>>> Call backtraace: >>>> Program Check Exception >>> I cannot see here in this log, where you typed mtest ... >> >> please see the attachment in this mail.i have captured the log file from hyper terminal. > >Hmm.. I looked in the log. Is this right, that if you get this error >u-boot never returns to the shell prompt? > >Also from your log: >Pattern 0000158A Writing... Reading... >Mem error @ 0x0071E65C: found 00008F3F, expected 00008F21 > ^^ ^^ > >Pattern FFFFEA75 Writing... Reading... >Mem error @ 0x00723684: found FFFF5CB6, expected FFFF5CD4 > ^^ ^^ > always the last byte seems broken > >Is there getting something hot and the board, and maybe disturb this datalines? > >bye >Heiko >-- >DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >

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