July 2009 - U-Boot

[U-Boot] [PATCH 4/6] Poseidon Board Support
by Vivek 01 Jul '09

01 Jul '09

Added include/configs/poseidon.h file. Signed-off-by: Vivek Dalal <v.dalal(a)samsung.com> --- include/configs/poseidon.h | 293 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 293 insertions(+) diff --git a/include/configs/poseidon.h b/include/configs/poseidon.h index e69de29..d2ccbfa 100644 --- a/include/configs/poseidon.h +++ b/include/configs/poseidon.h @@ -0,0 +1,286 @@ +/* + * (C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP24XX 1 /* which is a 24XX */ +#define CONFIG_OMAP243X 1 /* which is in a 243X */ +#define CONFIG_2430 1 +#define CONFIG_POSEIDON 1 + +/* Clock config for target */ +#define PRCM_CONFIG_I 1 /* DRAM-166MHz OneNAND-83MHz*/ +#ifdef CONFIG_SYS_NOR_BOOT +#undef CONFIG_SYS_USE_NOR +#define CONFIG_SYS_USE_NOR 1 +#endif + +#define CONFIG_SYS_USE_UBI +#include <asm/arch/omap24xx.h> /* get chip and board defs */ + +#define V_SCLK 13000000 + +/* input clock of PLL */ +/* the OMAP24XX SDP has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * TFTP Dump Command support + */ + +/* + * Size of malloc() pool + */ +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_256K +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE_4K SZ_256K +/* Total Size of Environment Sector of FLEX */ +#define CONFIG_ENV_SIZE_FLEX SZ_256K + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_2M) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (DEBUG_BASE+0x300) +#define CONFIG_LAN91C96_EXT_PHY +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_NS16550_COM1 OMAP24XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on SDP */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* Config CMD*/ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ONENAND 1 + +#ifdef CONFIG_SYS_USE_UBI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#endif + +#undef CONFIG_CMD_AUTOSCRIPT + +#ifndef CONFIG_SYS_USE_NOR +# undef CONFIG_CMD_FLASH +# undef CONFIG_CMD_IMLS +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.200.11 +#define CONFIG_SERVERIP 192.168.200.1 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_ETHADDR 00:0E:99:00:24:20 + +#define CONFIG_SYS_MEM "mem=128" + +#ifdef CONFIG_SYS_USE_UBI +#define CONFIG_SYS_UBI "ubi.mtd=4" +#else +#define CONFIG_SYS_UBI "" +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \ + " console=ttyS0,115200n8" \ + " ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \ + "apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \ + CONFIG_SYS_UBI + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "Image=tftp 0x80008000 Image; go 0x80008000\0" \ + "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \ + "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \ + "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \ + "xloader=tftp 0x80180000 x-load.bin; " \ + " cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \ + "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \ + "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \ + "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \ + "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \ + "onesyncboot=run syncmode oneboot\0" \ + "updateb=tftp 0x80180000 u-boot-onenand.bin; " \ + " onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \ + "ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \ + "bootcmd=run uboot\0" + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "Poseidon # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP24XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP24XX_SDRC_CS0) + +/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) + * or by 32KHz clk, or from external sig. This rate is divided by a local + * divisor. + */ +#define V_PVT 7 /* use with 12MHz/128 */ +#define CONFIG_SYS_TIMERBASE OMAP24XX_GPT2 +#define CONFIG_SYS_PTV V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_128M +#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* Configure the PISMO - REV A Version is as follows */ +#define PISMO_CS0 PISMO_SIBLEY0 +#define PISMO_CS1 PISMO_SIBLEY1 +#define PISMO_CS2 PISMO_ONENAND +#define PROC_NOR_SIZE GPMC_SIZE_64M +#define PROC_NAND_SIZE GPMC_SIZE_64M +#define PROC_ONENAND_SIZE GPMC_SIZE_16M +#define PISMO_SIB0_SIZE GPMC_SIZE_64M +#define PISMO_SIB1_SIZE GPMC_SIZE_64M +#define PISMO_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO_PCMCIA_SIZE GPMC_SIZE_128M + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#ifdef CONFIG_SYS_USE_NOR +/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */ +# define CONFIG_SYS_FLASH_BASE 0x18000000 +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_MAX_FLASH_SECT 1024 +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* Flash memory is CFI compliant */ +# define CONFIG_SYS_FLASH_CFI 1 +# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +/* Use buffered writes (~10x faster) */ +/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ +/* Use h/w sector protection*/ +# define CONFIG_SYS_FLASH_PROTECTION 1 + +#else /* !CONFIG_SYS_USE_NOR */ +# define CONFIG_SYS_NO_FLASH 1 +#endif /* CONFIG_SYS_USE_NOR */ + + +#define CONFIG_SYS_ONENAND_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */ + +#define CONFIG_ENV_IS_IN_ONENAND 1 + +#define CONFIG_ENV_ADDR 0x00020000 +#define CONFIG_ENV_ADDR_4K 0x00040000 +#define CONFIG_ENV_ADDR_FLEX 0x00040000 + +#ifdef CONFIG_SYS_USE_UBI +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "onenand0=onenand" +#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \ + "128k(params)," \ + "2m(kernel)," \ + "16m(rootfs)," \ + "32m(fs)," \ + "-(ubifs)" +#endif + + +#endif /* __CONFIG_H */

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[U-Boot] [PATCH 2/6] Generic MacroNames and OMAP2430 Definitions
by Vivek 01 Jul '09

01 Jul '09

Made the include/asm-arm/arch-omap24xx/ generic file rather then specific to omap2420. So as to make it for family of processor of type omap24xx; Changed macros ending with OMAP2420 to OMAP24XX. Put the omap2420 specific code in CONFIG_OMAP242X macro and Poseidon Board support in CONFIG_OMAP243X macro. Changed the Apollon board and omap2420h4 board specific .c files which were affected due to the above change. Signed-off-by: Vivek Dalal <v.dalal(a)samsung.com> --- board/apollon/apollon.c | 4 board/apollon/lowlevel_init.S | 4 board/apollon/mem.c | 10 board/omap2420h4/mem.c | 10 board/omap2420h4/omap2420h4.c | 7 include/asm-arm/arch-omap24xx/clocks.h | 202 +++++++++++++++ include/asm-arm/arch-omap24xx/i2c.h | 5 include/asm-arm/arch-omap24xx/mem.h | 107 ++++++++ include/asm-arm/arch-omap24xx/omap24xx.h | 399 ++++++++++++++++++++---------- include/asm-arm/arch-omap24xx/sys_info.h | 10 include/configs/apollon.h | 18 - include/configs/omap2420h4.h | 76 +++-- onenand_ipl/board/apollon/low_levelinit.S | 2 13 files changed, 674 insertions(+), 180 deletions(-) diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 30d8e31..5588a0e 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -68,7 +68,7 @@ int board_init(void) gd->bd->bi_arch_number = 919; /* adress of boot parameters */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100); + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); return 0; } @@ -147,7 +147,7 @@ void ether_init(void) #ifdef CONFIG_DRIVER_LAN91C96 int cnt = 20; - __raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */ + __raw_writeb(0x03, OMAP24XX_CTRL_BASE + 0x0f2); /*protect->gpio74 */ __raw_writew(0x0, LAN_RESET_REGISTER); do { diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S index d2d9025..c6450e1 100644 --- a/board/apollon/lowlevel_init.S +++ b/board/apollon/lowlevel_init.S @@ -178,7 +178,7 @@ copy_loop: #endif prcm_setup: - ldr r0, =OMAP2420_CM_BASE + ldr r0, =OMAP24XX_CM_BASE ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ bic r1, r1, #0x03 orr r1, r1, #0x02 @@ -212,7 +212,7 @@ prcm_setup: #endif str r2, [r1] - ldr r0, =OMAP2420_CM_BASE + ldr r0, =OMAP24XX_CM_BASE ldr r1, [r0, #0x084] and r1, r1, #0x01 cmp r1, #0x01 diff --git a/board/apollon/mem.c b/board/apollon/mem.c index e56b005..f4f36aa 100644 --- a/board/apollon/mem.c +++ b/board/apollon/mem.c @@ -82,14 +82,14 @@ u32 mem_ok(void) u32 pattern = 0x12345678; /* clear pos A */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); + __raw_writel(0x0, OMAP24XX_SDRC_CS0 + 0x400); /* pattern to pos B */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); + __raw_writel(pattern, OMAP24XX_SDRC_CS0); /* remove pattern off the bus */ - __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); + __raw_writel(0x0, OMAP24XX_SDRC_CS0 + 4); /* get pos A value */ - val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + val1 = __raw_readl(OMAP24XX_SDRC_CS0 + 0x400); + val2 = __raw_readl(OMAP24XX_SDRC_CS0); /* get val2 */ /* see if pos A value changed */ if ((val1 != 0) || (val2 != pattern)) diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index 719888f..359a6c0 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -123,11 +123,11 @@ u32 mem_ok(void) u32 val1, val2; u32 pattern = 0x12345678; - __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ - __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ - val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + __raw_writel(0x0, OMAP24XX_SDRC_CS0+0x400); /* clear pos A */ + __raw_writel(pattern, OMAP24XX_SDRC_CS0); /* pattern to pos B */ + __raw_writel(0x0, OMAP24XX_SDRC_CS0+4); /* remove pattern off the bus */ + val1 = __raw_readl(OMAP24XX_SDRC_CS0+0x400); /* get pos A value */ + val2 = __raw_readl(OMAP24XX_SDRC_CS0); /* get val2 */ if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ return(0); diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index d3dc5f3..38cb0a8 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -59,7 +59,8 @@ int board_init (void) gpmc_init(); /* in SRAM or SDRM, finish GPMC */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ + /* address of boot parameters */ + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0+0x100); return 0; } @@ -159,7 +160,7 @@ void ether_init (void) #ifdef CONFIG_DRIVER_LAN91C96 int cnt = 20; - __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ + __raw_writeb(0x3, OMAP24XX_CTRL_BASE+0x10a); /*protect->gpio95 */ __raw_writew(0x0, LAN_RESET_REGISTER); do { @@ -738,7 +739,7 @@ void muxSetupSDRC(void) *****************************************************************************/ void update_mux(u32 btype,u32 mtype) { - u32 cpu, base = OMAP2420_CTRL_BASE; + u32 cpu, base = OMAP24XX_CTRL_BASE; cpu = get_cpu_type(); if (btype == BOARD_H4_MENELAUS) { diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h index 2e92569..7d47959 100644 --- a/include/asm-arm/arch-omap24xx/clocks.h +++ b/include/asm-arm/arch-omap24xx/clocks.h @@ -31,6 +31,8 @@ #define DPLL_LOCK 0x3 /* DPLL lock */ #endif +#if defined(CONFIG_OMAP242X) + /****************************************************************************; ; PRCM Scheme II ; @@ -109,4 +111,204 @@ /* lock delay time out */ #define LDELAY 12000000 +#elif defined(CONFIG_OMAP243X) + +/* cm_clksel core fields not ratio governed */ +#define RX_CLKSEL_DSS1 (0x10 << 8) +#define RX_CLKSEL_DSS2 (0x0 << 13) +#define RX_CLKSEL_SSI (0x5 << 20) + +/* 2430 Ratio's */ +/* 2430-Ratio Config 1 */ +#define R1_CLKSEL_L3 (4 << 0) +#define R1_CLKSEL_L4 (2 << 5) +#define R1_CLKSEL_USB (4 << 25) +#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI \ + | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 \ + | R1_CLKSEL_L4 | R1_CLKSEL_L3) +#define R1_CLKSEL_MPU (2 << 0) +#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU +#define R1_CLKSEL_DSP (2 << 0) +#define R1_CLKSEL_DSP_IF (2 << 5) +#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF) +#define R1_CLKSEL_GFX (2 << 0) +#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX +#define R1_CLKSEL_MDM (4 << 0) +#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM + +/* 2430-Ratio Config 2 */ +#define R2_CLKSEL_L3 (6 << 0) +#define R2_CLKSEL_L4 (2 << 5) +#define R2_CLKSEL_USB (2 << 25) +#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI \ + | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 \ + | R2_CLKSEL_L4 | R2_CLKSEL_L3) +#define R2_CLKSEL_MPU (2 << 0) +#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU +#define R2_CLKSEL_DSP (2 << 0) +#define R2_CLKSEL_DSP_IF (3 << 5) +#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF) +#define R2_CLKSEL_GFX (2 << 0) +#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX +#define R2_CLKSEL_MDM (6 << 0) +#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM + +/* 2430-Ratio Boot */ +#define RB_CLKSEL_L3 (1 << 0) +#define RB_CLKSEL_L4 (1 << 5) +#define RB_CLKSEL_USB (1 << 25) +#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI \ + | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 \ + | RB_CLKSEL_L4 | RB_CLKSEL_L3) +#define RB_CLKSEL_MPU (1 << 0) +#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU +#define RB_CLKSEL_DSP (1 << 0) +#define RB_CLKSEL_DSP_IF (1 << 5) +#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF) +#define RB_CLKSEL_GFX (1 << 0) +#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX +#define RB_CLKSEL_MDM (1 << 0) +#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM + +/* 2430 Target modes: Along with each configuration the CPU has several modes + * * which goes along with them. Modes mainly are the addition of descrite DPLL + * * combinations to go along with a ratio. + * */ +/* hardware goverend */ +#define MX_48M_SRC (0 << 3) +#define MX_54M_SRC (0 << 5) +#define MX_APLLS_CLIKIN_12 (3 << 23) +#define MX_APLLS_CLIKIN_13 (2 << 23) +#define MX_APLLS_CLIKIN_19_2 (0 << 23) + +/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */ +/* boot (boot) */ +#define MB_DPLL_MULT (1 << 12) +#define MB_DPLL_DIV (0 << 8) +#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_12) + +#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_13) + +#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_19) + +/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */ + +#define M2_DPLL_MULT_12 (55 << 12) +#define M2_DPLL_DIV_12 (1 << 8) +#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC \ + | M2_DPLL_DIV_12 | M2_DPLL_MULT_12 \ + | MX_APLLS_CLIKIN_12) +/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */ +#define M2_DPLL_MULT_13 (330 << 12) +#define M2_DPLL_DIV_13 (12 << 8) +#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC \ + | M2_DPLL_DIV_13 | M2_DPLL_MULT_13 \ + | MX_APLLS_CLIKIN_13) +#define M2_DPLL_MULT_19 (275 << 12) +#define M2_DPLL_DIV_19 (15 << 8) +#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC \ + | M2_DPLL_DIV_19 | M2_DPLL_MULT_19 \ + | MX_APLLS_CLIKIN_19_2) + +/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */ +#define M3_DPLL_MULT_12 (55 << 12) +#define M3_DPLL_DIV_12 (1 << 8) +#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC \ + | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 \ + | MX_APLLS_CLIKIN_12) +#define M3_DPLL_MULT_13 (330 << 12) +#define M3_DPLL_DIV_13 (12 << 8) +#define M5A_DPLL_MULT_13 (266 << 12) +#define M5A_DPLL_DIV_13 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC \ + | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 \ + | MX_APLLS_CLIKIN_13) +#define M5A_DPLL_MULT_19 (180 << 12) +#define M5A_DPLL_DIV_19 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC \ + | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 \ + | MX_APLLS_CLIKIN_19_2) + +/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */ +#define M5B_DPLL_MULT_12 (50 << 12) +#define M5B_DPLL_DIV_12 (2 << 8) +#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC \ + | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 \ + | MX_APLLS_CLIKIN_12) +#define M5B_DPLL_MULT_13 (200 << 12) +#define M5B_DPLL_DIV_13 (12 << 8) + +#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC \ + | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 \ + | MX_APLLS_CLIKIN_13) +#define M5B_DPLL_MULT_19 (125 << 12) +#define M5B_DPLL_DIV_19 (31 << 8) +#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC \ + | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 \ + | MX_APLLS_CLIKIN_19_2) + +/*high and low operation value */ +#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) +#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) + + +/* set defaults for boot up */ + +#if defined(PRCM_CONFIG_I) /* ARM-330MHz IVA2-330MHz L3-165MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R2_CLKSEL_MPU +# define DSP_DIV R2_CM_CLKSEL_DSP_VAL +# define GFX_DIV R2_CM_CLKSEL_GFX_VAL +# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R1_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_II) /*ARM-100MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV 0x00000002 +# define DSP_DIV 0x00000042 +# define GFX_DIV 0x00000002 +# define BUS_DIV 0x08501046 +# define DPLL_VAL 0x0112CC00 +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#endif + +#endif + +/* lock delay time out */ +#define LDELAY 12000000 +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + + #endif diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h index 7248950..06c4e65 100644 --- a/include/asm-arm/arch-omap24xx/i2c.h +++ b/include/asm-arm/arch-omap24xx/i2c.h @@ -23,8 +23,9 @@ #ifndef _OMAP24XX_I2C_H_ #define _OMAP24XX_I2C_H_ -#define I2C_BASE 0x48070000 -#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ +/* I2C base */ +#define I2C_BASE (OMAP24XX_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP24XX_L4_IO_BASE + 0x72000) #define I2C_REV (I2C_BASE + 0x00) #define I2C_IE (I2C_BASE + 0x04) diff --git a/include/asm-arm/arch-omap24xx/mem.h b/include/asm-arm/arch-omap24xx/mem.h index 42e8ab2..5e0a25c 100644 --- a/include/asm-arm/arch-omap24xx/mem.h +++ b/include/asm-arm/arch-omap24xx/mem.h @@ -153,4 +153,111 @@ typedef enum { # define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24)) #endif /* endif CONFIG_SYS_PRCM_III */ +#if defined(PRCM_CONFIG_II) /* L3 at 100MHz */ + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x0 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 + +#if defined(ASYNC_READ) +# define ONENAND_GPMC_CONFIG1 0x01011201 +# define ONENAND_GPMC_CONFIG2 0x00070800 +# define ONENAND_GPMC_CONFIG3 0x00020200 +# define ONENAND_GPMC_CONFIG4 0x07030803 +# define ONENAND_GPMC_CONFIG5 0x01060909 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +#else +# define ONENAND_GPMC_CONFIG1 0xE5011201 +# define ONENAND_GPMC_CONFIG2 0x00070D00 +# define ONENAND_GPMC_CONFIG3 0x00020300 +# define ONENAND_GPMC_CONFIG4 0x07030D07 +# define ONENAND_GPMC_CONFIG5 0x020B090E +# define ONENAND_GPMC_CONFIG6 0x00000000 +#endif + +#endif + +#if defined(PRCM_CONFIG_III) /* L3 at 100MHz */ +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +#endif /* endif CFG_PRCM_III */ + +#if defined(PRCM_CONFIG_I) /* L3 at 165MHz */ + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +#endif + +/* Board Specific Settings for each of the configurations for chips + * whose values change as per platform. - None currently + */ + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PROC_NAND 2 +#define PISMO_SIBLEY0 3 +#define PISMO_SIBLEY1 4 +#define PISMO_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO_PCMCIA 7 +#define PROC_ONENAND 8 +#define ONENAND_CS2 9 +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + #endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-omap24xx/omap24xx.h b/include/asm-arm/arch-omap24xx/omap24xx.h index 1dec62e..6e1c9e8 100644 --- a/include/asm-arm/arch-omap24xx/omap24xx.h +++ b/include/asm-arm/arch-omap24xx/omap24xx.h @@ -27,96 +27,16 @@ #include <asm/arch/sizes.h> -/* - * 2420 specific Section - */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 -/* #define GP_DEVICE (BIT8|BIT9)FIXME--commented out to make compile--FIXME*/ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - /* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) #define TST_DEVICE 0x0 #define EMU_DEVICE 0x1 #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) -#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) -#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) -#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) -#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) -#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) -#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) -#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) -#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) -#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) -#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) -#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) -#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) -#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) -#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) -# define BURSTCOMPLETE_GROUP7 BIT31 -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 +#define OMAP24XX_SDRC_CS0 0x80000000 +#define OMAP24XX_SDRC_CS1 0xA0000000 #define CMD_NOP 0x0 #define CMD_PRECHARGE 0x1 #define CMD_AUTOREFRESH 0x2 @@ -130,25 +50,6 @@ #define REF_ON_IDLE (0x1 << 6) -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - /* timer regs offsets (32 bit regs) */ #define TIDR 0x0 /* r */ #define TIOCP_CFG 0x10 /* rw */ @@ -167,34 +68,55 @@ #define TCAR2 0x44 /* r */ /* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 #define WWPS 0x34 /* r */ #define WSPR 0x48 /* rw */ #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) +#if defined(CONFIG_OMAP242X) +/* + * 2420 specific Section + */ + +#define OMAP24XX_CM_BASE 0x48008000 +#define OMAP24XX_L4_IO_BASE (0x48000000) + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 +/* #define GP_DEVICE (BIT8|BIT9) FIXME-commented out to make compile--FIXME*/ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +/* UART */ +#define OMAP24XX_UART1 0x4806A000 +#define OMAP24XX_UART2 0x4806C000 +#define OMAP24XX_UART3 0x4806E000 + +#define OMAP24XX_TAP_BASE (0x48014000) +#define OMAP24XX_CTRL_BASE (0x48000000) +#define OMAP24XX_GPMC_BASE (0x6800A000) +#define OMAP24XX_SMS_BASE 0x68008000 +#define OMAP24XX_SDRC_BASE 0x68009000 + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 0x48028000 +#define OMAP24XX_GPT2 0x4802A000 +#define OMAP24XX_GPT3 0x48078000 +#define OMAP24XX_GPT4 0x4807A000 +#define OMAP24XX_GPT5 0x4807C000 +#define OMAP24XX_GPT6 0x4807E000 +#define OMAP24XX_GPT7 0x48080000 +#define OMAP24XX_GPT8 0x48082000 +#define OMAP24XX_GPT9 0x48084000 +#define OMAP24XX_GPT10 0x48086000 +#define OMAP24XX_GPT11 0x48088000 +#define OMAP24XX_GPT12 0x4808A000 /* * H4 specific Section */ @@ -240,7 +162,236 @@ /* Common */ #define LOW_LEVEL_SRAM_STACK 0x4020FFFC +#define PERIFERAL_PORT_BASE 0x480FE003 + + +#elif defined(CONFIG_OMAP243X) /*OMAP243X specific code*/ + +/* GPMC */ +#define OMAP24XX_GPMC_BASE (0x6E000000) +/* SMS */ +#define OMAP24XX_SMS_BASE 0x6C000000 +/* SDRC */ +#define OMAP24XX_SDRC_BASE 0x6D000000 +#define DEBUG_BASE 0x08000000 /* debug board */ +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP243X_CORE_L4_IO_BASE 0x48000000 +#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 +/* PRCM */ +#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) + +/* TAP information */ +#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) + +/* UART */ +#define OMAP24XX_UART1 (OMAP24XX_L4_IO_BASE+0x6a000) +#define OMAP24XX_UART2 (OMAP24XX_L4_IO_BASE+0x6c000) +#define OMAP24XX_UART3 (OMAP24XX_L4_IO_BASE+0x6e000) + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) +#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) +#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) +#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) +#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) +#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) +#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) +#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) +#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) +#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) +#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) +#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) +#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) +#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ +#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +#if (CONFIG_2430) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC #define PERIFERAL_PORT_BASE 0x480FE003 +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) + + +#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +#define LED_REGISTER (DEBUG_BASE+0x40) +#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +#define I2C2_MEMORY_STATUS_REG (DEBUG_BASE+0x10000+0xA) +#define ENHANCED_UI_EE_NAME "750-2038" +#define GDP_MB_EE_NAME "750-2031-3" #endif + +#if defined(CONFIG_POSEIDON) +#define POSEIDON_CS0_BASE 0x00000000 /* OneNAND */ +#define POSEIDON_CS1_BASE 0x08000000 /* ethernet */ +#define POSEIDON_CS2_BASE 0x10000000 /* OneNAND */ +#define POSEIDON_CS3_BASE 0x18000000 /* NOR */ + +#endif /* endif CONFIG_POSEIDON */ + +#endif /******OMAP243X Specific code******/ + +/* CONTROL */ +#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) +#define OMAP24XX_MCR (OMAP24XX_CTRL_BASE + 0x8C) + + +/* TAP information */ +#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP24XX_TAP_BASE+0x208) + +/* GPMC */ +#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) +#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP24XX_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP24XX_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP24XX_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP24XX_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP24XX_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP24XX_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP24XX_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP24XX_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP24XX_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP24XX_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP24XX_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP24XX_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP24XX_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP24XX_GPMC_BASE+0x108) + +#define GPMC_CONFIG_CS0 (OMAP24XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) +#define GPMC_CONFIG_CS1 (OMAP24XX_GPMC_BASE+0x90) +#define GPMC_CONFIG_CS2 (OMAP24XX_GPMC_BASE+0xC0) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +/* SMS */ +#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) +#define SMS_CLASS_ARB0 (OMAP24XX_SMS_BASE+0xD0) +# define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP24XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) + +#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) + +#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) + +#define SDRC_DLLB_STATUS (OMAP24XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + + + +#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) + +#define SDRC_MR_1 (OMAP24XX_SDRC_BASE+0xB4) + +#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) + +#define SDRC_MANUAL_1 (OMAP24XX_SDRC_BASE+0xD8) + + + +/* PRCM */ + +#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) + +/* IVA2 */ +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#endif + diff --git a/include/asm-arm/arch-omap24xx/sys_info.h b/include/asm-arm/arch-omap24xx/sys_info.h index 53c231a..5f3cded 100644 --- a/include/asm-arm/arch-omap24xx/sys_info.h +++ b/include/asm-arm/arch-omap24xx/sys_info.h @@ -53,6 +53,7 @@ typedef struct h4_system_data { #define CPU_2420 0x2420 #define CPU_2422 0x2422 /* 2420 + 64M stacked */ #define CPU_2423 0x2423 /* 2420 + 96M stacked */ +#define CPU_2430 0x2430 #define CPU_2422_ES1 1 #define CPU_2422_ES2 2 @@ -60,19 +61,28 @@ typedef struct h4_system_data { #define CPU_2420_ES2 2 #define CPU_2420_2422_ES1 1 +#define CPU_2430_ES1 1 +#define CPU_2430_ES2 2 +#define CPU_2430_ES2_1_0 3 + #define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_2430_CHIPID 0x0B68A000 #define CPU_24XX_ID_MASK 0x0FFFF000 #define CPU_242X_REV_MASK 0xF0000000 #define CPU_242X_PID_MASK 0x000F0000 #define BOARD_H4_MENELAUS 1 #define BOARD_H4_SDP 2 +#define BOARD_SDP_2430_M1 4 /* pre-T2 platform */ +#define BOARD_SDP_2430_T2 5 /* Triton2 companion chip */ +#define BOARD_GDP_2430_T2 6 /* 2430 GDP Variant */ #define GPMC_MUXED 1 #define GPMC_NONMUXED 0 #define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ #define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 #define WIDTH_8BIT 0x0000 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index cec18d9..47d11c2 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -32,8 +32,8 @@ */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420_APOLLON 1 +#define CONFIG_OMAP242X 1 /* which is in a 2420 */ +#define CONFIG_OMAP242X_APOLLON 1 #define CONFIG_APOLLON 1 #define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */ @@ -100,7 +100,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 +#define CONFIG_SYS_NS16550_COM1 OMAP24XX_UART1 /* * select serial console configuration @@ -193,17 +193,17 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) +#define CONFIG_SYS_MEMTEST_START (OMAP24XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) /* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) +#define CONFIG_SYS_LOAD_ADDR (OMAP24XX_SDRC_CS0) /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) * or by 32KHz clk, or from external sig. This rate is divided by a local * divisor. */ -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 +#define CONFIG_SYS_TIMERBASE OMAP24XX_GPT2 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) @@ -222,9 +222,9 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE SZ_128M -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_SDRAM_2 OMAP24XX_SDRC_CS1 /*----------------------------------------------------------------------- * FLASH and environment organization diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index b0f442f..b312e76 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -33,7 +33,7 @@ */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ +#define CONFIG_OMAP242X 1 /* which is in a 2420 */ #define CONFIG_OMAP2420H4 1 /* and on a H4 board */ /*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ @@ -70,9 +70,11 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* * Hardware drivers @@ -98,7 +100,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 +#define CONFIG_SYS_NS16550_COM1 OMAP24XX_UART1 /* * select serial console configuration @@ -152,7 +154,8 @@ * Board NAND Info. */ #define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ +/* physical address to access nand at CS0*/ +#define CONFIG_SYS_NAND_ADDR 0x04000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -210,13 +217,15 @@ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) - -#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ +#define CONFIG_SYS_MEMTEST_START (OMAP24XX_SDRC_CS0) /*memtest works on*/ +#define CONFIG_SYS_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) +/* default load addr */ +#define CONFIG_SYS_LOAD_ADDR (OMAP24XX_SDRC_CS0) /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. @@ -227,7 +236,7 @@ #define V_PTV 7 /* use with 12MHz/128 */ #endif -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 +#define CONFIG_SYS_TIMERBASE OMAP24XX_GPT2 #define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) @@ -246,25 +255,32 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_SDRAM_2 OMAP24XX_SDRC_CS1 #define PHYS_FLASH_SECT_SIZE SZ_128K #define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ #define PHYS_FLASH_SIZE_1 SZ_32M -#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ +/* same cs, 2 chips in series */ +#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) #define PHYS_FLASH_SIZE_2 SZ_32M /*----------------------------------------------------------------------- * FLASH and environment organization */ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 } +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT (259) +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reserve 1 sector */ +#define CONFIG_SYS_MONITOR_LEN SZ_128K +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE \ + + PHYS_FLASH_SIZE_1 } #ifdef CONFIG_SYS_NAND_BOOT #define CONFIG_ENV_IS_IN_NAND 1 @@ -273,7 +289,9 @@ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE -#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ +/* Environment after Monitor */ +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_BASE \ + + CONFIG_SYS_MONITOR_LEN) #endif /*----------------------------------------------------------------------- @@ -281,12 +299,16 @@ */ #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) +/* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) #define CONFIG_SYS_JFFS2_MEM_NAND diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S index f7ee19f..6f1728e 100644 --- a/onenand_ipl/board/apollon/low_levelinit.S +++ b/onenand_ipl/board/apollon/low_levelinit.S @@ -98,7 +98,7 @@ lowlevel_init: strb r1, [r0] /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE + ldr r0, =OMAP24XX_SDRC_BASE ldr r1, =0x00000010 str r1, [r0, #0x10]

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[U-Boot] [PATCH 1/6] Generic FileName
by Vivek 01 Jul '09

01 Jul '09

Changed name of file omap2420.h to omap24xx.h in include/asm-arm/arch-omap24xx/. Changed the files which are affected by this name change. These files are Apollon board and OMAP2420h4 specific. Signed-off-by: Vivek Dalal <v.dalal(a)samsung.com> --- board/apollon/apollon.c | 2 board/apollon/lowlevel_init.S | 2 board/apollon/mem.c | 2 board/apollon/sys_info.c | 2 board/omap2420h4/lowlevel_init.S | 2 board/omap2420h4/mem.c | 2 board/omap2420h4/omap2420h4.c | 2 board/omap2420h4/sys_info.c | 2 cpu/arm1136/omap24xx/interrupts.c | 2 cpu/arm1136/omap24xx/start.S | 2 include/asm-arm/arch-omap24xx/omap24xx.h | 246 ++++++++++++++++++++++++++++ include/configs/apollon.h | 2 include/configs/omap2420h4.h | 2 onenand_ipl/board/apollon/low_levelinit.S | 2 include/asm-arm/arch-omap24xx/omap2420.h | 246 ---------------------------- diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 8964eba..30d8e31 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -24,7 +24,7 @@ * MA 02111-1307 USA */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mux.h> diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S index 64550f6..d2d9025 100644 --- a/board/apollon/lowlevel_init.S +++ b/board/apollon/lowlevel_init.S @@ -26,7 +26,7 @@ #include <config.h> #include <version.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/arch/mem.h> #include <asm/arch/clocks.h> #include "mem.h" diff --git a/board/apollon/mem.c b/board/apollon/mem.c index 36bf6e9..e56b005 100644 --- a/board/apollon/mem.c +++ b/board/apollon/mem.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mux.h> diff --git a/board/apollon/sys_info.c b/board/apollon/sys_info.c index 26ac9a2..92a5636 100644 --- a/board/apollon/sys_info.c +++ b/board/apollon/sys_info.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mem.h> /* get mem tables */ diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S index 9752fc4..33a49a0 100644 --- a/board/omap2420h4/lowlevel_init.S +++ b/board/omap2420h4/lowlevel_init.S @@ -26,7 +26,7 @@ #include <config.h> #include <version.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/arch/mem.h> #include <asm/arch/clocks.h> diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index c8b4186..719888f 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -20,7 +20,7 @@ */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mux.h> diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 0fe9380..d3dc5f3 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mux.h> diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c index a9f7241..ee5eca7 100644 --- a/board/omap2420h4/sys_info.c +++ b/board/omap2420h4/sys_info.c @@ -20,7 +20,7 @@ */ #include <common.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/mem.h> /* get mem tables */ diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c index a0c535d..d6f370c 100644 --- a/cpu/arm1136/omap24xx/interrupts.c +++ b/cpu/arm1136/omap24xx/interrupts.c @@ -32,7 +32,7 @@ #include <common.h> #include <asm/arch/bits.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #define TIMER_LOAD_VAL 0 diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/start.S index 5f8343f..f39838d 100644 --- a/cpu/arm1136/omap24xx/start.S +++ b/cpu/arm1136/omap24xx/start.S @@ -28,7 +28,7 @@ * MA 02111-1307 USA */ -#include <asm/arch/omap2420.h> +#include <config.h> .globl reset_cpu reset_cpu: diff --git a/include/asm-arm/arch-omap24xx/omap2420.h b/include/asm-arm/arch-omap24xx/omap2420.h deleted file mode 100644 index 0c11bec..0000000 --- a/include/asm-arm/arch-omap24xx/omap2420.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, <www.ti.com> - * Richard Woodruff <r-woodruff2(a)ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include <asm/arch/sizes.h> - -/* - * 2420 specific Section - */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 -/* #define GP_DEVICE (BIT8|BIT9) FIXME -- commented out to make compile -- FIXME */ - -/* L3 Firewall */ -#define A_REQINFOPERM0 0x68005048 -#define A_READPERM0 0x68005050 -#define A_WRITEPERM0 0x68005058 - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* device type */ -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) -#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) -#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) -#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) -#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) -#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) -#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) -#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) -#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) -#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) -#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) -#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) -#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) -#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) -#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) -# define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -#if defined(CONFIG_APOLLON) -#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ -#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ -#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ -#define APOLLON_CS3_BASE 0x18000000 /* NOR */ - -#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) -#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) -#endif /* endif CONFIG_APOLLON */ - -/* Common */ -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif diff --git a/include/asm-arm/arch-omap24xx/omap24xx.h b/include/asm-arm/arch-omap24xx/omap24xx.h index e69de29..1dec62e 100644 --- a/include/asm-arm/arch-omap24xx/omap24xx.h +++ b/include/asm-arm/arch-omap24xx/omap24xx.h @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include <asm/arch/sizes.h> + +/* + * 2420 specific Section + */ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 +/* #define GP_DEVICE (BIT8|BIT9)FIXME--commented out to make compile--FIXME*/ + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + +/* CONTROL */ +#define OMAP2420_CTRL_BASE (0x48000000) +#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) + +/* device type */ +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* TAP information */ +#define OMAP2420_TAP_BASE (0x48014000) +#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP2420_TAP_BASE+0x208) + +/* GPMC */ +#define OMAP2420_GPMC_BASE (0x6800A000) +#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) +#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) + +/* SMS */ +#define OMAP2420_SMS_BASE 0x68008000 +#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) +#define SMS_CLASS_ARB0 (OMAP2420_SMS_BASE+0xD0) +# define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define OMAP2420_SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP2420_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) +#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) +#define OMAP2420_SDRC_CS0 0x80000000 +#define OMAP2420_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2420_UART1 0x4806A000 +#define OMAP2420_UART2 0x4806C000 +#define OMAP2420_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP2420_GPT1 0x48028000 +#define OMAP2420_GPT2 0x4802A000 +#define OMAP2420_GPT3 0x48078000 +#define OMAP2420_GPT4 0x4807A000 +#define OMAP2420_GPT5 0x4807C000 +#define OMAP2420_GPT6 0x4807E000 +#define OMAP2420_GPT7 0x48080000 +#define OMAP2420_GPT8 0x48082000 +#define OMAP2420_GPT9 0x48084000 +#define OMAP2420_GPT10 0x48086000 +#define OMAP2420_GPT11 0x48088000 +#define OMAP2420_GPT12 0x4808A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP2420_CM_BASE 0x48008000 +#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP2420H4) +/* GPMC */ +#ifdef CONFIG_VIRTIO_A /* Pre version B */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#else +# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x08000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#endif + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) +#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#if defined(CONFIG_APOLLON) +#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ +#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ +#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ +#define APOLLON_CS3_BASE 0x18000000 /* NOR */ + +#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) +#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) +#endif /* endif CONFIG_APOLLON */ + +/* Common */ +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +#endif diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 925079d..cec18d9 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -56,7 +56,7 @@ /* uncommnet if you want to use UBI */ #define CONFIG_SYS_USE_UBI -#include <asm/arch/omap2420.h> /* get chip and board defs */ +#include <asm/arch/omap24xx.h> /* get chip and board defs */ #define V_SCLK 12000000 diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 1803b13..b0f442f 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -42,7 +42,7 @@ #define PRCM_CONFIG_II 1 /* #define PRCM_CONFIG_III 1 */ -#include <asm/arch/omap2420.h> /* get chip and board defs */ +#include <asm/arch/omap24xx.h> /* get chip and board defs */ /* On H4, NOR and NAND flash are mutual exclusive. Define this if you want to use NAND diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S index 205170f..f7ee19f 100644 --- a/onenand_ipl/board/apollon/low_levelinit.S +++ b/onenand_ipl/board/apollon/low_levelinit.S @@ -26,7 +26,7 @@ */ #include <config.h> -#include <asm/arch/omap2420.h> +#include <asm/arch/omap24xx.h> #include <asm/arch/mem.h> #include <asm/arch/clocks.h>

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[U-Boot] [PATCH 0/6] Poseidon Board Support
by Vivek 01 Jul '09

01 Jul '09

Hi I have added support for Samsung Poseidon GP Board(OMAP 2430) in U-Boot. [U-Boot][PATCH 1/6] Generic FileName ---- -- Changed name of file omap2420.h to omap24xx.h in include/asm-arm/arch-omap24xx/. -- Changed the files which are affected by this name change. These files are Apollon and OMAP2420h4 board specific. [U-Boot][PATCH 2/6] Generic MacroNames and OMAP2430 Definitions---- -- Made the include/asm-arm/arch-omap24xx/ generic rather then specific to omap2420. So as to make it for family of processor of type omap24xx; changed macros ending with OMAP2420 to OMAP24XX. -- Put the omap2420 specific code in CONFIG_OMAP242X macro and Poseidon Board support in CONFIG_OMAP243X macro. Common code kept out of it. -- Changed the Apollon and omap2420h4 specific .c which were affected due to the above change. [U-Boot][PATCH 3/6] Poseidon Board Support -- Added board/poseidon directory and poseidon board specific files in it. [U-Boot][PATCH 4/6] Poseidon Board Support -- Added include/configs/poseidon.h file. [U-Boot][PATCH 5/6] Poseidon IPL Support -- Added onenand_ipl/board/poseidon directory and onenand IPL specific files for poseidon in it. [U-Boot][PATCH 6/6] Poseidon Compilation -- Changed Makefile to configure and compile for Poseidon Board. I have Apollon and Poseidon boards. I have already tested Apollon board to check Legacy support after my changes. Regards Vivek Dalal

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[U-Boot] ppc-4xx timer application problem
by prathika 01 Jul '09

01 Jul '09

hi all, I am working on PPC440EP based board.I have ported u-boot on the board. I was able to fix the problem of extracting data from the flash and executing it. Now I want to run a timer based application on u-boot. I am expecting periodical interrupts based on my configured value. I have written a timer application but there is no interrupts with respect to my configuration. --I have configured GPT0_COMP6 with 0x120 and CPT0_MASK6 registers with value 0x0. --I disabled the Interrupt mask bit in GPT0_IM register for Compare Timer6. --I have enabled interrupt in GPT0_IE register for Compare Timer6. --I am installing interrupt handler for Compare Timer6 using install_hdlr() function. When I run this application, the behaviour is like this: Interrupts are generated when the GPT0_TBC overflows to a certain value that is not equal to my GPT0_COMP6 value. That is the TBC counts continously, overflows from 0xFFFFFFFF to 0x0 and then there is a interrupt when TBC value is 0x22b. And still the TBC continues to count even though I am writing 0x0 in my interrupt handler, overflows and when again it reaches 0x22b, there is a interrupt generated, and this 0x22b value is not fixed, sometimes its 0x22b and sometimes its 0x220. Some one please help me in this regard and point out where am I going wrong? Is the behaviour I am expecting from the timer right and the timer misbehaving? Or have I not understood it's behaviour properly? Thanks & Regards, Prathika R

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[U-Boot] [PATCH] ppc4xx: Fixed compilation warning in 4xx_enet.c
by Alessio Centazzo 01 Jul '09

01 Jul '09

This patch fixes a compilation warning for some Ethernet PHY-less PPC4xx platforms (440SPE based ones) and a potential compilation error for 440SP platforms (use of undefined 'ethgroup' variable). In the original code and in case of 440SPE platforms, 'ethgroup' is initialized to -1 and never modified. Later in the function, within an #ifdef statement, an 'if statement' executes code only if 'ethgroup' is set to 4, therefore it is harmless to avoid executing the 'if statement' by removing the CONFIG_440SPE from the affected #ifdefs. In case of 440SP platforms with on-board Ethernet PHY, 'ethgroup' is undefined but used (there are not such platforms in the repository yet). All other architectures are not affected by this change. This is the current warning message with a Ethernet PHY-less 440SPE platform build (there is not such platform in the repository yet): 4xx_enet.c: In function 'ppc_4xx_eth_init': 4xx_enet.c:880: warning: unused variable 'ethgroup' Signed-off-by: Alessio Centazzo acpatin(a)yahoo.com --- drivers/net/4xx_enet.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 587605d..c020048 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -870,7 +870,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) defined(CONFIG_405EX) u32 opbfreq; sys_info_t sysinfo; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ +#if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) @@ -1119,7 +1119,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) -- 1.6.0.4

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[U-Boot] [PATCH] ppc4xx: Fixed PPC4xx debug compilation error in uic.c
by Alessio Centazzo 01 Jul '09

01 Jul '09

This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin(a)yahoo.com --- cpu/ppc4xx/uic.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c index a95d1cb..1a370b3 100644 --- a/cpu/ppc4xx/uic.c +++ b/cpu/ppc4xx/uic.c @@ -164,7 +164,7 @@ void pic_irq_enable(unsigned int vec) else if (vec >= 96) mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec)); - debug("Install interrupt for vector %d ==> %p\n", vec, handler); + debug("Enable interrupt vector %d\n", vec); } void pic_irq_disable(unsigned int vec) -- 1.6.0.4

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[U-Boot] [PATCH] xscale: add support for the polaris board
by Stefano Babic 01 Jul '09

01 Jul '09

The Polaris board is based on the TrizepsIV module of Keith & Koep (http://www.keith-koep.com). Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- MAINTAINERS | 5 +++++ MAKEALL | 2 ++ Makefile | 7 ++++++- board/trizepsiv/conxs.c | 22 ++++++++++++---------- include/configs/trizepsiv.h | 25 ++++++++++++++++++++++--- 5 files changed, 47 insertions(+), 14 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 9379c7e..7cc26db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -500,6 +500,11 @@ Rowel Atienza <rowel(a)diwalabs.com> armadillo ARM720T +Stefano Babic <sbabic(a)denx.de> + + polaris xscale + trizepsiv xscale + Dirk Behme <dirk.behme(a)gmail.com> omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC) diff --git a/MAKEALL b/MAKEALL index f4599d6..c127472 100755 --- a/MAKEALL +++ b/MAKEALL @@ -604,7 +604,9 @@ LIST_pxa=" \ innokom \ lubbock \ pleb2 \ + polaris \ pxa255_idp \ + trizepsiv \ wepep250 \ xaeniax \ xm250 \ diff --git a/Makefile b/Makefile index acec1a0..3a77988 100644 --- a/Makefile +++ b/Makefile @@ -3082,8 +3082,13 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +polaris_config \ trizepsiv_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + @mkdir -p $(obj)include + @if [ "$(findstring polaris,$@)" ] ; then \ + echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \ + fi; + @$(MKCONFIG) -a trizepsiv arm pxa trizepsiv wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 5c0eb41..4249e3d 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -44,6 +44,11 @@ extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; extern struct serial_device serial_stuart_device; +#if CONFIG_POLARIS +#define BOOT_CONSOLE "serial_stuart" +#else +#define BOOT_CONSOLE "serial_ffuart" +#endif /* ------------------------------------------------------------------------- */ /* @@ -112,17 +117,14 @@ int board_late_init(void) #if defined(CONFIG_SERIAL_MULTI) char *console=getenv("boot_console"); - if ((strcmp(console,"serial_btuart") == 0) || - (strcmp(console,"serial_stuart") == 0) || - (strcmp(console,"serial_ffuart") == 0)) { - setenv("stdout",console); - setenv("stdin", console); - setenv("stderr",console); - } else { - setenv("stdout", "serial"); - setenv("stdin", "serial"); - setenv("stderr", "serial"); + if ((console == NULL) || (strcmp(console,"serial_btuart") && + strcmp(console,"serial_stuart") && + strcmp(console,"serial_ffuart"))) { + console = BOOT_CONSOLE; } + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); #endif return 0; } diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index bfa7157..fa5aae8 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -239,11 +239,17 @@ #define CONFIG_SYS_GRER1_VAL 0x00000000 #define CONFIG_SYS_GRER2_VAL 0x00000000 #define CONFIG_SYS_GRER3_VAL 0x00000000 -#define CONFIG_SYS_GFER0_VAL 0x00000000 + #define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 #define CONFIG_SYS_GFER3_VAL 0x00000020 +#if CONFIG_POLARIS +#define CONFIG_SYS_GFER0_VAL 0x00000001 +#define CONFIG_SYS_GFER2_VAL 0x00200000 +#else +#define CONFIG_SYS_GFER0_VAL 0x00000000 +#define CONFIG_SYS_GFER2_VAL 0x00000000 +#endif #define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ @@ -259,7 +265,11 @@ #define CONFIG_SYS_MSC0_VAL 0x4df84df0 #define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 +#if CONFIG_POLARIS +#define CONFIG_SYS_MSC2_VAL 0xa2697ff8 +#else #define CONFIG_SYS_MSC2_VAL 0xa26936d4 +#endif #define CONFIG_SYS_MDCNFG_VAL 0x880009C9 #define CONFIG_SYS_MDREFR_VAL 0x20ca201e #define CONFIG_SYS_MDMRS_VAL 0x00220022 @@ -280,7 +290,13 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000000 + +#if CONFIG_POLARIS +#define CONFIG_DM9000_BASE 0x0C800000 +#else +#define CONFIG_DM9000_BASE 0x08000000 +#endif + #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) @@ -312,6 +328,9 @@ /* write flash less slowly */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Unlock to be used with Intel chips */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + /* Flash environment locations */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ -- 1.6.0.4

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