July 2009 - U-Boot

Re: [U-Boot] U-boot && forth kernel
by Frank 03 Jul '09

03 Jul '09

--- On Fri, 7/3/09, Сергей Миронов <ierton(a)gmail.com> wrote: > From: Сергей Миронов <ierton(a)gmail.com> > Subject: [U-Boot] U-boot && forth kernel > To: u-boot(a)lists.denx.de > Date: Friday, July 3, 2009, 5:13 AM > Hello to all! > > We are developing various IP-blocks for sparc' > system-on-chip's. I > have successfully ported u-boot to our board (it was not > too hard, > thanks!) , but now there is an idea to run some > FORTH-kernel for > testing and debugging purposes without any OS. I > tried OpenBIOS > software, but without luck. So my question is - does anyone > have an > experience of launching FORTH as u-boot application? > > Thanks, > Sergey I managed to launch a modified version of Pforth from u-boot a few years ago. I don't see why it would be that difficult for any other variant of Forth.

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[U-Boot] U-boot && forth kernel
by Сергей Миронов 03 Jul '09

03 Jul '09

Hello to all! We are developing various IP-blocks for sparc' system-on-chip's. I have successfully ported u-boot to our board (it was not too hard, thanks!) , but now there is an idea to run some FORTH-kernel for testing and debugging purposes without any OS. I tried OpenBIOS software, but without luck. So my question is - does anyone have an experience of launching FORTH as u-boot application? Thanks, Sergey

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[U-Boot] Porting u-boot to new PPC440EP board
by yangguang3501 03 Jul '09

03 Jul '09

Hi, I use a new board designing based on PPC440EP evaluating board, called yosemite. I use u-boot version 1.3.1. I reduce the SDRAM and Flash size to 128M and 16M, I do the porting works as decribed in th maillist"new board SDRAM conf",which you posted in last year. http://lists.denx.de/pipermail/u-boot/2008-November/042924.html and now face the same problem when u-boot run to trap_init, and get the same error message. When I add blr instruction to the trap_init function, it return but hang befor main loop. Would you like tell me how did you solve the problem , or how can I completely porting u-boot to the new board. Best regards, Yangguang ##########Board configuration deference############ ##Yosemite Cofiguration## FLASH (CS0) 64MBYTE NOR Flash (s29GL512N) SDRAM bank 0- 128MB bank 1- 128MB ## My Board configuration## FLASH (CS0) 16MBYTE NOR Flash (s29GL128N) SDRAM bank 0- 128MB bank 1- NONE #########Error message when run to trap_init######### U-Boot 1.3.1 (Jul 3 2009 - 10:36:26) CPU: AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) I2C boot EEPROM disabled Bootstrap Option E - Boot ROM Location EBC (16 bits) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluatio I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 555k for U-Boot at: 07f75000 Reserving 264k for malloc() at: 07f33000 Reserving 144 Bytes for Board Info at: 07f32f70 Reserving 48 Bytes for Global Data at: 07f32f40 Stack Pointer at: 07f32f28 New Stack Pointer is: 07f32f28 in board_init_f, before relocate_code in board_init_r Now running in RAM - U-Boot at: 07f75000 in board_init_r, before board_early_init_r in board_init_r, after board_early_init_r in board_init_r, after relocate command table in board_init_r, before trap_init Bus Fault @ 0x07f7773c, fixup 0x00000000 Machine Check Exception. Caused by (from msr): regs 07f32e00 Data Read PLB Error Machine Check exception is imprecise NIP: 07F7773C XER: 20000000 LR: 07F7773C REGS: 07f32e00 TRAP: 0200 DEAR: 0000000 0 MSR: 00021000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00 GPR00: 07F77314 07F32EF0 0000051B 07F75000 07F7E1C8 00000000 00000000 07F7773C GPR08: 00000600 00002098 03F940AA 13DE4354 07F32CB8 00000000 07FB4500 07FF5000 GPR16: 00000400 00000000 00000000 00000000 00000000 00000000 00000000 70002000 GPR24: 07F75000 07F32F28 07F32F70 07F35000 07F32F40 07F32F40 07FB46A8 00000000 Call backtrace: 07F7E1C0 07F776B0 machine check ### ERROR ### Please RESET the board ### #########Error message when add blr to the trap_init function######### U-Boot 1.3.1 (Jul 3 2009 - 09:25:59) CPU: AMCC PowerPC 440EP Rev. C at 333.333 MHz (PLB=133, OPB=66, EBC=33 MHz) I2C boot EEPROM disabled Bootstrap Option E - Boot ROM Location EBC (16 bits) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Yosemite - AMCC PPC440EP Evaluation Board, Rev. FF, PCI=66 MHz I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 555k for U-Boot at: 07f75000 Reserving 264k for malloc() at: 0 Reserving 144 Bytes for Board Info at: 07f32f70 Reserving 48 Bytes for Global Data at: 07f32f40 Stack Pointer at: 07f32f28 New Stack Pointer is: 07f32f28 in board_init_f, before relocate_code in board_init_r Now running in RAM - U-Boot at: 07f75000 in board_init_r, before board_early_init_r in board_init_r, after board_early_init_r in board_init_r, after relocate command table in board_init_r, before trap_init in board_init_r, after trap_init FLASH: flash detect cfi fwc addr ff000000 cmd 0 0 8bit x 8 bit fwc addr ff000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000000 cmd 0 0000 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= 0051 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= 0051 5151 fwc addr ff000000 cmd 0 0000 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= 0051 0051 is= cmd 52(R) addr ff000022 is= 0052 0052 is= cmd 59(Y) addr ff000024 is= 0059 0059 ushort addr is at ff000050 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 2 port 16 bits chip 16 bits ushort addr is at ff000026 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000aaa cmd aa 00aa 16bit x 16 bit fwc addr ff000554 cmd 55 0055 16bit x 16 bit fwc addr ff000aaa cmd 90 0090 16bit x 16 bit fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit ushort addr is at ff00002a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x40 addr[2] = 0x0 addr[3] = 0x0 retval = 0x40 ff000020 : 00 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 .Q.R.Y.....@.... ff000030 : 00 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 .......'.6...... ff000040 : 00 07 00 0a 00 00 00 03 00 05 00 04 00 00 00 18 ................ ff000050 : 00 02 00 00 00 05 00 00 00 01 00 7f 00 00 00 00 ................ ff000060 : 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ff000070 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ff000080 : 00 50 00 52 00 49 00 31 00 33 00 10 00 02 00 01 .P.R.I.1.3...... ff000090 : 00 00 00 08 00 00 00 00 00 02 00 b5 00 c5 00 05 ................ manufacturer is 2 manufacturer id is 0x1 device id is 0x7e device id2 is 0x2101 cfi version is 0x3133 size_ratio 1 port 16 bits chip found 1 erase regions long addr is at ff00005a info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x7f addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x0 addr[7] = 0x2 erase_region_count = 128 erase_region_size = 131072 ushort addr is at ff000054 info->portwidth = 2 addr[0] = 0x0 addr[1] = 0x5 addr[2] = 0x0 addr[3] = 0x0 retval = 0x5 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit flash_protect ON: from 0xFFF80000 to 0xFFFBA9FF protect on 124 protect on 125 flash_protect ON: from 0xFFF60000 to 0xFFF7FFFF protect on 123 flash_protect ON: from 0xFFF40000 to 0xFFF41FFF protect on 122 16 MB *** Warning - bad CRC, using default environment PCI: Bus Dev VenId DevId Class Int

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[U-Boot] FW: FW: [PATCH] zlib: updated to v.1.2.3
by Giuseppe CONDORELLI 03 Jul '09

03 Jul '09

Hi Detlev, I'm waiting for the patch approval after having received the mail as below. Are there news about the approval? It is not possible to split the patch because the big chunk is due to only one piece (the zlib.c rework). Thanks for the reply, Giuseppe -----Original Message----- From: u-boot-bounces(a)lists.denx.de [mailto:u-boot-bounces@lists.denx.de] Sent: Monday, June 29, 2009 11:52 AM To: giuseppe.condorelli(a)st.com Subject: Your message to U-Boot awaits moderator approval Your mail to 'U-Boot' with the subject [U-Boot][PATCH] zlib: updated to v.1.2.3 Is being held until the list moderator can review it for approval. The reason it is being held: Message body is too big: 183512 bytes with a limit of 100 KB Either the message will get posted to the list, or you will receive notification of the moderator's decision. If you would like to cancel this posting, please visit the following URL: http://lists.denx.de/mailman/confirm/u-boot/5f429d36a437d83cecb1b68135aaf436 d93b2d07

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[U-Boot] FW: [PATCH] zlib: updated to v.1.2.3
by Giuseppe CONDORELLI 03 Jul '09

03 Jul '09

Hi All, are there some news about the patch in subject? Best regards, Giuseppe

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Re: [U-Boot] [PATCH 2/3 v3] arm: A320: driver for FTRTC010 real time clock
by Po-Yu Chuang 03 Jul '09

03 Jul '09

This patch adds an FTRTC010 driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- drivers/rtc/Makefile | 1 + drivers/rtc/ftrtc010.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/ftrtc010.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 822dc1a..25252b5 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o +COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c new file mode 100644 index 0000000..0489565 --- /dev/null +++ b/drivers/rtc/ftrtc010.c @@ -0,0 +1,126 @@ +/* + * Faraday FTRTC010 Real Time Clock + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#undef DEBUG + +#include <config.h> +#include <common.h> +#include <rtc.h> +#include <asm/io.h> + +struct ftrtc010 { + unsigned int sec; /* 0x00 */ + unsigned int min; /* 0x04 */ + unsigned int hour; /* 0x08 */ + unsigned int day; /* 0x0c */ + unsigned int alarm_sec; /* 0x10 */ + unsigned int alarm_min; /* 0x14 */ + unsigned int alarm_hour; /* 0x18 */ + unsigned int record; /* 0x1c */ + unsigned int cr; /* 0x20 */ +}; + +/* + * RTC Control Register + */ +#define FTRTC010_CR_ENABLE (1 << 0) +#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ + +static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_SYS_RTC_BASE; + +static void ftrtc010_enable (void) +{ + writel (FTRTC010_CR_ENABLE, &rtc->cr); +} + +/* + * return current time in seconds + */ +static unsigned long ftrtc010_time (void) +{ + unsigned long day; + unsigned long hour; + unsigned long minute; + unsigned long second; + unsigned long second2; + + do { + second = readl (&rtc->sec); + day = readl (&rtc->day); + hour = readl (&rtc->hour); + minute = readl (&rtc->min); + second2 = readl (&rtc->sec); + } while (second != second2); + + return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; +} + +/* + * Get the current time from the RTC + */ + +int rtc_get (struct rtc_time *tmp) +{ + unsigned long now; + + debug ("%s(): record register: %x\n", + __func__, readl (&rtc->record)); + + now = ftrtc010_time () + readl (&rtc->record); + + to_tm (now, tmp); + + return 0; +} + +/* + * Set the RTC + */ +int rtc_set (struct rtc_time *tmp) +{ + unsigned long new; + unsigned long now; + + debug ("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + __func__, + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + new = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + now = ftrtc010_time (); + + debug ("%s(): write %lx to record register\n", __func__, new - now); + + writel (new - now, &rtc->record); + + return 0; +} + +void rtc_reset (void) +{ + debug ("%s()\n", __func__); + ftrtc010_enable (); +} -- 1.6.3.3

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[U-Boot] [PATCH 0/4 v2] Clean up the Nomadik board and add OneNand
by Alessandro Rubini 02 Jul '09

02 Jul '09

This patch-set cleans up some glitches in my first submission. I posted it as a single patch and a separate timer patch. The first one is split as JC asked, and the timer patch is there as well since it is conceptually in the same set, although I had no comments on the timer part yet. JC: I didn't split "clean" and "onenand", since the change in partitioning information in the config file is part of introducing onenand. A split would have introduced a never-tested artificial middle version. Alessandro Rubini (4): arm nomadik: rename board to nhk8815 arm nomadik: cleanup reset arm nomadik: allow Nand and OneNand to coexists arm nomadik: use 1000 as HZ value and rewrite timer code Makefile | 10 +- board/st/{nmdk8815 => nhk8815}/Makefile | 2 +- board/st/{nmdk8815 => nhk8815}/config.mk | 0 .../st/{nmdk8815/nmdk8815.c => nhk8815/nhk8815.c} | 4 + board/st/{nmdk8815 => nhk8815}/platform.S | 0 cpu/arm926ejs/nomadik/reset.S | 13 +-- cpu/arm926ejs/nomadik/timer.c | 190 ++++++-------------- doc/{README.nmdk8815 => README.nhk8815} | 10 + include/configs/{nmdk8815.h => nhk8815.h} | 59 ++++--- 9 files changed, 109 insertions(+), 179 deletions(-) rename board/st/{nmdk8815 => nhk8815}/Makefile (98%) rename board/st/{nmdk8815 => nhk8815}/config.mk (100%) rename board/st/{nmdk8815/nmdk8815.c => nhk8815/nhk8815.c} (91%) rename board/st/{nmdk8815 => nhk8815}/platform.S (100%) rename doc/{README.nmdk8815 => README.nhk8815} (75%) rename include/configs/{nmdk8815.h => nhk8815.h} (76%)

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[U-Boot] NAND boot for mpc8536ds
by Stefan Bohne 02 Jul '09

02 Jul '09

Hello, everyone, I have to set up a customized board based on the mpc8536ds which boots from nand flash. I'm new to U-Boot and PowerPCs, but I understand that most of the necessary code is already there in U-Boot and that the mpc8536ds configuration has to be extended to support nand boot. Could you give me some hints as to where to start, which #defines I have to look at or which other board configuration to use as reference? Thanks, Stefan Bohne

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[U-Boot] Is i.MX35 support in U-Boot under development?
by Mark Craske 02 Jul '09

02 Jul '09

There is no i.MX35 support in U-Boot 2009.06 as far as I can see. Is it under development? -- Mark Craske MontaVista Software Ltd

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[U-Boot] [PATCH 1/5]P2020RDB Adds GPIO registers to MPC85xx Memory Map.
by Poonam Aggrwal 02 Jul '09

02 Jul '09

Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> --- include/asm-ppc/immap_85xx.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index db2bdf0..0efef05 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -341,6 +341,15 @@ typedef struct ccsr_pcix { char res11[476]; } ccsr_pcix_t; +typedef struct ccsr_gpio { + uint gpdir; + uint gpodr; + uint gpdat; + uint gpier; + uint gpimr; + uint gpicr; +} ccsr_gpio_t; + #define PCIX_COMMAND 0x62 #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 @@ -1648,6 +1657,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) #define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) -- 1.5.6.3

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