June 2009 - U-Boot

[U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board
by Ilya Yanok 19 Nov '09

19 Nov '09

This patch set adds support for LogicPD i.MX27-LITEKIT development board. It contains support for i.MX27 CPU, support for serial console, FEC ethernet controller, NFC NAND controller and SDHC controller. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com>

10 33

[U-Boot] [PATCH/RFC] Better I2C support for OMAP3
by Hugo Vincent 31 Oct '09

31 Oct '09

Hi everyone, This patch improves I2C support on OMAP3 platforms, including supporting the second and third I2C controllers (mainline only supports the first controller), and supporting writes where alen=0 (i.e. no register address - this was needed for some I2C devices I needed to drive from u-boot). Tested on Gumstix Overo with several I2C devices, on I2C1 and 3. The multi-bus support is mostly from this patch: http://www.beagleboard.org/gitweb/?p=u-boot-arm.git;a=commit;h=52eddcd07c2e… Best regards, Hugo Vincent Signed-off-by: Hugo Vincent <hugo.vincent(a)gmail.com> diff --git a/board/omap3/common/power.c b/board/omap3/common/power.c index 4908e5b..efc5dd4 100644 --- a/board/omap3/common/power.c +++ b/board/omap3/common/power.c @@ -42,6 +42,7 @@ void power_init_r(void) unsigned char byte; #ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_set_bus_num(0); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 16439ac..6332965 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1324,6 +1324,7 @@ U_BOOT_CMD( #endif ); #endif /* CONFIG_I2C_CMD_TREE */ +#if !defined(CONFIG_I2C_CMD_TREE) U_BOOT_CMD( imd, 4, 1, do_i2c_md, \ "i2c memory display", \ @@ -1378,6 +1379,7 @@ U_BOOT_CMD( " (valid chip values 50..57)\n" ); #endif +#endif /* !defined(CONFIG_I2C_CMD_TREE) */ #if defined(CONFIG_I2C_MUX) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 6784603..424f172 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -1,7 +1,7 @@ /* * Basic I2C functions * - * Copyright (c) 2004 Texas Instruments + * Copyright (c) 2004, 2009 Texas Instruments * * This package is free software; you can redistribute it and/or * modify it under the terms of the license found in the file @@ -18,6 +18,7 @@ * * Adapted for OMAP2420 I2C, r-woodruff2(a)ti.com * + * Some additions by Hugo Vincent <hugo.vincent(a)gmail.com> June 2009 */ #include <common.h> @@ -25,40 +24,44 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#ifdef CONFIG_OMAP34XX +#define I2C_NUM_IF 3 +#else +#define I2C_NUM_IF 2 +#endif + static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static i2c_t *i2c = (i2c_t *)I2C_DEFAULT_BASE; + void i2c_init (int speed, int slaveadd) { - u16 scl; - - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); - udelay (50000); + if (readw (&i2c->con) & I2C_CON_EN) { + writew (0, &i2c->con); + udelay (10000); } - /* 12MHz I2C module clock */ - writew (0, I2C_PSC); - speed = speed/1000; /* 100 or 400 */ - scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - writew (scl, I2C_SCLL); - writew (scl, I2C_SCLH); + /* Timings from TRM, tested with scope - 100 kHz standard speed */ + writew (23, &i2c->psc); + writew (13, &i2c->scll); + writew (15, &i2c->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c->oa); + writew (I2C_CON_EN, &i2c->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -70,19 +77,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c- >con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -91,28 +98,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c->con); + while (readw (&i2c->stat) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c->data); #endif udelay (20000); } else { @@ -120,17 +127,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while (readw (&i2c->stat) + || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -143,12 +150,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c->con); /* wait until state change */ status = wait_for_pin (); @@ -156,24 +163,78 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c->data); #endif /* must have enough delay to allow BB bit to go low */ - udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int eout = 200; + + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + writew (0xFFFF, &i2c->stat); + if(--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); + return i2c_error; +} + +/* Write just one byte (no reg offset) */ +static int i2c_write_byte_raw (u8 devaddr, u8 value) +{ + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one bytes */ + writew (1, &i2c->cnt); + /* set slave address */ + writew (devaddr, &i2c->sa); + /* stop bit needed here */ + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c->con); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out 1 byte */ + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); + + status = wait_for_pin (); + + /* must have enough delay to allow BB bit to go low */ + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -183,18 +244,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -205,14 +266,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c->data); #else - readw(I2C_DATA); + readw(&i2c->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c->stat); udelay(1000); }else break; @@ -223,7 +284,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c->oa)) { return res; } @@ -231,27 +292,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c- >con); /* enough delay for the NACK bit set */ - udelay (50000); + udelay (1000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c->stat); /* failue, clear sources*/ + writew (readw (&i2c->con) | I2C_CON_STP, &i2c->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c->stat); return res; } @@ -284,23 +345,34 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + if (alen > 1 || alen < 0) { + printf ("I2C write: addr len %d not supported\n", alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("I2C write: address out of range\n"); return 1; } - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; + if (alen == 1) + for (i = 0; i < len; i++) + { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } + } + else if (alen == 0) + for (i = 0; i < len; i++) + { + if (i2c_write_byte_raw (chip, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } } - } return 0; } @@ -310,17 +382,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); - udelay (50000); + writew(0xFFFF, &i2c->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c->stat); + udelay (1000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -330,7 +402,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -338,8 +410,55 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c->stat)); + writew(0xFFFF, &i2c->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_NUM_IF)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#ifdef CONFIG_OMAP34XX + if (bus == 2) + i2c = (i2c_t *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c = (i2c_t *)I2C_BASE2; + else + i2c = (i2c_t *)I2C_BASE1; + + return 0; +} + +int i2c_get_bus_num(void) +{ +#ifdef CONFIG_OMAP34XX + if (i2c == (i2c_t *)I2C_BASE3) + return 2; + else +#endif + if (i2c == (i2c_t *)I2C_BASE2) + return 1; + else if (i2c == (i2c_t *)I2C_BASE1) + return 0; + else + return -1; +} + +int i2c_get_bus_speed() +{ + return 100000; +} + +int i2c_set_bus_speed(int speed) +{ + printf("Not yet implemented\n"); + return -1; +} + diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index e90db7e..234fddf 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -62,6 +62,9 @@ void twl4030_mmc_config(void) { unsigned char data; + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + data = DEV_GRP_P1; i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1); data = VMMC1_VSEL_30; diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch- omap3/i2c.h index 3937f35..9638abc 100644 --- a/include/asm-arm/arch-omap3/i2c.h +++ b/include/asm-arm/arch-omap3/i2c.h @@ -25,21 +25,24 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) +typedef struct i2c { + unsigned int rev; /* 0x00 */ + unsigned int ie; /* 0x04 */ + unsigned int stat; /* 0x08 */ + unsigned int iv; /* 0x0c */ + unsigned int res1; /* 0x10 */ + unsigned int buf; /* 0x14 */ + unsigned int cnt; /* 0x18 */ + unsigned int data; /* 0x1c */ + unsigned int sysc; /* 0x20 */ + unsigned int con; /* 0x24 */ + unsigned int oa; /* 0x28 */ + unsigned int sa; /* 0x2c */ + unsigned int psc; /* 0x30 */ + unsigned int scll; /* 0x34 */ + unsigned int sclh; /* 0x38 */ + unsigned int systest; /* 0x3c */ +} i2c_t; /* I2C masks */ diff --git a/include/configs/omap3_overo.h b/include/configs/ omap3_overo.h index b2c42fa..d8f7a9e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -103,6 +103,7 @@ "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_I2C_CMD_TREE /* New-style command interface */ #define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_CMD_NAND /* NAND support */ @@ -113,6 +114,7 @@ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1

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[U-Boot] Question about M29W128G CFI QRY bug
by Richard Retanubun 27 Oct '09

27 Oct '09

Hi Stefan, I'm trying to get u-boot 2009.03 on coldfire to boot on flash part M29W128G. I think I am getting hit by this bug in the flash chip http://lists.infradead.org/pipermail/linux-mtd/2008-July/022252.html The debug output is as follows: U-Boot 2009.03dvl-00087-gd53876a-dirty (Apr 09 2009 - 19:00:37) CPU: Freescale ColdFire MCF5270 rev. 1, at 150 MHz Board: Ruggedcom MCF5270 I2C: ready DRAM: 8 MB Top of RAM usable for U-Boot at: 00800000 Reserving 172k for U-Boot at: 007d4000 Reserving 256k for malloc() at: 00794000 Reserving 58 Bytes for Board Info at: 00793fc6 Reserving 56 Bytes for Global Data at: 00793f8e Reserving 64k for boot parameters at: 00783f8e Stack Pointer at: 00783f68 Start relocate of code from ff000400 to 007d4000 Now running in RAM - U-Boot at: 007d4000 FLASH: flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 [snip] Note that we suffer from the same bug, where QRY is not being setup properly. The notes there offers a remedy by sending ff before f0. (or skipping ff altogether). Am I on the right track here and if so, how can I make the same fix in u-boot? Thanks for your time - Richard <Raw debug output> U-Boot 2009.03dvl-00087-gd53876a-dirty (Apr 09 2009 - 19:00:37) CPU: Freescale ColdFire MCF5270 rev. 1, at 150 MHz Board: Ruggedcom MCF5270 I2C: ready DRAM: 8 MB Top of RAM usable for U-Boot at: 00800000 Reserving 172k for U-Boot at: 007d4000 Reserving 256k for malloc() at: 00794000 Reserving 58 Bytes for Board Info at: 00793fc6 Reserving 56 Bytes for Global Data at: 00793f8e Reserving 64k for boot parameters at: 00783f8e Stack Pointer at: 00783f68 Start relocate of code from ff000400 to 007d4000 Now running in RAM - U-Boot at: 007d4000 FLASH: flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000000 cmd ff 00ff 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= ff00 0051 fwc addr ff000aaa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= ff00 0051 fwc addr ff000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr ff000000 cmd ff ffffffff 32bit x 8 bit fwc addr ff000154 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 51515151 fwc addr ff001554 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 51515151 fwc addr ff000000 cmd f0 00f000f0 32bit x 16 bit fwc addr ff000000 cmd ff 00ff00ff 32bit x 16 bit fwc addr ff000154 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00510051 fwc addr ff001554 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00510051 fwc addr ff000000 cmd f0 000000f0 32bit x 32 bit fwc addr ff000000 cmd ff 000000ff 32bit x 32 bit fwc addr ff000154 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00000051 fwc addr ff001554 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00000051 fwrite addr ff000000 cmd f0 fffffffffffffffffffff0 64 bit x 8 bit fwrite addr ff000000 cmd ff ffffffffffffffffffffff 64 bit x 8 bit fwrite addr ff0002a8 cmd 98 ffffffffffffffffffff98 64 bit x 8 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005151515151 fwrite addr ff002aa8 cmd 98 ffffffffffffffffffff98 64 bit x 8 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005151515151 fwrite addr ff000000 cmd f0 00ff00ff00ff00fffffff0 64 bit x 16 bit fwrite addr ff000000 cmd ff 00ff00ff00ff00ffffffff 64 bit x 16 bit fwrite addr ff0002a8 cmd 98 00ff00ff00ff00ffffff98 64 bit x 16 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100510051 fwrite addr ff002aa8 cmd 98 00ff00ff00ff00ffffff98 64 bit x 16 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100510051 fwrite addr ff000000 cmd f0 000000ff000000fffffff0 64 bit x 32 bit fwrite addr ff000000 cmd ff 000000ff000000ffffffff 64 bit x 32 bit fwrite addr ff0002a8 cmd 98 000000ff000000ffffff98 64 bit x 32 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100000051 fwrite addr ff002aa8 cmd 98 000000ff000000ffffff98 64 bit x 32 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100000051 fwrite addr ff000000 cmd f0 00000000000000fffffff0 64 bit x 64 bit fwrite addr ff000000 cmd ff 00000000000000ffffffff 64 bit x 64 bit fwrite addr ff0002a8 cmd 98 00000000000000ffffff98 64 bit x 64 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234000000000051 fwrite addr ff002aa8 cmd 98 00000000000000ffffff98 64 bit x 64 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234000000000051 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFF000400 to 0xFF0231FF flash_protect ON: from 0xFF004000 to 0xFF005FFF *** failed *** Ignoring flash failure, see if we boot In: serial Out: serial Err: serial MAC: ethaddr 00:00:00:00:01:00 U-Boot relocated to 007d4000 Net: FEC0 [PRIME] ### main_loop entered: bootdelay=0

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[U-Boot] Please pull u-boot-i2c.git next branch
by Heiko Schocher 15 Oct '09

15 Oct '09

The following changes since commit 6b8edfde22acc574b5532e9f086e6a7287a9bc78: Wolfgang Denk (1): Prepare v2009.06-rc1 are available in the git repository at: git://git.denx.de/u-boot-i2c.git next Peter Tyser (12): i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE value cpci750: i2c cleanup Marvell: i2c cleanup mpc7448hpc2: Add CONFIG_SYS_I2C_SPEED define tsi108_i2c: Add i2c_init() stub function cm5200: Make function test command names more unique i2c: Create common default i2c_[set|get]_bus_speed() functions i2c: Remove deprecated individual i2c commands i2c: Update references to individual i2c commands cmd_i2c: Clean up i2c command argument parsing cmd_i2c: Clean up trivial helper functions cmd_i2c: Fix i2c help command output when CONFIG_I2C_MUX README | 20 +---- board/Marvell/common/i2c.c | 19 +++-- board/cm5200/cmd_cm5200.c | 18 ++-- board/esd/cpci750/i2c.c | 16 ++-- board/esd/tasreg/tasreg.c | 4 +- common/cmd_eeprom.c | 4 - common/cmd_i2c.c | 176 +++++++++++++------------------------- cpu/arm920t/at91rm9200/i2c.c | 10 -- cpu/mpc512x/i2c.c | 14 --- cpu/mpc8260/i2c.c | 16 ---- cpu/ppc4xx/40x_spd_sdram.c | 4 - cpu/ppc4xx/44x_spd_ddr.c | 4 - cpu/ppc4xx/i2c.c | 14 --- doc/README.ebony | 20 ++-- doc/README.m52277evb | 8 +-- doc/README.m5373evb | 8 +-- doc/README.m54455evb | 8 +-- doc/README.m5475evb | 8 +-- doc/README.ppc440 | 4 +- doc/README.xpedite1k | 6 +- doc/feature-removal-schedule.txt | 12 --- drivers/i2c/soft_i2c.c | 14 --- drivers/i2c/tsi108_i2c.c | 11 ++- include/configs/DU405.h | 1 - include/configs/DU440.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/PMC440.h | 1 - include/configs/SIMPC8313.h | 1 - include/configs/XPEDITE5200.h | 1 - include/configs/XPEDITE5370.h | 1 - include/configs/ads5121.h | 1 - include/configs/at91rm9200ek.h | 1 - include/configs/bubinga.h | 2 +- include/configs/katmai.h | 1 - include/configs/keymile-common.h | 1 - include/configs/kmeter1.h | 1 - include/configs/korat.h | 1 - include/configs/mpc7448hpc2.h | 1 + include/configs/sacsng.h | 6 +- include/configs/sbc8349.h | 1 - include/configs/socrates.h | 1 - include/configs/taihu.h | 2 +- include/i2c.h | 12 ++- 51 files changed, 140 insertions(+), 324 deletions(-) -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] u-boot fails to uncompress a "gzip'ed -9" kernel
by N. van Bolhuis 30 Sep '09

30 Sep '09

A certain powerpc 2.6.28 kernel (which is by default compressed with gzip -9) fails to load with u-boot v2008.10. It results in a machine check stop. I'm testing on a MPC8313-RDB. Btw. the linux-2.6.28/arch/powerpc/boot/wrapper script takes care of compressing with "gzip -9". On my host linux pc I'm using gzip 1.3.5 (2002-09-30). If I manually compress that same kernel with "gzip -8" and generate a uImage, it *does* work. As far as I know my start/load memory addresses are ok. If anybody has any clues, please let me know. more details follow. Here's the full output of when the problem occurs: U-Boot 2008.10 (Jan 19 2009 - 12:21:43) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c3, MPC8313E, Rev: 1.0 at 333.333 MHz, CSB: 166.667 MHz Board: Freescale MPC8313ERDB I2C: ready DRAM: 128 MB Top of RAM usable for U-Boot at: 08000000 Reserving 307k for U-Boot at: 07fb3000 Reserving 520k for malloc() at: 07f31000 Reserving 68 Bytes for Board Info at: 07f30fbc Reserving 104 Bytes for Global Data at: 07f30f54 Stack Pointer at: 07f30f38 New Stack Pointer is: 07f30f38 Now running in RAM - U-Boot at: 07fb3000 FLASH: 8 MB NAND: 32 MiB In: serial Out: serial Err: serial U-Boot relocated to 07fb3000 Net: TSEC0, TSEC1 [PRIME] => run tird Speed: 100, full duplex Using TSEC1 device TFTP from server 10.10.4.142; our IP address is 10.10.77.77 Filename 'uImage'. Load address: 0x2000000 Loading: ################################################################# ##################################################### done Bytes transferred = 1717604 (1a3564 hex) Speed: 100, full duplex Using TSEC1 device TFTP from server 10.10.4.142; our IP address is 10.10.77.77 Filename 'initramfs.igz.uboot'. Load address: 0x1000000 Loading: ################################################################# ################################################################# ########## done Bytes transferred = 2051722 (1f4e8a hex) Speed: 100, full duplex Using TSEC1 device TFTP from server 10.10.4.142; our IP address is 10.10.77.77 Filename 'mpc8313erdb.dtb'. Load address: 0x400000 Loading: # done Bytes transferred = 11130 (2b7a hex) ## Current stack ends at 0x07f30c00 * kernel: cmdline image address = 0x02000000 ## Booting kernel from Legacy Image at 02000000 ... Image Name: Linux-2.6.28wa2 Created: 2009-01-19 11:36:09 UTC Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size: 1717540 Bytes = 1.6 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK kernel data at 0x02000040, len = 0x001a3524 (1717540) * ramdisk: cmdline image address = 0x01000000 ## Loading init Ramdisk from Legacy Image at 01000000 ... Image Name: uboot initramfs Created: 2009-01-12 14:56:02 UTC Image Type: PowerPC Linux RAMDisk Image (gzip compressed) Data Size: 2051658 Bytes = 2 MB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ramdisk start = 0x01000040, ramdisk end = 0x011f4e8a * fdt: cmdline image address = 0x00400000 ## Checking for 'FDT'/'FDT Image' at 00400000 * fdt: raw FDT blob ## Flattened Device Tree blob at 00400000 Booting using the fdt blob at 0x400000 of_flat_tree at 0x00400000 size 0x00002b7a Uncompressing Kernel Image ... U-Boot 2008.10 (Jan 19 2009 - 12:21:43) MPC83XX Reset Status: Check Stop, External/Internal Soft, External/Internal Hard I already applied this patch: http://www.mail-archive.com/u-boot@lists.denx.de/msg06709.html it makes no difference. I also applied this patch: http://www.mail-archive.com/u-boot@lists.denx.de/msg04544.html it makes no difference either. Using "bzip2 --best" gives: Uncompressing Kernel Image ... BUNZIP2: uncompress or overwrite error -3 - must RESET board to recover Using "bzip2 --fast" works, but it takes a long time for u-boot to uncompress the kernel. What's also strange is that some other 2.6.28 kernels (compressed with gzip -9) do work. I probably have some kind of memory error, I don't see it though. Unfortunately the problem doesn't occur when I start debugging it with a jtag debugger (lauterbach). if anybody has any clues, please let me know.

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[U-Boot] [PATCH] tools/netconsole: make a bit more robust and use ncb when possible
by Mike Frysinger 15 Sep '09

15 Sep '09

The netcat utility likes to exit when it receives an empty packet (as it thinks this means EOF). This can easily occur when working with command line editing as this behavior will be triggered when using backspace. Or with tabs and command line completion. Since the local ncb util does not have this "feature" and it supports broadcast udp, default to using that rather than netcat. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/netconsole | 18 +++++++++++++++--- 1 files changed, 15 insertions(+), 3 deletions(-) diff --git a/tools/netconsole b/tools/netconsole index 09c8981..aa30d9b 100755 --- a/tools/netconsole +++ b/tools/netconsole @@ -31,12 +31,24 @@ if [ -z "${ip}" ] || [ -n "$3" ] ; then fi for nc in netcat nc ; do - type ${nc} >/dev/null && break + type ${nc} >/dev/null 2>&1 && break done trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15 echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" stty -icanon -echo intr ^T -${nc} -u -l -p ${port} < /dev/null & -exec ${nc} -u ${ip} ${port} +( +if [ -x ./ncb ] ; then + exec ./ncb ${port} +elif [ -x ${0%/*}/ncb ] ; then + exec ${0%/*}/ncb ${port} +else + while ${nc} -u -l -p ${port} < /dev/null ; do + : + done +fi +) & +pid=$! +${nc} -u ${ip} ${port} +kill $pid 2>/dev/null -- 1.6.1

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[U-Boot] [PATCH] AT91RM9200 BGA port D defines
by Jens Scharsig 11 Sep '09

11 Sep '09

This patch add's the defines for port d I/Os on AT91RM9200 (BGA package) Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 95db017..308dea1 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -634,10 +634,12 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ #define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ + #define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ #define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ #define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ #define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ +#define AT91C_ID_PIOD ((unsigned int) 5) /* PIO port D BGA only */ #define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ #define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ #define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ @@ -730,6 +732,35 @@ typedef struct _AT91S_PDC #define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ #define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ +#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */ +#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */ +#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */ +#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */ +#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */ +#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */ +#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */ +#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */ +#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */ +#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */ +#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */ +#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */ +#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */ +#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */ +#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */ +#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */ +#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */ +#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */ +#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */ +#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */ +#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */ +#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */ +#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */ +#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */ +#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */ +#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */ +#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */ +#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */ + #define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ #define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */

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[U-Boot] [PATCH] usb: musb: drop old musb read/write prototypes
by Mike Frysinger 02 Sep '09

02 Sep '09

These functions are no longer defined, so remove their prototypes. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/usb/musb/musb_core.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index b81c536..f9da3f0 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -307,10 +307,4 @@ extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); extern void write_fifo(u8 ep, u32 length, void *fifo_data); extern void read_fifo(u8 ep, u32 length, void *fifo_data); -/* extern functions */ -extern inline void musb_writew(u32 offset, u16 value); -extern inline void musb_writeb(u32 offset, u8 value); -extern inline u16 musb_readw(u32 offset); -extern inline u8 musb_readb(u32 offset); - #endif /* __MUSB_HDRC_DEFS_H__ */ -- 1.6.3.1

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[U-Boot] [PATCH 0/7][v3] Support for LogicPD i.MX27-LITEKIT development board
by Ilya Yanok 01 Sep '09

01 Sep '09

This patch set adds support for LogicPD i.MX27-LITEKIT development board. It contains support for i.MX27 CPU, support for serial console, FEC ethernet controller, NFC NAND controller and SDHC controller. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com>

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[U-Boot] Large Block USB Flash Drive Problem
by Barnes, Clifton A. 01 Sep '09

01 Sep '09

I have been trying out loading the Linux kernel using a USB flash drive in the u-boot-2009.06-rc2 release and ran into a problem with one of my flash drives. This particular drive has a block size of 2048 while the other drives have block sizes of 512. The drives with a block size of 512 work perfectly. However, the flash drive with a block size of 2048 fails during the 'usb start' command. I traced this issue to the Part_dos.c file and the function test_part_dos. The buffer allocated there is only 512 bytes. When I changed it to 2048, the 'usb start' command worked correctly and found the one storage device connected. This had no adverse affect with the flash drives that were 512 bytes. Should the macro DEFAULT_SECTOR_SIZE be changed to accommodate larger block size usb flash drives? The second problem came when I tried to use the FAT utilities. When I ran 'fatls usb 0', it failed the same way as when the 'usb start' failed before. Naturally, I guessed that it was a buffer size problem again. I was able to trace the issue to the macro SECTOR_SIZE in fat.h. I tried changing it to 2048, however, there is a check right below it that fails if SECTOR_SIZE != FS_BLOCK_SIZE. So, I assume that the support isn't written to handle sector sizes that are different than the FAT block size. However, I went ahead and changed them both to 2048. This fixed the issues with the FAT utilities partly. I was able to run 'fatls usb 0' and it listed the files but also some junk. I'm guessing it was grabbing junk after the files since the block size is too big. I was also able to run 'fatload usb 0 0x22000000 uImage' successfully and boot the kernel successfully. So, I think the fix has to be in the SECTOR_SIZE macro in the fat.h file. Can anyone with expertise in the FAT implementation take a look at supporting different sector sizes for larger block size flash drives? I can send a large block flash drive to someone if they're willing to take a look at this issue and they don't have one of these drives. Thanks, Clifton A Barnes INDesign, LLC cabarnes(a)indesign-llc.com

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