June 2009 - U-Boot

[U-Boot-Users] [PATCH] add explicit bbt creation to commandline
by Harald Welte 17 Feb '10

17 Feb '10

[PATCH] add explicit bbt creation to commandline ("nand createbbt" command) This patch adds user-requested BBT creation. It includes the following changes: - common/cmd_nand.c: move yes/no decision to separate function - do_nand: ask for confirmation for "nand erase" - do_nand: add command "nand createbbt" to erase NAND and create a new BBT Signed-off-by: Werner Almesberger <werner(a)openmoko.org> Signed-off-by: Harald Welte <laforge(a)openmoko.org> --- diff --git a/common/cmd_nand.c b/common/cmd_nand.c index bb46f34..2f41157 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -162,6 +162,17 @@ out: return 0; } +static int yes(void) +{ + char c; + + c = getc(); + if (c != 'y' && c != 'Y') + return 0; + c = getc(); + return c == '\r' || c == '\n'; +} + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i, dev, ret; @@ -231,7 +242,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 && + strcmp(cmd, "createbbt") != 0 ) goto usage; /* the following commands operate on the current device */ @@ -286,13 +298,23 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "are sure of what you are doing!\n" "\nReally scrub this NAND flash? <y/N>\n"); - if (getc() == 'y' && getc() == '\r') { + if (yes()) { opts.scrub = 1; } else { puts("scrub aborted\n"); return -1; } } + else { + if (opts.length == nand->size) { + puts("Really erase everything ? <y/N>\n"); + if (!yes()) { + puts("erase aborted\n"); + return -1; + } + } + } + ret = nand_erase_opts(nand, &opts); printf("%s\n", ret ? "ERROR" : "OK"); @@ -461,6 +483,33 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } + if (strcmp(cmd, "createbbt") == 0) { + struct nand_chip *nand_chip = nand->priv; + nand_erase_options_t opts; + + puts("Create BBT and erase everything ? <y/N>\n"); + if (!yes()) { + puts("createbbt aborted\n"); + return -1; + } + memset(&opts, 0, sizeof(opts)); + opts.length = nand->size; + if (nand_erase_opts(nand, &opts)) { + puts("Erase failed\n"); + return 1; + } + nand_chip->options &= ~NAND_DONT_CREATE_BBT; + puts("Creating BBT. Please wait ..."); + if (nand_default_bbt(nand)) { + puts("\nFailed\n"); + return 1; + } + else { + puts("\n"); + return 0; + } + } + usage: printf("Usage:\n%s\n", cmdtp->usage); return 1; @@ -481,7 +530,8 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n"); + "nand unlock [offset] [size] - unlock section\n" + "nand createbbt - create bad block table\n"); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 27d5988..3fdc25a 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -795,7 +795,8 @@ int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate memory (2bit per block) */ - this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) + this->bbt = kmalloc (len, GFP_KERNEL); if (!this->bbt) { printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); return -ENOMEM; -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

5 16

[U-Boot] [patch 0/2] Some more USB-OHCI bugfixes [V2]
by Remy Bohmer 01 Feb '10

01 Feb '10

This is version 2 of these series! Only patch 1 of 2 has changed, some pedantic Coding Style issues updated that were not detected by Linux/scripts/checkpatch.pl. The USB OHCI init procedure sets the maximum message length the wrong way. A max of 64 bits should not be done by writing '64' in maxpacketsize, but '3'. While fixing this problem it turned out that there is more wrong here in this code it turned out that the wrong bits were checked to determine if the pipe was of type PIPE_INTERRUPT. This series fixes those errors also. I made it 2 seperate patches. The 1st of this series is fully tested and correct on at least the AT91SAM9261 cores. The 2nd patch, however, is created by search-for-the-same-errors-and-replace. I am not able to test that patch, I do not have the boards, so that needs to be done by others or by review. It is clear that code there is buggy in the first place. These patches require my previous series called 'Improve stability USB memory sticks for the common OHCI USB layer.' to be applied before this series. So they should apply on the u-boot-usb git tree. --> git://git.denx.de/u-boot-usb.git I want to mention also, that everytime I look deeper into this code, I find new bugs. It appears that several parts of this code is written with interrupt handling in mind, while we have no interrupt handling at all. Assumptions are done that a interrupt handler does things asynchronous, causing long loops that have no real use at all... So, no guarantees that _all_ problems are solved by now... --

4 8

[U-Boot] [PATCH][RFC] bootm: Added CONFIG_BOOTM_{LINUX, NETBSD, RTEMS}
by Kumar Gala 26 Jan '10

26 Jan '10

Added the ability to config out bootm support for Linux, NetBSD, RTEMS Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Looking for suggestions on how to deal with enabling LINUX, NETBSD, and RTEMS. common/cmd_bootm.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 1b2dfc4..47f9b45 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -103,13 +103,23 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); typedef int boot_os_fn (int flag, int argc, char *argv[], bootm_headers_t *images); /* pointers to os/initrd/fdt */ +#define CONFIG_BOOTM_LINUX 1 +#define CONFIG_BOOTM_NETBSD 1 +#define CONFIG_BOOTM_RTEMS 1 + +#ifdef CONFIG_BOOTM_LINUX extern boot_os_fn do_bootm_linux; +#endif +#ifdef CONFIG_BOOTM_NETBSD static boot_os_fn do_bootm_netbsd; +#endif #if defined(CONFIG_LYNXKDI) static boot_os_fn do_bootm_lynxkdi; extern void lynxkdi_boot (image_header_t *); #endif +#ifdef CONFIG_BOOTM_RTEMS static boot_os_fn do_bootm_rtems; +#endif #if defined(CONFIG_CMD_ELF) static boot_os_fn do_bootm_vxworks; static boot_os_fn do_bootm_qnxelf; @@ -121,12 +131,18 @@ static boot_os_fn do_bootm_integrity; #endif boot_os_fn * boot_os[] = { +#ifdef CONFIG_BOOTM_LINUX [IH_OS_LINUX] = do_bootm_linux, +#endif +#ifdef CONFIG_BOOTM_NETBSD [IH_OS_NETBSD] = do_bootm_netbsd, +#endif #ifdef CONFIG_LYNXKDI [IH_OS_LYNXOS] = do_bootm_lynxkdi, #endif +#ifdef CONFIG_BOOTM_RTEMS [IH_OS_RTEMS] = do_bootm_rtems, +#endif #if defined(CONFIG_CMD_ELF) [IH_OS_VXWORKS] = do_bootm_vxworks, [IH_OS_QNX] = do_bootm_qnxelf, @@ -1161,6 +1177,7 @@ static void fixup_silent_linux () /* OS booting routines */ /*******************************************************************/ +#ifdef CONFIG_BOOTM_NETBSD static int do_bootm_netbsd (int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -1246,6 +1263,7 @@ static int do_bootm_netbsd (int flag, int argc, char *argv[], return 1; } +#endif /* CONFIG_BOOTM_NETBSD*/ #ifdef CONFIG_LYNXKDI static int do_bootm_lynxkdi (int flag, int argc, char *argv[], @@ -1269,6 +1287,7 @@ static int do_bootm_lynxkdi (int flag, int argc, char *argv[], } #endif /* CONFIG_LYNXKDI */ +#ifdef CONFIG_BOOTM_RTEMS static int do_bootm_rtems (int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -1299,6 +1318,7 @@ static int do_bootm_rtems (int flag, int argc, char *argv[], return 1; } +#endif /* CONFIG_BOOTM_RTEMS */ #if defined(CONFIG_CMD_ELF) static int do_bootm_vxworks (int flag, int argc, char *argv[], -- 1.5.5.1

5 28

[U-Boot] [PATCH 1/1] avr32/hsdramc: Move conditional compilation to Makefile
by Jean-Christophe PLAGNIOL-VILLARD 26 Nov '09

26 Nov '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> Cc: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- cpu/at32ap/Makefile | 2 +- cpu/at32ap/hsdramc.c | 3 --- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index e08f273..60899c7 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a START-y += start.o COBJS-y += cpu.o -COBJS-y += hsdramc.o +COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index f74121c..b6eae66 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -21,7 +21,6 @@ */ #include <common.h> -#ifdef CONFIG_SYS_HSDRAMC #include <asm/io.h> #include <asm/sdram.h> @@ -116,5 +115,3 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) return sdram_size; } - -#endif /* CONFIG_SYS_HSDRAMC */ -- 1.6.3.1

4 3

[U-Boot] PATCH Nios2 kernel bootstrap error due to missing processor data cache flush: fix
by Renato Andreola 23 Nov '09

23 Nov '09

From b75bd27f89ac6c105cebb6507cf082b6f5fffc7d Mon Sep 17 00:00:00 2001 From: Renato Andreola <renato.andreola(a)imagos.it> Date: Fri, 10 Apr 2009 12:32:29 +0200 Subject: Nios2: do_boom_linux(): kernel gunzip input data integrity problem due to mi ssing cache flush Added instruction and data caches flush Signed-off-by: Renato Andreola <renato.andreola(a)imagos.it> --- lib_nios2/bootm.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 53fd569..1e8034b 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -2,6 +2,9 @@ * (C) Copyright 2003, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt(a)psyent.com> * + * (C) Copyright 2009, Imagos sas <www.imagos.it> + * Renato Andreola <renato.andreola(a)imagos.it> + * * See file CREDITS for list of people who contributed to this * project. * @@ -24,6 +27,7 @@ #include <common.h> #include <command.h> #include <asm/byteorder.h> +#include <asm/cache.h> int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -31,7 +35,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - + /* flushes data and instruction caches before calling the kernel */ + flush_dcache (0,CONFIG_SYS_DCACHE_SIZE ); + flush_icache (0,CONFIG_SYS_ICACHE_SIZE); /* For now we assume the Microtronix linux ... which only * needs to be called ;-) */ -- 1.5.5

4 11

[U-Boot] [PATCH] at91: Extended soft_i2c driver for AT91SAM9263 SoC
by Daniel Gorsulowski 23 Nov '09

23 Nov '09

While hard_i2c support is not available (see http://lists.denx.de/pipermail/u-boot/2009-March/049751.html), this patch enables soft_i2c on AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- drivers/i2c/soft_i2c.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 59883a5..9a48783 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -34,6 +34,11 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> #endif -- 1.6.1

5 13

[U-Boot-Users] [PATCH] mtd: SPI Flash: Winbond W25X16/WX2532/WX2564 support
by Jason McMullan 22 Nov '09

22 Nov '09

Add support for the Winbond W25X16/32/64 series of SPI Flash devices. --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/spi_flash.c | 5 + drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/mtd/spi/winbond.c | 331 ++++++++++++++++++++++++++++++++++ 4 files changed, 338 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/winbond.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 01b288a..5941235 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libspi_flash.a COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o +COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 35ce822..e81b1be 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -134,6 +134,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, flash = spi_flash_probe_atmel(spi, idcode); break; #endif +#ifdef CONFIG_SPI_FLASH_WINBOND + case 0xef: + flash = spi_flash_probe_winbond(spi, idcode); + break; +#endif #ifdef CONFIG_SPI_FLASH_STMICRO case 0x00: case 0xff: diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index e5f758e..1eacb5c 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -44,3 +44,4 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c new file mode 100644 index 0000000..85e5b80 --- /dev/null +++ b/drivers/mtd/spi/winbond.c @@ -0,0 +1,331 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan(a)netapp.com> + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ + +#define WINBOND_ID_W25X16 0x3015 +#define WINBOND_ID_W25X32 0x3016 +#define WINBOND_ID_W25X64 0x3017 + +#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct winbond_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint8_t nr_blocks; + const char *name; +}; + +struct winbond_spi_flash { + const struct winbond_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct winbond_spi_flash * +to_winbond_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct winbond_spi_flash, flash); +} + +static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { + { + .id = WINBOND_ID_W25X16, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25X16", + }, + { + .id = WINBOND_ID_W25X32, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25X32", + }, + { + .id = WINBOND_ID_W25X64, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25X64", + }, +}; + +static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff }; + + ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) { + debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret); + return -1; + } + + if ((status & WINBOND_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & WINBOND_SR_WIP) == 0) + return 0; + + debug("SF: Timed out on command %02x: %d\n", cmd, ret); + /* Timed out */ + return -1; +} + +/* + * Assemble the address part of a command for Winbond devices in + * non-power-of-two page size mode. + */ +static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset) +{ + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + + /* + * The "extra" space per page is the power-of-two page size + * divided by 32. + */ + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = page_addr >> (16 - page_shift); + cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[2] = byte_addr; +} + +static int winbond_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + winbond_build_address(stm, cmd + 1, offset); + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int winbond_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_W25_PP; + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[3] = byte_addr; + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: Winbond Page Program failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: Winbond page programming timed out\n"); + goto out; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long sector_size; + unsigned int page_shift; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * This function currently uses sector erase only. + * probably speed things up by using bulk erase + * when possible. + */ + + page_shift = stm->params->l2_page_size; + sector_size = (1 << page_shift) * stm->params->pages_per_sector; + + if (offset % sector_size || len % sector_size) { + debug("SF: Erase offset/length not multiple of sector size\n"); + return -1; + } + + len /= sector_size; + cmd[0] = CMD_W25_SE; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + winbond_build_address(stm, &cmd[1], offset + actual * sector_size); + printf("Erase: %02x %02x %02x %02x\n", + cmd[0], cmd[1], cmd[2], cmd[3]); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: Winbond sector erase failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, 2 * CFG_HZ); /* Up to 2 seconds */ + if (ret < 0) { + debug("SF: Winbond sector erase timed out\n"); + goto out; + } + } + + debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n", + len * sector_size, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) +{ + const struct winbond_spi_flash_params *params; + unsigned long page_size; + struct winbond_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { + params = &winbond_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(winbond_spi_flash_table)) { + debug("SF: Unsupported Winbond ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct winbond_spi_flash)); + if (!stm) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = winbond_write; + stm->flash.erase = winbond_erase; + stm->flash.read = winbond_read_fast; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, page_size, stm->flash.size); + + return &stm->flash; +} -- 1.5.4.3

3 6

[U-Boot] [PATCH] Added preliminary support to EHCI USB FSL controller for platform MPC5121
by Rendine Francesco 22 Nov '09

22 Nov '09

Hi all, I would like to submit you a patch to add a preliminary support to EHCI USB Freescale controller integrated on MPC5121. There is still much job to do..for now, this patch add support for USB0 on UTMI phy. I've personally tested this feature with mass storage and it does work. Could be a base for future development..I'm available to possible improvement of source code with your suggestions. Summary: - introduced ehci_hcd_init and ehci_hcd_stop functions for MPC5121 integrated EHCI USB controller - introduced enable of EHCI USB controller in include/mpc5121ads.h - introduced many defines and struct ehci fields to be able to provvide OTG feature Regards, Francesco Rendine. Signed-off-by: Francesco Rendine <francesco.rendine(a)valueteam.com> diff -Naur u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c --- u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-24 18:12:06.000000000 +0200 @@ -54,7 +54,8 @@ #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ CLOCK_SCCR2_I2C_EN | \ CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN) + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_USB1_EN) #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) diff -Naur u-boot.orig/drivers/usb/host/ehci-fsl.c u-boot.usb/drivers/usb/host/ehci-fsl.c --- u-boot.orig/drivers/usb/host/ehci-fsl.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci-fsl.c 2009-06-25 01:14:34.000000000 +0200 @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009, Value Team S.p.A. + * Francesco Rendine, <francesco.rendine(a)valueteam.com> + * * (C) Copyright 2009 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB @@ -30,6 +33,7 @@ #include "ehci.h" #include "ehci-core.h" +#ifndef CONFIG_MPC512X /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -38,34 +42,93 @@ */ int ehci_hcd_init(void) { - struct usb_ehci *ehci; + struct usb_ehci *ehci; - ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; - hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); - hcor = (struct ehci_hcor *)((uint32_t) hccr + - HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - /* Set to Host mode */ - setbits_le32((void *)ehci->usbmode, CM_HOST); + /* Set to Host mode */ + setbits_le32((void *)ehci->usbmode, CM_HOST); - out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); - out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); - /* Init phy */ - if (!strcmp(getenv("usb_phy_type"), "utmi")) - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); - else - out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); + /* Init phy */ + if (!strcmp(getenv("usb_phy_type"), "utmi")) + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + else + out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); - /* Enable interface. */ - setbits_be32((void *)ehci->control, USB_EN); + /* Enable interface. */ + setbits_be32((void *)ehci->control, USB_EN); - out_be32((void *)ehci->prictrl, 0x0000000c); - out_be32((void *)ehci->age_cnt_limit, 0x00000040); - out_be32((void *)ehci->sictrl, 0x00000001); + out_be32((void *)ehci->prictrl, 0x0000000c); + out_be32((void *)ehci->age_cnt_limit, 0x00000040); + out_be32((void *)ehci->sictrl, 0x00000001); + + in_le32((void *)ehci->usbmode); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} +#else +/* + * Initialize SOC FSL EHCI Controller + * + * This code is derived from EHCI FSL USB Linux driver for MPC5121 + * + */ +int ehci_hcd_init(void) +{ + struct usb_ehci *ehci; + u32 temp; - in_le32((void *)ehci->usbmode); + /* Hook the memory mapped registers for EHCI-Controller */ + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)(&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + /* Confgure interface for UTMI_WIDE */ + temp = in_be32(&ehci->isiphyctrl); + out_be32(&ehci->isiphyctrl, temp | PHYCTRL_PHYE | PHYCTRL_PXE); + + temp = in_be32(&ehci->usbgenctrl); + out_be32(&ehci->usbgenctrl, temp | GC_PPP | GC_PFP ); + + /* Workaround: disable ULPI phy */ + temp = 0x60000000 | 0x0C << 16 | 0x20 ; + temp = cpu_to_hc32(temp); + out_be32(&ehci->ulpi_viewpoint, temp); + + /* Configure interrupt */ + temp = ehci_readl(&hcor->or_usbintr); + temp |= (INTR_UE | INTR_UEE | INTR_PCE | INTR_SEE | INTR_AAE); + ehci_writel(&hcor->or_usbintr, temp); + + /* Init phy USB0 to UTMI+ */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW); + temp |= (PORT_PTS_UTMI | PORT_PTS_PTW); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Set to Host mode */ +#ifdef CONFIG_EHCI_DESC_BIG_ENDIAN + setbits_be32(&ehci->usbmode, CM_HOST | ES_BE); +#else + setbits_be32(&ehci->usbmode, CM_HOST); +#endif + return 0; } @@ -75,5 +138,16 @@ */ int ehci_hcd_stop(void) { + u32 temp; + + /* Disable phy USB0 */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW | PORT_PP | PORT_PR); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Unhook struct */ + hccr = hcor = NULL; + return 0; } +#endif diff -Naur u-boot.orig/drivers/usb/host/ehci.h u-boot.usb/drivers/usb/host/ehci.h --- u-boot.orig/drivers/usb/host/ehci.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci.h 2009-06-24 16:13:40.000000000 +0200 @@ -71,6 +71,11 @@ #define STD_ASS (1 << 15) #define STS_HALT (1 << 12) uint32_t or_usbintr; +#define INTR_UE (1 << 0) /* USB interrupt enable */ +#define INTR_UEE (1 << 1) /* USB error interrupt enable */ +#define INTR_PCE (1 << 2) /* Port change detect enable */ +#define INTR_SEE (1 << 4) /* system error enable */ +#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ uint32_t or_frindex; uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; diff -Naur u-boot.orig/include/asm-ppc/immap_512x.h u-boot.usb/include/asm-ppc/immap_512x.h --- u-boot.orig/include/asm-ppc/immap_512x.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/asm-ppc/immap_512x.h 2009-06-24 18:28:29.000000000 +0200 @@ -1228,4 +1228,8 @@ } #endif /* __ASSEMBLY__ */ +#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 +#define CONFIG_SYS_MPC512x_USB_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) + #endif /* __IMMAP_512x__ */ diff -Naur u-boot.orig/include/configs/mpc5121ads.h u-boot.usb/include/configs/mpc5121ads.h --- u-boot.orig/include/configs/mpc5121ads.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/configs/mpc5121ads.h 2009-06-25 01:38:29.000000000 +0200 @@ -342,6 +342,21 @@ #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +/* USB Support */ +#define CONFIG_USB + +#ifdef CONFIG_USB + #define CONFIG_USB_EHCI +#endif + +#ifdef CONFIG_USB_EHCI + #define CONFIG_USB_EHCI_FSL + #define CONFIG_EHCI_MMIO_BIG_ENDIAN + #define CONFIG_EHCI_DESC_BIG_ENDIAN + #define CONFIG_SYS_USB_EHCI_REGS_BASE 0x80004000 + #define CONFIG_EHCI_IS_TDI +#endif + /* * Environment */ @@ -387,6 +402,16 @@ #define CONFIG_ISO_PARTITION #endif /* defined(CONFIG_CMD_IDE) */ +#if defined(CONFIG_USB) +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_SUPPORT_VFAT +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -484,6 +509,7 @@ "rootpath=/opt/eldk/ppc_6xx\n" \ "netdev=eth0\0" \ "consdev=ttyPSC0\0" \ + "usb_phy_type=utmi\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ diff -Naur u-boot.orig/include/usb/ehci-fsl.h u-boot.usb/include/usb/ehci-fsl.h --- u-boot.orig/include/usb/ehci-fsl.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/usb/ehci-fsl.h 2009-06-24 16:22:15.000000000 +0200 @@ -35,12 +35,16 @@ #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) +#define PORT_PTS_PHCD (1 << 23) +#define PORT_PP (1 << 12) +#define PORT_PR (1 << 8) /* USBMODE Register bits */ #define CM_IDLE (0 << 0) #define CM_RESERVED (1 << 0) #define CM_DEVICE (2 << 0) #define CM_HOST (3 << 0) +#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ #define USBMODE_RESERVED_2 (0 << 2) #define SLOM (1 << 3) #define SDIS (1 << 4) @@ -70,7 +74,74 @@ #define PHY_CLK_VALID (1 << 17) #define FSL_SOC_USB_PORTSC2 0x188 + +/* OTG Status Control Register bits */ +#define FSL_SOC_USB_OTGSC 0x1a4 +#define CTRL_VBUS_DISCHARGE (0x1<<0) +#define CTRL_VBUS_CHARGE (0x1<<1) +#define CTRL_OTG_TERMINATION (0x1<<3) +#define CTRL_DATA_PULSING (0x1<<4) +#define CTRL_ID_PULL_EN (0x1<<5) +#define HA_DATA_PULSE (0x1<<6) +#define HA_BA (0x1<<7) +#define STS_USB_ID (0x1<<8) +#define STS_A_VBUS_VALID (0x1<<9) +#define STS_A_SESSION_VALID (0x1<<10) +#define STS_B_SESSION_VALID (0x1<<11) +#define STS_B_SESSION_END (0x1<<12) +#define STS_1MS_TOGGLE (0x1<<13) +#define STS_DATA_PULSING (0x1<<14) +#define INTSTS_USB_ID (0x1<<16) +#define INTSTS_A_VBUS_VALID (0x1<<17) +#define INTSTS_A_SESSION_VALID (0x1<<18) +#define INTSTS_B_SESSION_VALID (0x1<<19) +#define INTSTS_B_SESSION_END (0x1<<20) +#define INTSTS_1MS (0x1<<21) +#define INTSTS_DATA_PULSING (0x1<<22) +#define INTR_USB_ID_EN (0x1<<24) +#define INTR_A_VBUS_VALID_EN (0x1<<25) +#define INTR_A_SESSION_VALID_EN (0x1<<26) +#define INTR_B_SESSION_VALID_EN (0x1<<27) +#define INTR_B_SESSION_END_EN (0x1<<28) +#define INTR_1MS_TIMER_EN (0x1<<29) +#define INTR_DATA_PULSING_EN (0x1<<30) +#define INTSTS_MASK (0x00ff0000) + +#define INTERRUPT_ENABLE_BITS_MASK \ + (INTR_USB_ID_EN | \ + INTR_1MS_TIMER_EN | \ + INTR_A_VBUS_VALID_EN | \ + INTR_A_SESSION_VALID_EN | \ + INTR_B_SESSION_VALID_EN | \ + INTR_B_SESSION_END_EN | \ + INTR_DATA_PULSING_EN) + +#define INTERRUPT_STATUS_BITS_MASK \ + (INTSTS_USB_ID | \ + INTR_1MS_TIMER_EN | \ + INTSTS_A_VBUS_VALID | \ + INTSTS_A_SESSION_VALID | \ + INTSTS_B_SESSION_VALID | \ + INTSTS_B_SESSION_END | \ + INTSTS_DATA_PULSING) + #define FSL_SOC_USB_USBMODE 0x1a8 + +#define USBGENCTRL 0x200 /* NOTE: big endian */ +#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ +#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ +#define GC_PPP (1 << 3) /* Port Power Polarity */ +#define GC_PFP (1 << 2) /* Power Fault Polarity */ +#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ +#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ + +#define ISIPHYCTRL 0x204 /* NOTE: big endian */ +#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ +#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ +#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ +#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ +#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ + #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ @@ -86,43 +157,59 @@ #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 #if defined(CONFIG_MPC83XX) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR #elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#elif defined(CONFIG_MPC512X) +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR #endif + /* * USB Registers */ struct usb_ehci { - u8 res1[0x100]; + u32 id; /* 0x000 - Identification register */ + u32 hwgeneral; /* 0x004 - General hardware parameters */ + u32 hwhost; /* 0x008 - Host hardware parameters */ + u32 hwdevice; /* 0x00C - Device hardware parameters */ + u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ + u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ + u8 res1[0x68]; + u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ + u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ + u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ + u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ + u32 sbuscfg; /* 0x090 - System Bus Interface Control */ + u8 res2[0x6C]; u16 caplength; /* 0x100 - Capability Register Length */ u16 hciversion; /* 0x102 - Host Interface Version */ u32 hcsparams; /* 0x104 - Host Structural Parameters */ u32 hccparams; /* 0x108 - Host Capability Parameters */ - u8 res2[0x14]; + u8 res3[0x14]; u32 dciversion; /* 0x120 - Device Interface Version */ u32 dciparams; /* 0x124 - Device Controller Params */ - u8 res3[0x18]; + u8 res4[0x18]; u32 usbcmd; /* 0x140 - USB Command */ u32 usbsts; /* 0x144 - USB Status */ u32 usbintr; /* 0x148 - USB Interrupt Enable */ u32 frindex; /* 0x14C - USB Frame Index */ - u8 res4[0x4]; + u8 res5[0x4]; u32 perlistbase; /* 0x154 - Periodic List Base - USB Device Address */ u32 ep_list_addr; /* 0x158 - Next Asynchronous List - End Point Address */ - u8 res5[0x4]; + u8 res6[0x4]; u32 burstsize; /* 0x160 - Programmable Burst Size */ u32 txfilltuning; /* 0x164 - Host TT Transmit pre-buffer packet tuning */ - u8 res6[0x8]; + u8 res7[0x8]; u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ - u8 res7[0xc]; + u8 res8[0xc]; u32 config_flag; /* 0x180 - Configured Flag Register */ u32 portsc; /* 0x184 - Port status/control */ - u8 res8[0x20]; + u8 res9[0x1C]; + u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ u32 usbmode; /* 0x1a8 - USB Device Mode */ u32 epsetupstat; /* 0x1ac - End Point Setup Status */ u32 epprime; /* 0x1b0 - End Point Init Status */ @@ -135,15 +222,18 @@ u32 epctrl3; /* 0x1cc - End Point Control 3 */ u32 epctrl4; /* 0x1d0 - End Point Control 4 */ u32 epctrl5; /* 0x1d4 - End Point Control 5 */ - u8 res9[0x228]; + u8 res10[0x28]; + u32 usbgenctrl; /* 0x200 - USB General Control */ + u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ + u8 res11[0x1F8]; u32 snoop1; /* 0x400 - Snoop 1 */ u32 snoop2; /* 0x404 - Snoop 2 */ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ u32 prictrl; /* 0x40c - Priority Control */ u32 sictrl; /* 0x410 - System Interface Control */ - u8 res10[0xEC]; + u8 res12[0xEC]; u32 control; /* 0x500 - Control */ - u8 res11[0xafc]; + u8 res13[0xafc]; }; #endif /* _EHCI_FSL_H */

2 3

[U-Boot] [PATCH] 85xx: Enable the DDR3 SPD support for P2020DS board
by Dave Liu 22 Nov '09

22 Nov '09

* The ELPIDA 2GB unbuffered DDR3 SDRAM DIMMs - EBJ21EE8BAFA-AE-E 600MT/s, 667MT/s and 800MT/s passed on P2020DS * Micron 1GB unbuffered DDR3 SDRAM DIMMs - MT9JSF12872AY-1G4D1 600MT/s, 667MT/s and 800MT/s passed on P2020DS Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley(a)freescale.com> --- board/freescale/p2020ds/ddr.c | 34 ++++++++++++++++------------------ include/configs/P2020DS.h | 6 ++++-- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b9c0cb2..aaff6e8 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -51,27 +51,21 @@ typedef struct { * cpo 2-0x1E (30) */ - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][20] = { { /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 10, 5, 0}, - {681, 850, 2, 1, 12, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 4, 0x1f, 2, 0}, + {334, 400, 2, 4, 0x1f, 2, 0}, + {401, 549, 2, 4, 0x1f, 2, 0}, + {550, 680, 2, 4, 0x1f, 3, 0}, + {681, 850, 2, 4, 0x1f, 4, 0}, + { 0, 333, 1, 4, 0x1f, 2, 0}, + {334, 400, 1, 4, 0x1f, 2, 0}, + {401, 549, 1, 4, 0x1f, 2, 0}, + {550, 680, 1, 4, 0x1f, 3, 0}, + {681, 850, 1, 4, 0x1f, 4, 0} }, }; @@ -127,4 +121,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; + /* + * Disable write leveling + */ + popts->wrlvl_en = 0; } diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index e4119e3..0564242 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -82,8 +82,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -121,6 +121,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -- 1.5.4

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[U-Boot] [PATCH 2/2] 85xx: add the nfsboot/ramboot to default environment
by Dave Liu 22 Nov '09

22 Nov '09

Give the MPC8569MDS board one default environment var. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC8569MDS.h | 72 ++++++++++++++++++++++++------------------ 1 files changed, 41 insertions(+), 31 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..7fd2b56 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -409,46 +409,56 @@ extern unsigned long get_clock_freq(void); * Environment Configuration */ #define CONFIG_HOSTNAME mpc8569mds -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_ROOTPATH /tftpboot +#define CONFIG_BOOTFILE uImage.8569 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:85:69:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:85:69:02 + +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.254 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=u-boot.8569\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.8569\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=dtb.8569\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #endif /* __CONFIG_H */ -- 1.5.4

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