June 2009 - U-Boot

[U-Boot] [PATCH-ARM 2/2] Add support for the Embest SBC2440-II Board
by kevin.morfitt＠fearnside-systems.co.uk 19 Jun '09

19 Jun '09

This is the second of two patches that will add support for the Embest SBC2440-II Board. This one adds the new code for the Embest SBC2440-II Board. Tested on an Embest SBC2440-II Board with u-boot in NOR flash, using tftp to copy kernel and root file system images from a tftp server, programming them into NAND flash and ensuring the kernel boots correctly at re-start. Also, MAKEALL was run for all ARM9 boards and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/embest/sbc2440ii/Makefile | 55 ++++++ board/embest/sbc2440ii/config.mk | 25 +++ board/embest/sbc2440ii/lowlevel_init.S | 219 +++++++++++++++++++++++ board/embest/sbc2440ii/sbc2440ii.c | 109 ++++++++++++ cpu/arm920t/s3c24x0/timer.c | 1 + drivers/mtd/nand/s3c2440_nand.c | 9 +- include/configs/sbc2440ii.h | 299 ++++++++++++++++++++++++++++++++ 10 files changed, 722 insertions(+), 3 deletions(-) create mode 100644 board/embest/sbc2440ii/Makefile create mode 100644 board/embest/sbc2440ii/config.mk create mode 100644 board/embest/sbc2440ii/lowlevel_init.S create mode 100644 board/embest/sbc2440ii/sbc2440ii.c create mode 100644 include/configs/sbc2440ii.h diff --git a/MAINTAINERS b/MAINTAINERS index 9379c7e..39c938e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -578,6 +578,10 @@ Nishanth Menon <nm(a)ti.com> omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) +Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> + + sbc2440ii ARM920T + David Müller <d.mueller(a)elsoft.ch> smdk2410 ARM920T diff --git a/MAKEALL b/MAKEALL index f4599d6..ae95ffa 100755 --- a/MAKEALL +++ b/MAKEALL @@ -519,6 +519,7 @@ LIST_ARM9=" \ omap5912osk \ omap730p2 \ sbc2410x \ + sbc2440ii \ scb9328 \ smdk2400 \ smdk2410 \ diff --git a/Makefile b/Makefile index acec1a0..ddcb1cc 100644 --- a/Makefile +++ b/Makefile @@ -2900,6 +2900,9 @@ omap730p2_cs3boot_config : unconfig sbc2410x_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 +sbc2440ii_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2440ii embest s3c24x0 + scb9328_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx diff --git a/board/embest/sbc2440ii/Makefile b/board/embest/sbc2440ii/Makefile new file mode 100644 index 0000000..f791f39 --- /dev/null +++ b/board/embest/sbc2440ii/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sbc2440ii.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/embest/sbc2440ii/config.mk b/board/embest/sbc2440ii/config.mk new file mode 100644 index 0000000..def11d8 --- /dev/null +++ b/board/embest/sbc2440ii/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# +# Modified for EMBEST SBC2440-II board with S3C2440 (ARM920T) cpu by: +# (C) Copyright 2009 +# Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + +# +# SBC2440-II has 1 bank of 64 MB DRAM +# +# 3000'0000 to 3800'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# +# we load ourself to 33F8'0000 +# +# download area is 3000'0000 + +TEXT_BASE = 0x33F80000 diff --git a/board/embest/sbc2440ii/lowlevel_init.S b/board/embest/sbc2440ii/lowlevel_init.S new file mode 100644 index 0000000..697c2a2 --- /dev/null +++ b/board/embest/sbc2440ii/lowlevel_init.S @@ -0,0 +1,219 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw(a)its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker(a)its.tudelft.nl) + * + * Modified for the Samsung SMDK2410 by + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar(a)sec.samsung.com> + */ + +#define BWSCON 0x48000000 + +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1 << 2) +#define UBLB (0x1 << 3) + +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) +#define BWSCON_VAL ((B1_BWSCON << 4) + (B2_BWSCON << 8) + \ + (B3_BWSCON << 12) + (B4_BWSCON << 16) + \ + (B5_BWSCON << 20) + (B6_BWSCON << 24) + \ + (B7_BWSCON << 28)) + +#define B0_TACS 0x0 +#define B0_TCOS 0x0 +#define B0_TACC 0x7 +#define B0_TCOH 0x0 +#define B0_TAH 0x0 +#define B0_TACP 0x0 +#define B0_PMC 0x0 +#define BANKCON0_VAL ((B0_TACS << 13) + (B0_TCOS << 11) + (B0_TACC << 8) + \ + (B0_TCOH << 6) + (B0_TAH << 4) + (B0_TACP << 2) + \ + B0_PMC) + +#define B1_TACS 0x0 +#define B1_TCOS 0x0 +#define B1_TACC 0x7 +#define B1_TCOH 0x0 +#define B1_TAH 0x0 +#define B1_TACP 0x0 +#define B1_PMC 0x0 +#define BANKCON1_VAL ((B1_TACS << 13) + (B1_TCOS << 11) + (B1_TACC << 8) + \ + (B1_TCOH << 6) + (B1_TAH << 4) + (B1_TACP << 2) + \ + B1_PMC) + +#define B2_TACS 0x0 +#define B2_TCOS 0x0 +#define B2_TACC 0x7 +#define B2_TCOH 0x0 +#define B2_TAH 0x0 +#define B2_TACP 0x0 +#define B2_PMC 0x0 +#define BANKCON2_VAL ((B2_TACS << 13) + (B2_TCOS << 11) + (B2_TACC << 8) + \ + (B2_TCOH << 6) + (B2_TAH << 4) + (B2_TACP << 2) + \ + B2_PMC) + +#define B3_TACS 0x0 /* 0clk */ +#define B3_TCOS 0x3 /* 4clk */ +#define B3_TACC 0x7 /* 14clk */ +#define B3_TCOH 0x1 /* 1clk */ +#define B3_TAH 0x3 /* 4clk */ +#define B3_TACP 0x3 /* 6clk */ +#define B3_PMC 0x0 /* 16data */ +#define BANKCON3_VAL ((B3_TACS << 13) + (B3_TCOS << 11) + (B3_TACC << 8) + \ + (B3_TCOH << 6) + (B3_TAH << 4) + (B3_TACP << 2) + \ + B3_PMC) + +#define B4_TACS 0x0 +#define B4_TCOS 0x0 +#define B4_TACC 0x7 +#define B4_TCOH 0x0 +#define B4_TAH 0x0 +#define B4_TACP 0x0 +#define B4_PMC 0x0 +#define BANKCON4_VAL ((B4_TACS << 13) + (B4_TCOS << 11) + (B4_TACC << 8) + \ + (B4_TCOH << 6) + (B4_TAH << 4) + (B4_TACP << 2) + \ + B4_PMC) + +#define B5_TACS 0x0 +#define B5_TCOS 0x0 +#define B5_TACC 0x7 +#define B5_TCOH 0x0 +#define B5_TAH 0x0 +#define B5_TACP 0x0 +#define B5_PMC 0x0 +#define BANKCON5_VAL ((B5_TACS << 13) + (B5_TCOS << 11) + (B5_TACC << 8) + \ + (B5_TCOH << 6) + (B5_TAH << 4) + (B5_TACP << 2) + \ + B5_PMC) + +#define B6_MT 0x3 /* SDRAM */ +#define B6_TRCD 0x2 +#define B6_SCAN 0x1 /* 9bit */ +#define BANKCON6_VAL ((B6_MT << 15) + (B6_TRCD << 2) + B6_SCAN) + +#define B7_MT 0x3 /* SDRAM */ +#define B7_TRCD 0x2 /* 4clk */ +#define B7_SCAN 0x1 /* 9bit */ +#define BANKCON7_VAL ((B7_MT << 15) + (B7_TRCD << 2) + B7_SCAN) + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define TRP 0x0 /* 2clk */ +#define TRC 0x3 /* 7clk */ +#define TCHR 0x2 /* 3clk */ +#define REFCNT 1259 +#define REFRESH_VAL ((REFEN << 23) + (TREFMD << 22) + (TRP << 20) + \ + (TRC << 18) + (TCHR << 16) + REFCNT) + +/* BANKSIZE parameter */ +#define BURST_EN 1 /* Enable burst mode */ +#define SCKE_EN 1 /* Enable SDRAM power-down mode */ +#define SCLK_EN 1 /* SCLK is active only during the access */ +#define BK67MAP 2 /* 128M/128M */ +#define BANKSIZE_VAL ((BURST_EN << 7) + (SCKE_EN << 5) + \ + (SCLK_EN << 4) + BK67MAP) + +/* MRSRB6 parameter */ +#define WBL6 0 /* Burst */ +#define TM6 0 /* Modem register set */ +#define CL6 3 /* Latency is 3 clocks */ +#define BT6 0 /* Sequential */ +#define BL6 0 +#define MRSRB6_VAL ((WBL6 << 9) + (TM6 << 7) + (CL6 << 4) + \ + (BT6 << 3) + BL6) + +/* MRSRB7 parameter */ +#define WBL7 0 /* Burst */ +#define TM7 0 /* Modem register set */ +#define CL7 3 /* Latency is 3 clocks */ +#define BT7 0 /* Sequential */ +#define BL7 0 +#define MRSRB7_VAL ((WBL7 << 9) + (TM7 << 7) + (CL7 << 4) + \ + (BT7 << 3) + BL7) + +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word BWSCON_VAL + .word BANKCON0_VAL + .word BANKCON1_VAL + .word BANKCON2_VAL + .word BANKCON3_VAL + .word BANKCON4_VAL + .word BANKCON5_VAL + .word BANKCON6_VAL + .word BANKCON7_VAL + .word REFRESH_VAL + .word BANKSIZE_VAL + .word MRSRB6_VAL + .word MRSRB7_VAL diff --git a/board/embest/sbc2440ii/sbc2440ii.c b/board/embest/sbc2440ii/sbc2440ii.c new file mode 100644 index 0000000..d58603a --- /dev/null +++ b/board/embest/sbc2440ii/sbc2440ii.c @@ -0,0 +1,109 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> + * + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <s3c2440.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +static inline void pll_settle_delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0"(loops)); +} + +int board_init(void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + writel(0xFFFFFFFF, &clk_power->LOCKTIME); + + /* configure UPLL */ + writel((CONFIG_SYS_U_MDIV << 12) + (CONFIG_SYS_U_PDIV << 4) + + CONFIG_SYS_U_SDIV, &clk_power->UPLLCON); + + /* some delay between UPLL and MPLL */ + pll_settle_delay(8000); + + /* configure MPLL */ + writel((CONFIG_SYS_M_MDIV << 12) + (CONFIG_SYS_M_PDIV << 4) + + CONFIG_SYS_M_SDIV, &clk_power->MPLLCON); + + /* configure the GPIO */ + writel(CONFIG_SYS_GPACON, &gpio->GPACON); + writel(CONFIG_SYS_GPBCON, &gpio->GPBCON); + writel(CONFIG_SYS_GPBUP, &gpio->GPBUP); + writel(CONFIG_SYS_GPBDAT, &gpio->GPBDAT); + writel(CONFIG_SYS_GPCCON, &gpio->GPCCON); + writel(CONFIG_SYS_GPCUP, &gpio->GPCUP); + writel(CONFIG_SYS_GPDCON, &gpio->GPDCON); + writel(CONFIG_SYS_GPDUP, &gpio->GPDUP); + writel(CONFIG_SYS_GPECON, &gpio->GPECON); + writel(CONFIG_SYS_GPEUP, &gpio->GPEUP); + writel(CONFIG_SYS_GPFCON, &gpio->GPFCON); + writel(CONFIG_SYS_GPFUP, &gpio->GPFUP); + writel(CONFIG_SYS_GPGCON, &gpio->GPGCON); + writel(CONFIG_SYS_GPGUP, &gpio->GPGUP); + writel(CONFIG_SYS_GPHCON, &gpio->GPHCON); + writel(CONFIG_SYS_GPHUP, &gpio->GPHUP); + writel(CONFIG_SYS_GPJCON, &gpio->GPJCON); + writel(CONFIG_SYS_GPJUP, &gpio->GPJUP); + writel(CONFIG_SYS_EXTINT0, &gpio->EXTINT0); + writel(CONFIG_SYS_EXTINT1, &gpio->EXTINT1); + writel(CONFIG_SYS_EXTINT2, &gpio->EXTINT2); + writel(CONFIG_SYS_EINTMASK, &gpio->EINTMASK); + + /* arch number of SBC2440-II Board */ + gd->bd->bi_arch_number = MACH_TYPE_SBC2440II; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 0f6b580..9359f2b 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -187,6 +187,7 @@ ulong get_tbclk(void) tbclk = timer_load_val * 100; #elif defined(CONFIG_SBC2410X) || \ defined(CONFIG_SMDK2410) || \ + defined(CONFIG_SBC2440II) || \ defined(CONFIG_VCMA9) tbclk = CONFIG_SYS_HZ; #else diff --git a/drivers/mtd/nand/s3c2440_nand.c b/drivers/mtd/nand/s3c2440_nand.c index 3328da6..cc92401 100644 --- a/drivers/mtd/nand/s3c2440_nand.c +++ b/drivers/mtd/nand/s3c2440_nand.c @@ -193,18 +193,21 @@ int board_nand_init(struct nand_chip *nand) cfg = S3C2440_NFCONF_TACLS(tacls); cfg |= S3C2440_NFCONF_TWRPH0(twrph0); cfg |= S3C2440_NFCONF_TWRPH1(twrph1); - writel(cfg, &nand->NFCONF); + writel(cfg, &nand_reg->NFCONF); cfg = S3C2440_NFCONT_EN; cfg |= S3C2440_NFCONT_nFCE; - writel(cfg, &nand->NFCONT); + writel(cfg, &nand_reg->NFCONT); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand->NFDATA; + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ + nand->select_chip = s3c2440_nand_select_chip; + nand->chip_delay = 50; + /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2440_hwcontrol; nand->dev_ready = s3c2440_dev_ready; diff --git a/include/configs/sbc2440ii.h b/include/configs/sbc2440ii.h new file mode 100644 index 0000000..26ad15d --- /dev/null +++ b/include/configs/sbc2440ii.h @@ -0,0 +1,299 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * Gary Jennejohn <gj(a)denx.de> + * David Mueller <d.mueller(a)elsoft.ch> + * + * Modified for the friendly-arm SBC-2410X by + * (C) Copyright 2005 + * JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com> + * + * Modified for the Embest SBC2440-II by + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt(a)fearnside-systems.co.uk> + * + * Configuation settings for the friendly-arm SBC-2410X board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IDENT_STRING " for Embest SBC2440-II" + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_SBC2440II 1 /* on an Embest SBC-2440-II Board */ + +/* + * input clock of PLL - the SBC2440-II has 12MHz input clock + */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +/* The PLL values for MPLL = 400MHz, UPLL = 48MHz + The clock frequency ratios are set to 1:4:8 ie: + PCLK = 50MHz + HCLK = 100MHz + FCLK = 400MHz + */ +/* The MPLL values. */ +#define CONFIG_SYS_M_MDIV 0x5C +#define CONFIG_SYS_M_PDIV 1 +#define CONFIG_SYS_M_SDIV 1 + +/* The UPLL values. */ +#define CONFIG_SYS_U_MDIV 0x38 +#define CONFIG_SYS_U_PDIV 2 +#define CONFIG_SYS_U_SDIV 2 + +#undef USE_920T_MMU +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* The GPIO configuration */ +#define CONFIG_SYS_GPACON 0x007FFFFF +#define CONFIG_SYS_GPBCON 0x00055555 +#define CONFIG_SYS_GPBUP 0x000007FF +#define CONFIG_SYS_GPBDAT 0x000001C0 /* Switch on LED1. */ +#define CONFIG_SYS_GPCCON 0xAAAAAAAA +#define CONFIG_SYS_GPCUP 0x0000FFFF +#define CONFIG_SYS_GPDCON 0xAAAAAAAA +#define CONFIG_SYS_GPDUP 0x0000FFFF +#define CONFIG_SYS_GPECON 0xAAAAA800 +#define CONFIG_SYS_GPEUP 0x00001FFF +#define CONFIG_SYS_GPFCON 0x000055AA +#define CONFIG_SYS_GPFUP 0x000000FF +#define CONFIG_SYS_GPGCON 0xFD95FFBA +#define CONFIG_SYS_GPGUP 0x0000FFFF +#define CONFIG_SYS_GPHCON 0x0002FAAA +#define CONFIG_SYS_GPHUP 0x000007FF +#define CONFIG_SYS_GPJCON 0x02FAAAAA +#define CONFIG_SYS_GPJUP 0x00001FFF +#define CONFIG_SYS_EXTINT0 0x22222222 +#define CONFIG_SYS_EXTINT1 0x22222222 +#define CONFIG_SYS_EXTINT2 0x22222222 +#define CONFIG_SYS_EINTMASK 0x00FFFFF0 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* + * size in bytes reserved for initial data + */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x19000300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * select serial console configuration + */ +#define CONFIG_S3C24X0_SERIAL +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2440-II */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_JFFS2_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=sbc2440-II-nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=sbc2440-II-nand:2m(kernel),62m(rootfs)" +#define CONFIG_EXTRA_ENV_SETTINGS "autostart=yes" + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS \ +"noinitrd root=/dev/mtdblock1 rootfstype=jffs2 init=/linuxrc console=ttySAC0" +#define CONFIG_LOADADDR 30008000 +/*#define CONFIG_BOOTFILE "elinos-lart" */ +#define CONFIG_BOOTCOMMAND "nboot 30008000 0 0" +/*#define CONFIG_NFSBOOTCOMMAND NFS_BOOTARGS*/ + +#if defined(CONFIG_CMD_KGDB) +/* + * speed to run kgdb serial port + */ +#define CONFIG_KGDB_BAUDRATE 115200 +/* + * which serial port to use + */ +#define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "[ SBC2440-II ]# " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x30000000 +#define CONFIG_SYS_MEMTEST_END 0x33F00000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CONFIG_SYS_HZ 1562500 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +/*----------------------------------------------------------------------- + * FLASH and environment and organization + */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x00200000 /* 2MB */ +#define CONFIG_SYS_MAX_FLASH_SECT (35) +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE - CONFIG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) + +/*----------------------------------------------------------------------- + * NAND flash settings + */ +#if defined(CONFIG_CMD_NAND) + #define CONFIG_NAND_S3C2440 + #define CONFIG_SYS_NAND_BASE 0x4e00000c + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define SECTORSIZE 512 +/* #define CONFIG_S3C2440_NAND_HWECC*/ +#endif /* CONFIG_CMD_NAND */ + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#else +#define CONFIG_AUTO_COMPLETE +#endif + +/*----------------------------------------------------------------------- + * USB settings + */ +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x49000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sbc2440-II" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#endif /* __CONFIG_H */ -- 1.6.0.6

2 1

[U-Boot] [PATCH] arm nomadik: use 1000 as HZ value and rewrite timer code
by Alessandro Rubini 19 Jun '09

19 Jun '09

From: Alessandro Rubini <rubini(a)unipv.it> This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. Signed-off-by: Alessandro Rubini <rubini(a)unipv.it> Acked-by: Andrea Gallo <andrea.gallo(a)stericsson.com> --- cpu/arm926ejs/nomadik/timer.c | 190 +++++++++++----------------------------- include/configs/nhk8815.h | 2 +- 2 files changed, 53 insertions(+), 139 deletions(-) diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 2870d24..3618c4a 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -1,20 +1,5 @@ /* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * (C) Copyright 2009 Alessandro Rubini * * See file CREDITS for list of people who contributed to this * project. @@ -38,145 +23,74 @@ #include <common.h> #include <asm/io.h> -#define TIMER_LOAD_VAL 0xffffffff +/* + * Registers in the MTU block -- same as <mach/mtu.h> in linux +*/ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20) -static ulong timestamp; -static ulong lastdec; +/* + * The timer is a decrementer, we'll left it free running at 2.4MHz. + * We have 2.4 ticks per microsecond and an overflow in almost 30min + */ +#define TIMER_CLOCK (24*100*1000) +#define COUNT_TO_USEC(x) ((x)*5/12) /* overflows at 6min */ +#define USEC_TO_COUNT(x) ((x)*12/5) /* overflows at 6min */ +#define TICKS_PER_HZ (TIMER_CLOCK/CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x)/TICKS_PER_HZ) + +/* macro to read the 32 bit timer: since it decrements, we invert read value */ +#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) -/* nothing really to do with interrupts, just starts up a counter. */ +/* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) { - /* Load timer with initial value */ - writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16); - - /* - * Set timer to be enabled, free-running, no interrupts, 256 divider, - * 32-bit, wrap-mode - */ - writel(0x8a, CONFIG_SYS_TIMERBASE + 24); - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, + CONFIG_SYS_TIMERBASE + MTU_CR(0)); + reset_timer(); return 0; } -/* - * timer without interrupts - */ +/* Restart counting from 0 */ void reset_timer(void) { - reset_timer_masked(); + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ } +/* Return how many HZ passed since "base" */ ulong get_timer(ulong base) { - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - timestamp = t; + ulong res = TICKS_TO_HZ(READ_TIMER()) - base; + return res; } -/* delay x useconds AND perserve advance timstamp value */ +/* Delay x useconds */ void udelay(unsigned long usec) { - ulong tmo, tmp; - - if (usec >= 1000) { - /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */ - tmo /= 1000; /* finish normalize. */ - } else { - /* small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000 * 1000); - } - - tmp = get_timer(0); /* get current timestamp */ - if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */ - reset_timer_masked(); /* reset to 0, set lastdec value */ - else - tmo += tmp; - - while (get_timer_masked() < tmo) - /* nothing */ ; -} - -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked(void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* move stamp fordward */ - timestamp += lastdec - now; - } else { - /* - * An overflow is expected. - * nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked(unsigned long usec) -{ - ulong tmo; - - if (usec >= 1000) { - /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */ - tmo /= 1000; /* finish normalize. */ - } else { - /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - reset_timer_masked(); - /* set "advancing" timestamp to 0, set lastdec vaule */ - - while (get_timer_masked() < tmo) - /* nothing */ ; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; + ulong ini, end; - tbclk = CONFIG_SYS_HZ; - return tbclk; + ini = READ_TIMER(); + end = ini + USEC_TO_COUNT(usec); + while ((signed)(end - READ_TIMER()) > 0) + ; } diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index bf1a915..3e2e09f 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -96,7 +96,7 @@ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ /* timing informazion */ -#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ +#define CONFIG_SYS_HZ 1000 /* Mandatory... */ #define CONFIG_SYS_TIMERBASE 0x101E2000 /* serial port (PL011) configuration */ -- 1.6.0.2

1 0

[U-Boot] [PATCH] [PATCH v2] remove _IO_BASE and KSEG1ADDR from board configuration files
by Timur Tabi 19 Jun '09

19 Jun '09

The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet driver, but the code that used that macro was removed over a year ago, so board configuration files no longer need to define it. The _IO_BASE macro is also automatically defined to 0 if it isn't already set, so there's no need to define that macro either in the board configuration files. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/configs/HIDDEN_DRAGON.h | 4 +--- include/configs/M5253DEMO.h | 1 - include/configs/M5253EVBE.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/MPC8349ITX.h | 7 ------- include/configs/MPC8536DS.h | 6 ------ include/configs/MPC8544DS.h | 6 ------ include/configs/MPC8572DS.h | 6 ------ include/configs/MPC8610HPCD.h | 4 ---- include/configs/MPC8641HPCN.h | 4 ---- include/configs/MVBLM7.h | 2 -- include/configs/P2020DS.h | 6 ------ include/configs/PN62.h | 2 -- include/configs/mpc7448hpc2.h | 4 ---- include/configs/r2dplus.h | 2 -- 15 files changed, 1 insertions(+), 55 deletions(-) diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index f6777b9..251fe67 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -103,9 +103,7 @@ #define PCI_ENET1_MEMADDR 0x81000000 #define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) + /* Make sure the ethaddr can be overwritten TODO: Remove this on final product */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 50b3a03..5e86e4c 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -85,7 +85,6 @@ # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -# define _IO_BASE 0 #endif #define CONFIG_NET_MULTI 1 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index cf8b773..df6970c 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define _IO_BASE 0 #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 101dced..87f3a73 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -180,7 +180,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#define _IO_BASE 0 /* Realtime clock */ #define CONFIG_MCFRTC diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f2e574b..d4d3256 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -360,16 +360,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ #endif -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR 0x00000000 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9e00b89..7085d28 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -427,12 +427,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 59cfde6..1d8fecf 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -340,12 +340,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689..c7385e4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -484,12 +484,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1091043..2f40ef4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -280,10 +280,6 @@ #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) -#define _IO_BASE 0x00000000 - /* controller 1, Base address 0xa000 */ #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb..de2cf1a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -348,10 +348,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 - #ifdef CONFIG_PHYS_64BIT /* * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9675205..ac8cb57 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -193,8 +193,6 @@ #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 -#define _IO_BASE 0x00000000 - #define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 3 diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26..443bc40 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -517,12 +517,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 562c5c3..dd95b85 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -133,8 +133,6 @@ #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ #define CONFIG_PCNET_79C973 -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ - /* * Start addresses for the final memory configuration diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 7d42155..4f98ba4 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -124,8 +124,6 @@ /* Networking Configuration */ -#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */ - #define CONFIG_TSI108_ETH #define CONFIG_TSI108_ETH_NUM_PORTS 2 @@ -303,8 +301,6 @@ #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */ -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - /* PCI Config Space mapping */ #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */ #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 6fa1eaf..37d4fff 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -123,7 +123,5 @@ */ #define CONFIG_NET_MULTI #define CONFIG_RTL8139 -#define _IO_BASE 0x00000000 -#define KSEG1ADDR(x) (x) #endif /* __CONFIG_H */ -- 1.6.0.6

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[U-Boot] u-boot & gdb
by Paul Thomas 19 Jun '09

19 Jun '09

I've been using gdb with u-boot via openocd. I'm sure others are doing something similar, but I did a quick entry on what I'm doing. Maybe someone else will find it usefull. http://openhardware.wordpress.com/2009/06/19/u-boot-gdb/ thanks, Paul

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[U-Boot] [PATCH] fsl: remove _IO_BASE and KSEG1ADDR from board configuration files
by Timur Tabi 19 Jun '09

19 Jun '09

The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet driver, but the code that used that macro was removed over a year ago, so board configuration files no longer need to define it. The _IO_BASE macro is also automatically defined to 0 if it isn't already set, so there's no need to define that macro either in the board configuration files. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/configs/MPC8349ITX.h | 7 ------- include/configs/MPC8536DS.h | 6 ------ include/configs/MPC8544DS.h | 6 ------ include/configs/MPC8572DS.h | 6 ------ include/configs/MPC8610HPCD.h | 4 ---- include/configs/MPC8641HPCN.h | 4 ---- include/configs/P2020DS.h | 6 ------ 7 files changed, 0 insertions(+), 39 deletions(-) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index f2e574b..d4d3256 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -360,16 +360,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ #endif -#define _IO_BASE 0x00000000 /* points to PCI I/O space */ - #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR 0x00000000 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9e00b89..7085d28 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -427,12 +427,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 59cfde6..1d8fecf 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -340,12 +340,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2aba689..c7385e4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -484,12 +484,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 1091043..2f40ef4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -280,10 +280,6 @@ #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) -#define _IO_BASE 0x00000000 - /* controller 1, Base address 0xa000 */ #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb..de2cf1a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -348,10 +348,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 - #ifdef CONFIG_PHYS_64BIT /* * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index a39ff26..443bc40 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -517,12 +517,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #undef CONFIG_TULIP #define CONFIG_RTL8139 -#ifdef CONFIG_RTL8139 -/* This macro is used by RTL8139 but not defined in PPC architecture */ -#define KSEG1ADDR(x) (x) -#define _IO_BASE 0x00000000 -#endif - #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS -- 1.6.0.6

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[U-Boot] how to build a U-Boot forU-boot for STR710FZ2T6
by Ansujit 19 Jun '09

19 Jun '09

Hi, I have a ARM board STR710FZ2T6, and I want to build u-boot for it, so I downloaded the latest u-boot source,but it has not included STR710FZ2T6.So can anyone tell me how to modify u-boot for STR710FZ2T6. -- View this message in context: http://www.nabble.com/how-to-build-a-U-Boot-forU-boot-for-STR710FZ2T6-tp241… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Marvell Kirkwood newbie question GPIO functions
by Dieter Kiermaier 19 Jun '09

19 Jun '09

Hello everybody out there, first off all - thanks to everyone from the u-boot community for this helpful piece of code :) Could somebody give me a short overview of the plans regarding the u-boot port of the Kirkwood arch (e.g. Sheevaplug board)? Currently I'm using the u-boot from git.marvell.com which has first board support for sheevaplug. I'm working on a custom hardware design but as a starting point the sheevaplug seems to work well. Sadly there is no generic gpio support - at least I couldn't find it. Are there any plans to support a driver for this feature? I'm willing to contribute some code if someone guides me a bit? Thanks in advance, Dieter

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[U-Boot] [PATCH v4 0/6] MX31: NAND boot for PDK boards.
by Ulrich Gerster 19 Jun '09

19 Jun '09

Hi everybody and especially developers of i.MX31 NAND boot patches, I wrote an e-mail yesterday asking about the need of the mx31_nand.c file in drivers/mtd/nand/ folder. Since nobody answerd I tried to review the development of the latest patch "[PATCH v4 0/6] MX31: NAND boot for PDK boards." historically. It's probably a stupid question but for me as a u-boot newbe it would be very helpful. I started in August 2008 where I found the first patch called "[PATCH RFC 0/5] Add NAND Support..." and later two patches with the same title and the prefix [PATCH v2 0/6] and [PATCH v3 0/6] from Magnus Lilja. In October Mr. Assis posted a patch regarding to this topic aswell. In December and January Maxim Artamonov postet a patches to introduce NAND SPL support. In April then another series of patches from Magnus Lilja were posted with the title "[RFC 0/5] MX31: NAND boot for phyCORE and PDK boards." I think based on this in April version 2 and and in June now version 3 and 4 were posted by Magnus Lilja. As I can see the latest patch includes all the necessary code from the previous patches. So no other patch has to be applied to boot u-boot from a NAND Flash on a board with the i.MX31 ? But I had a very hard time doing this review and I'm not 100% sure if I'm correct Would be very nice if someone could tell me if I'm right and if not tell me what I need more to boot from a NAND flash. Thank you very mutch, Ulrich Gerster

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Re: [U-Boot] How to port uboot Marvell PXA320 Zylonite board
by Prafulla Wadaskar 19 Jun '09

19 Jun '09

> -----Original Message----- > From: sadanand.tavadare(a)wipro.com > [mailto:sadanand.tavadare@wipro.com] > Sent: Friday, June 19, 2009 2:02 PM > To: Prafulla Wadaskar > Subject: RE: How to port uboot Marvell PXA320 Zylonite board > > Hi Prafulla > > We did "make zylonite_config" and generated .bin file for uboot. > Is it Ok to download this .bin file into PXA Zylonite board directly On kirkwood platform, it is NOT, the u-boot.bin needs further processing to create flashable bin for NANDF or SF This code is not currently part of u-boot Similarly, I don't think you can use the same binary to flash on the on-board flash? the board maintainer can answer this better way :-) Regards.. Prafulla . . > > Thanks > Sada > > > > -----Original Message----- > From: Prafulla Wadaskar [mailto:prafulla@marvell.com] > Sent: Friday, June 19, 2009 1:32 PM > To: Sadanand Tavadare (WT01 - PES-Medical-HealthCare); > u-boot(a)lists.denx.de > Subject: RE: How to port uboot Marvell PXA320 Zylonite board > > > > > -----Original Message----- > > From: u-boot-bounces(a)lists.denx.de > > [mailto:u-boot-bounces@lists.denx.de] On Behalf Of > > sadanand.tavadare(a)wipro.com > > Sent: Thursday, June 18, 2009 1:42 PM > > To: u-boot(a)lists.denx.de > > Subject: [U-Boot] How to port uboot Marvell PXA320 Zylonite board > > > > Hi > > > > Please let me know anybody ported uboot on Marvell PXA320 Zylonite > > board. > Hi, > Not for PXA, but I have done it for Marvell Kirkwood SoCs Any > way, how I can help you? > > Regards.. > Prafulla . . > > Please do not print this email unless it is absolutely necessary. > > The information contained in this electronic message and any > attachments to this message are intended for the exclusive > use of the addressee(s) and may contain proprietary, > confidential or privileged information. If you are not the > intended recipient, you should not disseminate, distribute or > copy this e-mail. Please notify the sender immediately and > destroy all copies of this message and any attachments. > > WARNING: Computer viruses can be transmitted via email. The > recipient should check this email and any attachments for the > presence of viruses. The company accepts no liability for any > damage caused by any virus transmitted by this email. > > www.wipro.com >

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[U-Boot] How to port uboot Marvell PXA320 Zylonite board
by sadanand.tavadare＠wipro.com 19 Jun '09

19 Jun '09

Hi Please let me know anybody ported uboot on Marvell PXA320 Zylonite board. Thanks Sada Please do not print this email unless it is absolutely necessary. The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com

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