April 2009 - U-Boot

[U-Boot] Pull request - net
by Ben Warren 24 Apr '09

24 Apr '09

Wolfgang, The following changes since commit 7ee38c044ca5041d3378d6507580ea4ec344af96: David Brownell (1): fix DaVinci NS16550_REG_SIZE regression are available in the git repository at: git://git.denx.de/u-boot-net.git master Michael Zaidman (1): NetLoop initialization bug Timur Tabi (1): net: fix ULI 526x macro usage in netdev.h include/netdev.h | 2 +- net/net.c | 63 +++-------------------------------------------------- 2 files changed, 5 insertions(+), 60 deletions(-)

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[U-Boot] Grant
by Fondation De France 24 Apr '09

24 Apr '09

Congratulation for your $1,350,000.00 as grant from the Fondation De France and ECOWAS. You are to send us the following details so that we can proceed to process your grant. Name: Address: Occupation: Sex: Tel. And send to Mr Patrice Williams (fdf014(a)yahoo.com.hk) Sincerely, Mrs. Claudia Lauren Announcer.

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[U-Boot] (no subject)
by John Tobias 24 Apr '09

24 Apr '09

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[U-Boot] REF NO: UKL/74-A0802742009.
by reaz＠duet.ac.bd 24 Apr '09

24 Apr '09

Congratulations!!! Your Email Account have been picked as the winner of a lump sum pay out of £1,230,310 GBP (One Million Two Hundred and Thirty Thousand Three Hundred and Ten Pounds Sterling ) in cash credited to REF NO: UKL/74-A0802742009. To file for your claim, please Contact our Fiduciary Agent below for Verification. Contact Person: Mr. Cooper Butler, E-mail: (cgnlcooperbutler25(a)live.com) Telephone: ( +447045746304 ) WINNERS VERIFICATION REQUIREMENTS. 1.FULL NAMES:___ 2.ADDRESS:___ 3.City____ 4.State____ 5.Country____ 6.SEX:____ 7.AGE:___ 8.OCCUPATION:___ 9.TELEPHONE NUMBER:____ 10. CHOOSE YOUR CLAIMS OPTION. (1) COURIER DELIVERY (2) BANK TRANSFER Mrs. Cynthia Reazlers ON-LINE COORDINATOR, THE CAMELOT GROUP, OPERATORS OF THE UK NATIONAL LOTTERY

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[U-Boot] Booting uImage on the mx31
by alfred steele 24 Apr '09

24 Apr '09

Hi, I am using an uImage generated by LTIB . I am not sure how the ideal uImage is generated for the PDK board. I try booting this uimage from RAM and then load it at 80008000. It gets stuck after "done, booting the kernel." Please see the bootup messages below. Any hints? I hope with, 0x80008000 as the load address on the MX31, you eliminate the cause of one probable failure, overlay memory with the existing code on RAM e.g. existing u-boot and the compressed kernel image mc911x: MAC 92:92:92:bb:bb:bb TFTP from server 206.44.18.25; our IP address is 206.44.18.31 Filename 'uImage_spin2'. Load address: 0x80800000 Loading: ################################################################# ################################################# done Bytes transferred = 1665060 (196824 hex) ## Booting kernel from Legacy Image at 80800000 ... Image Name: Linux-2.6.24-140-g68eb4b4 Created: 2009-04-23 3:28:44 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1664996 Bytes = 1.6 MB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK Loading Kernel Image ... OK OK Starting kernel ... Uncompressing Linux............................................................. ............................................... done, booting the kernel. <IT freezes here> Thanks, Alfred.

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[U-Boot] [PATCH 0/7] Remove individual I2C commands and cleanup
by Peter Tyser 24 Apr '09

24 Apr '09

This patch series removes the "individual" I2C commands (and the CONFIG_I2C_CMD_TREE define) and migrates all boards to the newer "tree style" I2C commands. A small amount of cleanup was performed before and after removing the individual commands. Peter Tyser (7): cm5200: Make function test command names more unique cmd_i2c: Create common default i2c_[set|get]_bus_speed() functions cmd_i2c: Remove deprecated individual i2c commands cmd_i2c: Update references to individual i2c commands cmd_i2c: Clean up i2c command argument parsing cmd_i2c: Clean up trivial helper functions cmd_i2c: Fix i2c help command output when CONFIG_I2C_MUX README | 20 +---- board/cm5200/cmd_cm5200.c | 18 ++-- board/esd/tasreg/tasreg.c | 4 +- common/cmd_i2c.c | 176 +++++++++++++------------------------- cpu/arm920t/at91rm9200/i2c.c | 10 -- cpu/mpc512x/i2c.c | 14 --- cpu/mpc8260/i2c.c | 13 --- cpu/ppc4xx/i2c.c | 14 --- doc/README.ebony | 20 ++-- doc/README.m52277evb | 8 +-- doc/README.m5373evb | 8 +-- doc/README.m54455evb | 8 +-- doc/README.m5475evb | 8 +-- doc/README.ppc440 | 4 +- doc/README.xpedite1k | 6 +- doc/feature-removal-schedule.txt | 12 --- drivers/i2c/soft_i2c.c | 14 --- drivers/i2c/tsi108_i2c.c | 2 +- include/configs/DU405.h | 1 - include/configs/DU440.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/PMC440.h | 1 - include/configs/SIMPC8313.h | 1 - include/configs/XPEDITE5200.h | 1 - include/configs/XPEDITE5370.h | 1 - include/configs/ads5121.h | 1 - include/configs/at91rm9200ek.h | 1 - include/configs/bubinga.h | 2 +- include/configs/katmai.h | 1 - include/configs/keymile-common.h | 1 - include/configs/kmeter1.h | 1 - include/configs/korat.h | 1 - include/configs/sacsng.h | 6 +- include/configs/sbc8349.h | 1 - include/configs/socrates.h | 1 - include/configs/taihu.h | 2 +- 44 files changed, 99 insertions(+), 293 deletions(-)

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[U-Boot] [PATCH] mpc83xx: MPC8360ERDK: fix environment offset configuration bug
by Anatolij Gustschin 24 Apr '09

24 Apr '09

The size of U-Boot binary for MPC8360ERDK increased (> 2 flash sectors now), so 'saveenv' will partially overwrite U-Boot in flash and will brick the board. This patch moves environment offset to fourth flash sector. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- include/configs/MPC8360ERDK.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index f7ebdaa..1670809 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -339,7 +339,7 @@ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x20000 #else /* CONFIG_SYS_RAMBOOT */ -- 1.5.3.3

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[U-Boot] NAND on mpc8360erdk
by Renaud barbier 24 Apr '09

24 Apr '09

I am in the middle of NAND debugging on a MPC8544 based system. In the following code for the mpc8360erdk, why is there the instruction "out_8(upm->io_addr, 0x0);" in the for loop. Is that board specific? static void upm_setup(struct fsl_upm *upm) { int i; /* write upm array */ out_be32(upm->mxmr, MxMR_OP_WARR); for (i = 0; i < 64; i++) { out_be32(upm->mdr, upm_array[i]); out_8(upm->io_addr, 0x0); } /* normal operation */ out_be32(upm->mxmr, MxMR_OP_NORM); while (in_be32(upm->mxmr) != MxMR_OP_NORM) eieio(); }

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[U-Boot] [PATCH v7] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 23 Apr '09

23 Apr '09

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported default and router port vlan config supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code v5: updated as per review comments for v3 code moved to drivers/net/phy/ vlan_init changed to vlan_config and platform specific v6: mutichip related alias moved to header file vlan_config functions renamed as port_vlan_config mv_switch_88f61xx_init renamed as mv88f61xx_switch_initialization the function prototype for same is added in netdev.h v7: minor updates as per v6 review feedback RD_PHY/WR_PHY macros defined and used in the code drivers/net/phy/Makefile | 1 + drivers/net/phy/mv88e61xx.c | 298 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/mv88e61xx.h | 86 +++++++++++++ include/netdev.h | 1 + 4 files changed, 386 insertions(+), 0 deletions(-) create mode 100644 drivers/net/phy/mv88e61xx.c create mode 100644 drivers/net/phy/mv88e61xx.h diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 4fe3b05..3b92614 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libphy.a COBJS-$(CONFIG_BITBANGMII) += miiphybb.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c new file mode 100644 index 0000000..100934f --- /dev/null +++ b/drivers/net/phy/mv88e61xx.c @@ -0,0 +1,298 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include "mv88e61xx.h" + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { + printf("Error..could not read PHY dev address\n"); + return; + } + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); + } + /* Set CPU port VID to 0x1 */ + RD_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0xfff; + reg |= 0x1; + WR_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0xc000; + WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { + /* + * all any port can send frames to all other ports + * ref: sec 3.2.1.1 of datasheet + */ + reg |= 0x03f; + reg &= ~(1 << prt); + } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { + /* + * all other ports can send frames to CPU port only + * ref: sec 3.2.1.2 of datasheet + */ + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + } + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + RD_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + WR_PHY(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + RD_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + WR_PHY(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + /* ports 2,3,4 not available */ + swconfig->ports_enabled &= 0x023; + } + + /* Port based VLANs configuration */ + if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) + || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) + mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + else { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + WR_PHY(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + WR_PHY(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + RD_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + WR_PHY(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h new file mode 100644 index 0000000..8cc4798 --- /dev/null +++ b/drivers/net/phy/mv88e61xx.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#include <miiphy.h> + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88e61xx_cfg_vlan { + MV88E61XX_VLANCFG_DEFAULT, + MV88E61XX_VLANCFG_ROUTER +}; + +enum mv88e61xx_cfg_rgmiid { + MV88E61XX_RGMII_DELAY_DIS, + MV88E61XX_RGMII_DELAY_EN +}; + +enum mv88e61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88e61xx_config { + char *name; + enum mv88e61xx_cfg_vlan vlancfg; + enum mv88e61xx_cfg_rgmiid rgmii_delay; + enum mv88e61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +static int mv88e61xx_busychk_multic(u32 devaddr); +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); +#define WR_PHY mv88e61xx_wr_phy +#define RD_PHY mv88e61xx_rd_phy +#else +#define WR_PHY miiphy_write +#define RD_PHY miiphy_read +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +#endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index 2794ddd..f7a7db1 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -59,6 +59,7 @@ int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc8220_fec_initialize(bd_t *bis); int mpc82xx_scc_enet_initialize(bd_t *bis); +int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); int natsemi_initialize(bd_t *bis); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); -- 1.5.3.4

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[U-Boot] PAYMENT PROCESSING FORM
by Mrs Caroline Bryan 23 Apr '09

23 Apr '09

You have been award for a grant prize of 1,000,000 GBP on the on going Global award 2009 Promo, for your prize contact email:uknl220@googlemail.com Names:............ Address:.............. Country:................. Age:.......... Sex:.............. Phone/cellphone........ Mrs Caroline Brya

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